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| v850es/kj2 32-bit single-chip microcontrollers hardware printed in japan document no. u17702ej1v0ud00 (1st edition) date published october 2005 n cp(k) preliminary user?s manual pd70f3733 pd70f3734 2005
preliminary user?s manual u17702ej1v0ud 2 [memo] preliminary user?s manual u17702ej1v0ud 3 1 2 3 4 voltage application waveform at input pin waveform distortion due to input noise or a reflected wave may cause malfunction. if the input of the cmos device stays in the area between v il (max) and v ih (min) due to noise, etc., the device may malfunction. take care to prevent chattering noise from entering the device when the input level is fixed, and also in the transition period when the input level passes through the area between v il (max) and v ih (min). handling of unused input pins unconnected cmos device inputs can be cause of malfunction. if an input pin is unconnected, it is possible that an internal input level may be generated due to noise, etc., causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd via a resistor if there is a possibility that it will be an output pin. all handling related to unused pins must be judged separately for each device and according to related specifications governing the device. precaution against esd a strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it when it has occurred. environmental control must be adequate. when it is dry, a humidifier should be used. it is recommended to avoid using insulators that easily build up static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work benches and floors should be grounded. the operator should be grounded using a wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with mounted semiconductor devices. status before initialization power-on does not necessarily define the initial status of a mos device. immediately after the power source is turned on, devices with reset functions have not yet been initialized. hence, power-on does not guarantee output pin levels, i/o settings or contents of registers. a device is not initialized until the reset signal is received. a reset operation must be executed immediately after power-on for devices with reset functions. power on/off sequence in the case of a device that uses different power supplies for the internal operation and external interface, as a rule, switch on the external power supply after switching on the internal power supply. when switching the power supply off, as a rule, switch off the external power supply and then the internal power supply. use of the reverse power on/off sequences may result in the application of an overvoltage to the internal elements of the device, causing malfunction and degradation of internal elements due to the passage of an abnormal current. the correct power on/off sequence must be judged separately for each device and according to related specifications governing the device. input of signal during power off state do not input signals or an i/o pull-up power supply while the device is not powered. the current injection that results from input of such a signal or i/o pull-up power supply may cause malfunction and the abnormal current that passes in the device at this time may cause degradation of internal elements. input of signals during the power off state must be judged separately for each device and according to related specifications governing the device. notes for cmos devices 5 6 preliminary user?s manual u17702ej1v0ud 4 caution: pd70f3733 and 70f3734 use superflash ? technology licensed from silicon storage technology, inc. minicube is a registered trademark of nec electronics corporation in japan and germany. eeprom is a trademark of nec electronics corporation. superflash is a registered trademark of silicon st orage technology, inc. in several countries including the united states and japan. the information contained in this document is being issued in advance of the production cycle for the product. the parameters for the product may change before final production or nec electronics corporation, at its own discretion, may withdraw the product prior to its production. not all products and/or types are available in every country. please check with an nec electronics sales representative for availability and additional information. no part of this document may be copied or reproduced in any form or by any means without the prior written consent of nec electronics. nec electronics assumes no responsibility for any errors that may appear in this document. nec electronics does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of nec electronics products listed in this document or any other liability arising from the use of such products. no license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec electronics or others. descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. the incorporation of these circuits, software and information in the design of a customer's equipment shall be done under the full responsibility of the customer. nec electronics assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. while nec electronics endeavors to enhance the quality, reliability and safety of nec electronics products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. to minimize risks of damage to property or injury (including death) to persons arising from defects in nec electronics products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment and anti-failure features. nec electronics products are classified into the following three quality grades: "standard", "special" and "specific". the "specific" quality grade applies only to nec electronics products developed based on a customer-designated "quality assurance program" for a specific application. the recommended applications of an nec electronics products depend on its quality grade, as indicated below. customers must check the quality grade of each nec electronics product before using it in a particular application. "standard": computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots. "special": transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support). "specific": aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. the quality grade of nec electronics products is "standard" unless otherwise expressly specified in nec electronics data sheets or data books, etc. if customers wish to use nec electronics products in applications not intended by nec electronics, they must contact an nec electronics sales representative in advance to determine nec electronics' willingness to support a given application. (note) (1) "nec electronics" as used in this statement means nec electronics corporation and also includes its majority-owned subsidiaries. (2) "nec electronics products" means any product developed or manufactured by or for nec electronics (as defined above). ? ? ? ? ? ? ? m5d 02. 11-1 preliminary user?s manual u17702ej1v0ud 5 regional information ? device availability ? ordering information ? product release schedule ? availability of related technical literature ? development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, ac supply voltages, and so forth) ? network requirements in addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. [global support] http://www.necel.com/en/support/support.html nec electronics america, inc. (u.s.) santa clara, california tel: 408-588-6000 800-366-9782 nec electronics hong kong ltd. hong kong tel: 2886-9318 nec electronics hong kong ltd. seoul branch seoul, korea tel: 02-558-3737 nec electronics shanghai ltd. shanghai, p.r. china tel: 021-5888-5400 nec electronics taiwan ltd. taipei, taiwan tel: 02-2719-2377 nec electronics singapore pte. ltd. novena square, singapore tel: 6253-8311 j05.6 n ec electronics (europe) gmbh duesseldorf, germany tel: 0211-65030 ? sucursal en espa?a madrid, spain tel: 091-504 27 87 vlizy-villacoublay, france tel: 01-30-67 58 00 ? succursale fran?aise ? filiale italiana milano, italy tel: 02-66 75 41 ? branch the netherlands eindhoven, the netherlands tel: 040-265 40 10 ? tyskland filial taeby, sweden tel: 08-63 87 200 ? united kingdom branch milton keynes, uk tel: 01908-691-133 some information contained in this document may vary from country to country. before using any nec electronics product in your application, piease contact the nec electronics office in your country to obtain a list of authorized representatives and distributors. they will verify: preliminary user?s manual u17702ej1v0ud 6 preface readers this manual is intended for users who wish to understand the functions of the v850es/kj2 and design applicati on systems using the v850es/kj2. purpose this manual is intended to give users an under standing of the hardw are functions of the v850es/kj2 shown in the organization below. organization this manual is divided into two parts: hardware (this manual) and architecture ( v850es architecture user?s manual ). hardware architecture ? pin functions ? cpu function ? on-chip peripheral functions ? flash memory programming ? electrical specifications ? data types ? register set ? instruction format and instruction set ? interrupts and exceptions ? pipeline operation how to read this manual it is assumed that the readers of this manual have general knowledge in the fields of electrical engineering, logic circuits, and microcontrollers. to find the details of a register where the name is known refer to appendix b register index . to understand the details of an instruction function refer to the v850es architecture user?s manual . register format the name of the bit whose number is in angle brackets (<>) in the figure of the register format of each register is defined as a reserved word in the device file. to understand the overall f unctions of the v850es/kj2 read this manual according to the contents . to know the electrical spec ifications of the v850es/kj2 refer to chapter 28 electrical specifications (target) . the ?yyy bit of the xxx register? is described as the ?xxx.yyy bit? in this manual. note with caution that even if ?xxx.yyy? is descri bed as is in a program, however, the compiler/assembler cannot recognize it correctly. preliminary user?s manual u17702ej1v0ud 7 conventions data significance: higher digits on the left and lower digits on the right active low representation: xxx (ove rscore over pin or signal name) memory map address: higher addresses on the top and lower addresses on the bottom note : footnote for item marked with note in the text caution : information requiring particular attention remark : supplementary information numeric representation: binary ... xxxx or xxxxb decimal ... xxxx hexadecimal ... xxxxh prefix indicating power of 2 (address space, memory capacity): k (kilo): 2 10 = 1,024 m (mega): 2 20 = 1,024 2 g (giga): 2 30 = 1,024 3 related documents the related documents indicated in this publication may include preliminary versions. however, preliminary versions are not marked as such. documents related to v850es/kj2 document name document no. v850es architecture user?s manual u15943e v850es/kj2 hardware user?s manual this manual documents related to developm ent tools (user?s manuals) document name document no. operation u17293e c language u17291e assembly language u17292e ca850 ver. 3.00 c compiler package link directives u17294e pm+ ver. 6.00 project manager u17178e id850qb ver. 3.10 integrated debugger operation u17435e sm850 ver. 2.50 system simulator operation u16218e sm850 ver. 2.00 or later system simulator external part user open interface specification u14873e basics u13430e installation u17419e technical u13431e rx850 ver. 3.20 or later real-time os task debugger u17420e basics u13773e installation u17421e technical u13772e rx850 pro ver. 3.20 real-time os task debugger u17422e az850 ver. 3.30 system performance analyzer u17423e pg-fp4 flash memory programmer u15260e preliminary user?s manual u17702ej1v0ud 8 contents chapter 1 introduction...................................................................................................... ............17 1.1 v850es/kx2 product lineup ................................................................................................. ........ 17 1.2 features .................................................................................................................. ........................ 18 1.3 applications.............................................................................................................. ...................... 19 1.4 ordering information ...................................................................................................... ............... 19 1.5 pin configuration (top view) .............................................................................................. .......... 20 1.6 function block configuration........................................... ................................................... ......... 22 1.7 overview of functions..................................................................................................... .............. 26 chapter 2 pin functions .................................................................................................... ............27 2.1 list of pin functions..................................................................................................... ................. 27 2.2 pin status................................................................................................................ ........................ 36 2.3 pin i/o circuits and recommend ed connection of unused pins ...... ....................................... 37 2.4 pin i/o circuits.......................................................................................................... ...................... 40 chapter 3 cpu functions.................................................................................................... ...........42 3.1 features .................................................................................................................. ........................ 42 3.2 cpu register set.......................................................................................................... .................. 43 3.2.1 program register set .................................................................................................... ...................... 44 3.2.2 system register set..................................................................................................... ....................... 45 3.3 operating modes ........................................................................................................... ................. 51 3.4 address space ............................................................................................................. .................. 52 3.4.1 cpu ad dress s pace ....................................................................................................... ................... 52 3.4.2 wraparound of cpu address space......................................................................................... ......... 53 3.4.3 memo ry map .............................................................................................................. ....................... 54 3.4.4 areas ................................................................................................................... .............................. 56 3.4.5 recommended us e of addre ss space ........................................................................................ ....... 60 3.4.6 peripheral i/o registers ................................................................................................ ..................... 63 3.4.7 specia l regist ers....................................................................................................... ......................... 76 3.4.8 c autio ns ................................................................................................................ ............................ 79 chapter 4 port functions ................................................................................................... .........83 4.1 features .................................................................................................................. ........................ 83 4.2 basic port configuration .................................................................................................. ............. 83 4.3 port configuration.......................................................... .............................................. .................. 84 4.3.1 po rt 0.................................................................................................................. ............................... 90 4.3.2 po rt 1.................................................................................................................. ............................... 93 4.3.3 po rt 3.................................................................................................................. ............................... 95 4.3.4 po rt 4.................................................................................................................. ............................. 101 4.3.5 po rt 5.................................................................................................................. ............................. 104 4.3.6 po rt 6.................................................................................................................. ............................. 108 4.3.7 po rt 7.................................................................................................................. ............................. 113 4.3.8 po rt 8.................................................................................................................. ............................. 114 preliminary user?s manual u17702ej1v0ud 9 4.3.9 port 9 ................................................................................................................... ..........................117 4.3.10 po rt cd ................................................................................................................ ..........................125 4.3.11 po rt cm................................................................................................................ ..........................127 4.3.12 po rt cs ................................................................................................................ ..........................129 4.3.13 po rt ct................................................................................................................ ...........................131 4.3.14 po rt dh ................................................................................................................ ..........................133 4.3.15 po rt dl................................................................................................................ ...........................135 4.4 block diagrams ............................................................................................................ ................ 138 4.5 port register setting when al ternate function is used .................. ....................................... 173 4.6 cautions.................................................................................................................. ...................... 182 4.6.1 cautions on bit m anipulation instru ction for port n register (pn)....................................................... 182 4.6.2 hysteresis characteri stics .............................................................................................. ..................183 4.6.3 cautions on p05 pin..................................................................................................... ....................183 chapter 5 bus control function...........................................................................................1 84 5.1 features .................................................................................................................. ...................... 184 5.2 bus control pins .......................................................................................................... ................ 185 5.2.1 pin status when internal rom, internal ram, or on-chip peri pheral i/o is accesse d .......................186 5.2.2 pin status in each operat ion mo de ....................................................................................... ............186 5.3 memory block function ..................................................................................................... ......... 187 5.3.1 chip select control function ............................................................................................ ..................188 5.4 external bus interface mode control function ......... ............................................................... 188 5.5 bus access................................................................................................................ ................... 189 5.5.1 number of clocks for access ............................................................................................. ...............189 5.5.2 bus size setting f unction ............................................................................................... ...................189 5.5.3 access by bus size...................................................................................................... .....................190 5.6 wait function ............................................................................................................. .................. 197 5.6.1 programmabl e wait fu nction.............................................................................................. ...............197 5.6.2 external wait function .................................................................................................. .....................198 5.6.3 relationship be tween programmable wait and external wait ...........................................................199 5.6.4 programmable addr ess wait functi on ...................................................................................... .........200 5.7 idle state insertion function................................... .......................................................... .......... 201 5.8 bus hold function ......................................................................................................... .............. 202 5.8.1 functi onal out line ...................................................................................................... .......................202 5.8.2 bus hol d proced ure ...................................................................................................... ....................203 5.8.3 operation in power sa ve mode ............................................................................................ ............203 5.9 bus priority.............................................................................................................. ..................... 204 5.10 bus timing............................................................................................................... ................... 205 5.11 cautions................................................................................................................. ..................... 211 chapter 6 clock generation function ...............................................................................212 6.1 overview .................................................................................................................. ..................... 212 6.2 configuration............................................................................................................. ................... 213 6.3 registers................................................................................................................. ...................... 215 6.4 operation ................................................................................................................. ..................... 219 6.4.1 operation of each clock ................................................................................................. ..................219 6.4.2 clock out put func tion................................................................................................... .....................219 preliminary user?s manual u17702ej1v0ud 10 6.4.3 external cl ock input function........................................................................................... ................. 219 6.5 pll function .............................................................................................................. .................. 220 6.5.1 ov erview ................................................................................................................ ......................... 220 6.5.2 r egist er ................................................................................................................ ........................... 220 6.5.3 usage ................................................................................................................... ........................... 221 chapter 7 16-bit timer/event counter p (tmp)................................................................. 222 7.1 overview .................................................................................................................. ..................... 222 7.2 functions ................................................................................................................. ..................... 222 7.3 configuration............................................................................................................. ................... 223 7.4 registers ................................................................................................................. ...................... 225 7.5 operation ................................................................................................................. ..................... 236 7.5.1 interval timer mode (tp0 md2 to tp0md0 bits = 000) ..................................................................... 23 7 7.5.2 external event count mode (tp0md2 to tp0md0 bits = 001) ......................................................... 247 7.5.3 external trigger pulse output mode (tp0md2 to tp0m d0 bits = 010)............................................. 255 7.5.4 one-shot pulse output mode (tp0md2 to tp0md0 bits = 011) ...................................................... 267 7.5.5 pwm output mode (tp0md 2 to tp0md0 bits = 100) ...................................................................... 274 7.5.6 free-running timer mode (t p0md2 to tp0md0 bits = 101) ............................................................ 283 7.5.7 pulse width meas urement mode (tp0md2 to tp0md0 bits = 110) ................................................ 300 7.5.8 timer ou tput oper ations ................................................................................................. ................. 306 7.6 eliminating noise on capture trigger input pin (t ip0a) .......................................................... 307 7.7 cautions .................................................................................................................. ...................... 309 chapter 8 16-bit timer/event counter 0 ............................................................................. 310 8.1 functions ................................................................................................................. ..................... 310 8.2 configuration............................................................................................................. ................... 311 8.3 registers ................................................................................................................. ...................... 316 8.4 operation ................................................................................................................. ..................... 325 8.4.1 interval timer oper ation................................................................................................ .................... 325 8.4.2 square wave output op eration............................................................................................ ............. 328 8.4.3 external event counter operatio n........................................................................................ ............. 331 8.4.4 operation in clear & start mode entered by ti 0n0 pin valid ed ge input ........................................... 334 8.4.5 free-runni ng timer oper ation ............................................................................................ ............... 350 8.4.6 ppg out put operat ion .................................................................................................... .................. 359 8.4.7 one-shot pul se output operatio n ......................................................................................... ............ 362 8.4.8 pulse width m easurement operatio n ....................................................................................... ........ 367 8.5 special use of tm0n ....................................................................................................... ............. 375 8.5.1 rewriting cr0n1 regi ster during tm 0n operat ion .......................................................................... . 375 8.5.2 setting lvs 0n and lvr 0n bits ............................................................................................ ............ 375 8.6 cautions .................................................................................................................. ...................... 377 chapter 9 8-bit timer/event counter 5 ............................................................................... 384 9.1 functions ................................................................................................................. ..................... 384 9.2 configuration............................................................................................................. ................... 385 9.3 registers ................................................................................................................. ...................... 388 9.4 operation ................................................................................................................. ..................... 391 9.4.1 operation as interval timer ............................................................................................. ................. 391 preliminary user?s manual u17702ej1v0ud 11 9.4.2 operation as ex ternal event count er ..................................................................................... ...........393 9.4.3 square-wave output op eration ............................................................................................ .............394 9.4.4 8-bit pwm output oper ation .............................................................................................. ...............396 9.4.5 operation as inte rval timer (16 bi ts) ................................................................................... ..............399 9.4.6 operation as external event counter (16 bits) ........................................................................... .......401 9.4.7 square-wave output op eration (16-bi t resolu tion) ........................................................................ ....402 9.4.8 c autio ns................................................................................................................ ...........................403 chapter 10 8-bit timer h .................................................................................................. ............404 10.1 functions ................................................................................................................ .................... 404 10.2 configuration............................................................................................................ .................. 404 10.3 registers................................................................................................................ ..................... 407 10.4 operation ................................................................................................................ .................... 411 10.4.1 operation as interv al timer/squar e wave output ......................................................................... ....411 10.4.2 pwm output mode ope ration .............................................................................................. ...........414 10.4.3 carrier generat or mode operatio n ....................................................................................... ...........420 chapter 11 interval timer, watch timer ............................................................................427 11.1 interval timer brg ....................................................................................................... ............. 427 11.1.1 f unction s .............................................................................................................. .........................427 11.1.2 conf iguration.......................................................................................................... ........................427 11.1.3 re gisters.............................................................................................................. ..........................429 11.1.4 o peratio n .............................................................................................................. .........................431 11.2 watch timer.............................................................................................................. .................. 432 11.2.1 f unction s .............................................................................................................. .........................432 11.2.2 conf iguration.......................................................................................................... ........................432 11.2.3 re gisters.............................................................................................................. ..........................433 11.2.4 o peratio n .............................................................................................................. .........................435 11.3 cautions................................................................................................................. ..................... 436 chapter 12 watchdog timer functions ...............................................................................438 12.1 watchdog timer 1......................................................................................................... ............. 438 12.1.1 f unction s .............................................................................................................. .........................438 12.1.2 conf iguration.......................................................................................................... ........................440 12.1.3 re gisters.............................................................................................................. ..........................440 12.1.4 o peratio n .............................................................................................................. .........................442 12.2 watchdog timer 2......................................................................................................... ............. 444 12.2.1 f unction s .............................................................................................................. .........................444 12.2.2 conf iguration.......................................................................................................... ........................445 12.2.3 re gisters.............................................................................................................. ..........................445 12.2.4 o peratio n .............................................................................................................. .........................447 chapter 13 real-time output function (rto)....................................................................448 13.1 function ................................................................................................................. ..................... 448 13.2 configuration............................................................................................................ .................. 449 13.3 registers................................................................................................................ ..................... 450 preliminary user?s manual u17702ej1v0ud 12 13.4 operation ................................................................................................................ .................... 452 13.5 usage.................................................................................................................... ....................... 453 13.6 cautions ................................................................................................................. ..................... 453 13.7 security function ........................................................................................................ ............... 454 chapter 14 a/d converter ................................................................................................... ...... 456 14.1 overview ................................................................................................................. .................... 456 14.2 functions ................................................................................................................ .................... 456 14.3 configuration............................................................................................................ .................. 457 14.4 registers ................................................................................................................ ..................... 459 14.5 operation ................................................................................................................ .................... 467 14.5.1 basic operation........................................................................................................ ...................... 467 14.5.2 tri gger m odes .......................................................................................................... ..................... 468 14.5.3 operat ion mo des........................................................................................................ ................... 469 14.5.4 power fail detection fu nction.......................................................................................... ................ 472 14.5.5 setti ng met hod ......................................................................................................... ..................... 473 14.6 cautions ................................................................................................................. ..................... 474 14.7 how to read a/d converter characteristics table ................................................................. 480 chapter 15 d/a converter ................................................................................................... ...... 484 15.1 functions ................................................................................................................ .................... 484 15.2 configuration............................................................................................................ .................. 485 15.3 registers ................................................................................................................ ..................... 486 15.4 operation ................................................................................................................ .................... 487 15.4.1 operation in norma l mode ............................................................................................... .............. 487 15.4.2 operation in real-time out put mode ..................................................................................... .......... 487 15.4.3 c autions ............................................................................................................... ......................... 488 chapter 16 asynchronous serial interface (uart)..................................................... 489 16.1 uart2 pin................................................................................................................ ................... 489 16.1.1 selecting ua rt2 or cs i00 mode.......................................................................................... ........ 490 16.1.2 selecting uart2 or i 2 c1 mo de ..................................................................................................... 491 16.2 features ................................................................................................................. ..................... 492 16.3 configuration............................................................................................................ .................. 493 16.4 registers ................................................................................................................ ..................... 495 16.5 interrupt requests ....................................................................................................... .............. 501 16.6 operation ................................................................................................................ .................... 502 16.6.1 data format............................................................................................................ ........................ 502 16.6.2 transmi t operat ion ..................................................................................................... ................... 503 16.6.3 continuous tr ansmission op eration ...................................................................................... ......... 505 16.6.4 receiv e operat ion ...................................................................................................... ................... 509 16.6.5 recept ion e rror........................................................................................................ ...................... 510 16.6.6 parity types and corresponding operat ion ............................................................................... ...... 512 16.6.7 receive dat a noise filter .............................................................................................. .................. 513 16.7 dedicated baud rate generator n (brgn) .............................................................................. 514 16.7.1 baud rate generator n (brgn) c onfigurat ion ............................................................................. .... 514 16.7.2 serial cl ock gener ation ................................................................................................ .................. 515 preliminary user?s manual u17702ej1v0ud 13 16.7.3 baud rate setting ex ample .............................................................................................. ...............518 16.7.4 allowable baud rate range dur ing rec eption ............................................................................. ......519 16.7.5 transfer rate durin g continuous transmi ssion ........................................................................... .....521 16.8 cautions................................................................................................................. ..................... 521 chapter 17 clocked serial interface 0 (csi0).................................................................522 17.1 features ................................................................................................................. ..................... 522 17.2 configuration............................................................................................................ .................. 523 17.3 registers................................................................................................................ ..................... 526 17.4 operation ................................................................................................................ .................... 535 17.4.1 transmission/receptio n completion interrupt requ est signal (i ntcsi 0n) ....................................... 535 17.4.2 single transfer mode ................................................................................................... ...................537 17.4.3 continuous transfe r mode ............................................................................................... ...............540 17.5 output pins.............................................................................................................. ................... 548 chapter 18 clocked serial interface a (csia) with automatic transmit/receive function.................................................................................549 18.1 functions ................................................................................................................ .................... 549 18.2 configuration............................................................................................................ .................. 550 18.3 registers................................................................................................................ ..................... 552 18.4 operation ................................................................................................................ .................... 561 18.4.1 3-wire se rial i/o mode ................................................................................................. ...................561 18.4.2 3-wire serial i/o mode with automat ic transmit/recei ve func tion .....................................................565 chapter 19 i 2 c bus......................................................................................................................... ..581 19.1 selecting uart2 or i 2 c1 mode ................................................................................................. 581 19.2 features ................................................................................................................. ..................... 582 19.3 configuration............................................................................................................ .................. 585 19.4 registers................................................................................................................ ..................... 587 19.5 functions ................................................................................................................ .................... 601 19.5.1 pin c onfigurat ion ...................................................................................................... ......................601 19.6 i 2 c bus definitions and control methods................................................................................ 602 19.6.1 star t condi tion ........................................................................................................ ........................602 19.6.2 a ddresses .............................................................................................................. ........................603 19.6.3 transfer direct ion specif ication....................................................................................... ................604 19.6.4 ack.................................................................................................................... ............................605 19.6.5 stop condition ......................................................................................................... .......................606 19.6.6 wait state ............................................................................................................. ..........................607 19.6.7 wait state c ancellation method ......................................................................................... .............609 19.7 i 2 c interrupt request signals (intiicn) .......................... ......................................................... 610 19.7.1 master device oper ation................................................................................................ .................611 19.7.2 slave device operation (when receiving slave address data ( address matc h)) .............................614 19.7.3 slave device operation (when receiving ex tension code)...............................................................61 8 19.7.4 operation wit hout comm unicati on ........................................................................................ ..........622 19.7.5 arbitration lo ss operation (operation as sl ave after arbitr ation lo ss)...............................................62 3 19.7.6 operation when arbitration loss occurs (no commu nication after arbi tration loss) .........................625 19.8 interrupt request signal (int iicn) generation timing and wait c ontrol ............................ 632 preliminary user?s manual u17702ej1v0ud 14 19.9 address match detect ion method ........................................................................................... . 633 19.10 error detection ......................................................................................................... ................ 633 19.11 extension code .......................................................................................................... .............. 634 19.12 arbitration ............................................................................................................. .................... 635 19.13 wakeup function ......................................................................................................... ............ 636 19.14 communication reservation ............................................................................................... ... 637 19.14.1 when communication reservation func tion is enabled (iicfn .iicrsvn bi t = 0)........................... 637 19.14.2 when communication reservation func tion is disabled (iicfn .iicrsvn bi t = 1) .......................... 640 19.15 cautions ................................................................................................................ .................... 641 19.16 communication operations ................................................................................................ .... 642 19.16.1 master operation in single mast er sy stem .............................................................................. ..... 643 19.16.2 master operation in multimas ter sy stem ................................................................................ ...... 644 19.16.3 slav e operat ion ....................................................................................................... .................... 647 19.17 timing of data communication ............................................................................................ .. 650 chapter 20 dma function (dma controller).................................................................... 657 20.1 features ................................................................................................................. ..................... 657 20.2 configuration............................................................................................................ .................. 658 20.3 registers ................................................................................................................ ..................... 659 20.4 transfer targets ......................................................................................................... ................ 666 20.5 transfer modes........................................................................................................... ................ 666 20.6 transfer types........................................................................................................... ................. 667 20.7 dma channel priorities ................................................................................................... .......... 667 20.8 time related to dma transfer............................................................................................. ..... 668 20.9 dma transfer start fact ors ............................................................................................... ....... 669 20.10 dma abort factors....................................................................................................... ............ 670 20.11 end of dma transfer..................................................................................................... ........... 670 20.12 operation timing........................................................................................................ .............. 670 20.13 cautions ................................................................................................................ .................... 675 chapter 21 interrupt/exception processing function............................................... 680 21.1 overview ................................................................................................................. .................... 680 21.1.1 f eatures ............................................................................................................... ......................... 680 21.2 non-maskable interrupts .................................................................................................. ......... 684 21.2.1 o peratio n.............................................................................................................. ......................... 687 21.2.2 re store................................................................................................................ .......................... 688 21.2.3 np flag................................................................................................................ ........................... 689 21.3 maskable interrupts ...................................................................................................... ............. 690 21.3.1 o peratio n.............................................................................................................. ......................... 690 21.3.2 re store................................................................................................................ .......................... 692 21.3.3 priorities of maskable in terrupts ...................................................................................... .............. 693 21.3.4 interrupt contro l register (xxlcn) ..................................................................................... ............... 697 21.3.5 interrupt mask register s 0 to 3 (imr 0 to im r3) ......................................................................... .... 700 21.3.6 in-service prio rity regist er (ispr) .................................................................................... .............. 702 21.3.7 id flag ................................................................................................................ ............................ 703 21.3.8 watchdog timer mode register 1 (wdtm1) ................................................................................. .. 704 21.4 external interrupt request i nput pins (nmi, intp0 to intp7) ............................................... 705 preliminary user?s manual u17702ej1v0ud 15 21.4.1 noise eliminat ion...................................................................................................... ......................705 21.4.2 edge detect ion ......................................................................................................... ......................707 21.5 software exceptions...................................................................................................... ............ 711 21.5.1 o peratio n .............................................................................................................. .........................711 21.5.2 re store ................................................................................................................ ..........................712 21.5.3 ep fl ag ................................................................................................................ ...........................713 21.6 exception trap ........................................................................................................... ................ 714 21.6.1 illega l op code ........................................................................................................ ........................714 21.6.2 de bug tr ap ............................................................................................................. ........................716 21.7 multiple interrupt servicing control ..................................................................................... ... 718 21.8 interrupt response time............................................ ...................................................... ......... 720 21.9 periods in which interrupts are not acknowledge d by cpu ............................................... 721 21.10 cautions................................................................................................................ .................... 721 chapter 22 key interrupt function ......................................................................................722 22.1 function ................................................................................................................. ..................... 722 22.2 register................................................................................................................. ...................... 723 chapter 23 standby function ................................................................................................ ...724 23.1 overview ................................................................................................................. .................... 724 23.2 registers................................................................................................................ ..................... 727 23.3 halt mode ................................................................................................................ ................. 730 23.3.1 setting and o peration status ........................................................................................... ...............730 23.3.2 releasi ng halt mode .................................................................................................... ...............730 23.4 idle mode................................................................................................................ ................... 732 23.4.1 setting and o peration status ........................................................................................... ...............732 23.4.2 releasi ng idle mode .................................................................................................... ................733 23.5 stop mode ................................................................................................................ ................. 735 23.5.1 setting and o peration status ........................................................................................... ...............735 23.5.2 releasi ng stop mode .................................................................................................... ..............736 23.5.3 securing oscillation stabilizati on time when stop mode is re leased ............................................738 23.6 subclock operation mode.................................................................................................. ....... 739 23.6.1 setting and o peration status ........................................................................................... ...............739 23.6.2 releasing subc lock operat ion m ode ...................................................................................... ........739 23.7 sub-idle mode............................................................................................................ ............... 741 23.7.1 setting and o peration status ........................................................................................... ...............741 23.7.2 releasing sub-idle mode ................................................................................................ .............742 chapter 24 reset function .................................................................................................. ......744 24.1 overview ................................................................................................................. .................... 744 24.2 configuration............................................................................................................ .................. 744 24.3 operation ................................................................................................................ .................... 745 chapter 25 regulator ........................................................................................................ ..........749 25.1 overview ................................................................................................................. .................... 749 25.2 operation ................................................................................................................ .................... 749 preliminary user?s manual u17702ej1v0ud 16 chapter 26 flash memory .................................................................................................... ...... 751 26.1 features ................................................................................................................. ..................... 751 26.2 memory configuration ..................................................................................................... .......... 752 26.3 functional outline....................................................................................................... ............... 753 26.4 rewriting by dedicated flash programmer ............................................................................ 755 26.4.1 programmi ng environ ment ................................................................................................ ............ 755 26.4.2 communi cation mode ..................................................................................................... .............. 756 26.4.3 flash me mory control ................................................................................................... ................. 761 26.4.4 selection of communica tion mo de........................................................................................ ......... 762 26.4.5 communi cation co mmands ................................................................................................. .......... 763 26.4.6 pin connection......................................................................................................... ...................... 764 26.5 rewriting by self progra mming............................................................................................ .... 769 26.5.1 ov erview ............................................................................................................... ........................ 769 26.5.2 f eatures ............................................................................................................... ......................... 770 26.5.3 standard self programmi ng fl ow......................................................................................... ........... 771 26.5.4 flash functi ons ........................................................................................................ ...................... 772 26.5.5 pin proce ssing ......................................................................................................... ...................... 772 26.5.6 internal resources used ................................................................................................ ................. 773 chapter 27 on-chip debug function ..................................................................................... 774 27.1 features ................................................................................................................. ..................... 774 27.2 connection circuit example ............................................................................................... ...... 775 27.3 interface signals........................................................................................................ ................. 775 27.4 register ................................................................................................................. ...................... 777 27.5 operation ................................................................................................................ .................... 779 27.6 rom security function.................................................................................................... .......... 780 27.6.1 secu rity id............................................................................................................ ......................... 780 27.6.2 setti ng ................................................................................................................ ........................... 781 27.7 cautions ................................................................................................................. ..................... 782 chapter 28 electrical specifications (target).............................................................. 783 chapter 29 package drawing................................................................................................. .. 830 appendix a instruction set list ........................................................................................... .. 831 a.1 conventions ............................................................................................................... .................. 831 a.2 instruction set (in alphabetical order)..................... .............................................................. ... 834 appendix b register index .................................................................................................. ....... 841 preliminary user?s manual u17702ej1v0ud 17 chapter 1 introduction 1.1 v850es/kx2 product lineup product name v850es/ke2 v850 es/kf2 v850es/kg2 v850es/kj2 number of pins 64 pins 80 pins 100 pins 144 pins flash memory 128 128 256 128 256 128 256 internal memory (kb) ram 4 6 12 6 16 6 16 supply voltage 2.7 to 5.5 v minimum instruction execution time 50 ns @20 mhz x1 input 2 to 10 mhz clock subclock 32.768 khz cmos input 8 8 8 16 cmos i/o 41 (4) note 57 (6) note 72 (8) note 106 (12) note port n-ch open-drain i/o 2 2 4 6 16-bit (tmp) 1 ch 1 ch 1 ch 1 ch 16-bit (tm0) 1 ch 2 ch 4 ch 6 ch 8-bit (tm5) 2 ch 2 ch 2 ch 2 ch 8-bit (tmh) 2 ch 2 ch 2 ch 2 ch interval timer 1 ch 1 ch 1 ch 1 ch watch 1 ch 1 ch 1 ch 1 ch wdt1 1 ch 1 ch 1 ch 1 ch timer wdt2 1 ch 1 ch 1 ch 1 ch rto 6 bits 1 ch 6 bits 1 ch 6 bits 1 ch 6 bits 2 ch csi 2 ch 2 ch 2 ch 3 ch automatic transmit/ receive 3-wire csi ? 1 ch 2 ch 2 ch uart 2 ch 2 ch 3 ch 3 ch serial interface i 2 c 1 ch 1 ch 1 ch 2 ch address space ? 128 kb 3 mb 15 mb address bus ? 16 bits 22 bits 24 bits external bus mode ? multiplex only multiplex/separate dma controller ? ? 4 ch 4 ch 10-bit a/d converter 8 ch 8 ch 8 ch 16 ch 8-bit d/a converter ? ? 2 ch 2 ch external 9 9 9 9 interrupt internal 26 29 41 47 key return input 8 ch 8 ch 8 ch 8 ch reset pin provided wdt1 provided reset wdt2 provided regulator none provided standby function halt/idle/stop/sub-idle mode operating ambient temperature ta = ? 40 to +85 c note figures in parentheses indicate the number of pins fo r which the n-ch open-drain output can be selected. chapter 1 introduction preliminary user?s manual u17702ej1v0ud 18 1.2 features { minimum instruction execution time: 50 ns (operation at main clock (f xx ) = 20 mhz) { general-purpose registers: 32 bits 32 registers { cpu features: signed multiplication (16 16 32): 1 to 2 clocks (instructions without creating register haza rds can be continuously executed in parallel) saturated operations (overflow and underflow detection functions are included) 32-bit shift instruction: 1 clock bit manipulation instructions load/store instructions with long/short format { memory space: 64 mb of linear address space memory block division function: 2 mb, 2 mb, 4 mb, 8 mb (total of 4 blocks) ? internal memory pd70f3733 (flash memory: 128 kb/ram: 6 kb) pd70f3734 (flash memory: 256 kb/ram: 16 kb) ? external bus interface separate bus/multiplex bus output selectable 8-/16-bit data bus sizing function wait function ? programmable wait function ? external wait function idle state function bus hold function { interrupts and exceptions non-maskable interrupts: 3 sources maskable interrupts: 53 sources software exceptions: 32 sources exception trap: 1 source { i/o lines: total: 128 { key interrupt function { timer function 16-bit timer/event counter p: 1 channel 16-bit timer/event counter 0: 6 channels 8-bit timer/event counter 5: 2 channels 8-bit timer h: 2 channels 8-bit interval timer brg: 1 channel watch timer/interval timer: 1 channel watchdog timers watchdog timer 1 (also usable as oscillation stabilization timer): 1 channel watchdog timer 2: 1 channel { serial interface asynchronous serial interface (uart): 3 channels 3-wire serial i/o (csi0): 3 channels 3-wire serial i/o (with automatic transmi t/receive function) (csia): 2 channels i 2 c bus interface (i 2 c): 2 channels { a/d converter: 10-bit resolution 16 channels { d/a converter: 8-bit resolution 2 channels { dma controller: 4 channels chapter 1 introduction preliminary user?s manual u17702ej1v0ud 19 { real-time output port: 6 bits 2 channels { standby functions: halt/idle/stop modes, subclock/sub-idle modes { on-chip debug function: jtag interface (only in the pd70f3734) { clock generator main clock oscillation (f x )/subclock oscillation (f xt ) cpu clock (f cpu ) 7 steps (f xx , f xx /2, f xx /4, f xx /8, f xx /16, f xx /32, f xt ) clock-through mode/pll mode selectable { reset ? reset by reset pin ? reset by overflow of watchdog timer 1 (wdtres1) ? reset by overflow of watchdog timer 2 (wdtres2) { package: 144-pin plastic lqfp (fine pitch) (20 20) 1.3 applications { automotive ? system control of body electrical system (p ower windows, keyless entry reception, etc.) ? submicrocontroller of control system { home audio, car audio { av equipment { pc peripheral devices (keyboards, etc.) { household appliances ? outdoor units of air conditioners ? microwave ovens, rice cookers { industrial devices ? pumps ? vending machines ? fa 1.4 ordering information part number package pd70f3733gj-uen-a pd70f3734gj-uen-a 144-pin plastic lqfp (fine pitch) (20 20) 144-pin plastic lqfp (fine pitch) (20 20) remark products with -a at the end of the part number are lead-free products. chapter 1 introduction preliminary user?s manual u17702ej1v0ud 20 1.5 pin configuration (top view) 144-pin plastic lqfp (fine pitch) (20 20) pd70f3733gj-uen-a pd70f3734gj-uen-a pdl3/ad3 pdl2/ad2 pdl1/ad1 pdl0/ad0 bv dd bv ss pct7 pct6/astb pct5 pct4/rd pct3 pct2 pct1/wr1 pct0/wr0 pcs7 pcs6 pcs5 pcs4 pcm5 pcm4 pcm3/hldrq pcm2/hldak pcm1/clkout pcm0/wait pcs3/cs3 pcs2/cs2 pcs1/cs1 pcs0/cs0 pcd3 pcd2 pcd1 pcd0 p915/a15/intp6 p914/a14/intp5 p913/a13/intp4 p912/a12/scka1 av ref0 av ss p10/ano0 p11/ano1 av ref1 p00/toh0 p01/toh1 flmd0 note 1 v dd regc note 2 v ss x1 x2 reset xt1 xt2 p02/nmi p03/intp0 p04/intp1 p05 note 3 /intp2/drst note 4 p06/intp3 p40/si00/rxd2 p41/so00/txd2 p42/sck00 p30/txd0/to2 p31/rxd0/intp7/to03 p32/asck0/adtrg/to01 p33/ti000/to00/tip00/top00 p34/ti001/to00/tip01/top01 p35/ti010/to01 p36 p37 ev ss ev dd p38/sda0 p39/scl0 p50/ti011/rtp00/kr0 p51/ti50/rtp01/kr1 p52/to50/rtp02/kr2/ddi note 4 p53/sia0/rtp03/kr3/ddo note 4 p54/soa0/rtp04/kr4/dck note 4 p55/scka0/rtp05/kr5/dms note 4 p60/rtp10 p61/rtp11 p62/rtp12 p63/rtp13 p64/rtp14 p65/rtp15 p66/si02 p67/so02 p68/sck02 p69/ti040 p610/ti041 p611/to04 p612/ti050 p613/ti051/to05 p614 p615 p80/rxd2/sda1 p81/txd2/scl1 p90/a0/txd1/kr6 p91/a1/rxd1/kr7 p92/a2/ti020/to02 p93/a3/ti021 p94/a4/ti030/to03 p95/a5/ti031 p96/a6/ti51/to51 p97/a7/si01 p98/a8/so01 p99/a9/sck01 p910/a10/sia1 p911/a11/soa1 p70/ani0 p71/ani1 p72/ani2 p73/ani3 p74/ani4 p75/ani5 p76/ani6 p77/ani7 p78/ani8 p79/ani9 p710/ani10 p711/ani11 p712/ani12 p713/ani13 p714/ani14 p715/ani15 pdh7/a23 pdh6/a22 pdh5/a21 pdh4/a20 pdh3/a19 pdh2/a18 pdh1/a17 pdh0/a16 pdl15/ad15 pdl14/ad14 pdl13/ad13 pdl12/ad12 pdl11/ad11 pdl10/ad10 pdl9/ad9 pdl8/ad8 pdl7/ad7 pdl6/ad6 pdl5/ad5/flmd1 pdl4/ad4 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 notes 1. flmd0 pin: connect to v ss in normal operation mode. 2. when using a regulator, connect the regc pin to v ss via a 10 f capacitor. when not using a regulator, connect the regc pin directly to v dd . 3. care must be exercised in processing the p05 pin when reset is released. for details, refer to 4.6.3 cautions on p05 pin . 4. the drst, ddi, ddo, dck, and dms pins can be used only in the pd70f3734. caution make ev dd the same potential as v dd . bv dd can be used when v dd = ev dd bv dd . chapter 1 introduction preliminary user?s manual u17702ej1v0ud 21 pin identification a0 to a23: ad0 to ad15: ani0 to ani15: ano0, ano1: asck0: astb: av ref0 , av ref1 : av ss : bv dd : bv ss : clkout: cs0 to cs3: dck: ddi: ddo: dms drst ev dd : ev ss : flmd0, flmd1 hldak: hldrq: intp0 to intp7: kr0 to kr7: nmi: p00 to p06: p10, p11: p30 to p39: p40 to p42: p50 to p55: p60 to p615: p70 to p715: p80, p81: p90 to p915: pcd0 to pcd3: pcm0 to pcm5: pcs0 to pcs7: address bus address/data bus analog input analog output asynchronous serial clock address strobe analog reference voltage ground for analog power supply for bus interface ground for bus interface clock output chip select debug clock debug data input debug data output debug mode select debug reset power supply for port ground for port flash programming mode hold acknowledge hold request external interrupt input key return non-maskable interrupt request port 0 port 1 port 3 port 4 port 5 port 6 port 7 port 8 port 9 port cd port cm port cs pct0 to pct7: pdh0 to pdh7: pdl0 to pdl15: rd: regc: reset: rtp00 to rtp05, rtp10 to rtp15: rxd0 to rxd2: sck00 to sck02, scka0, scka1: scl0, scl1: sda0, sda1: si00 to si02, sia0, sia1: so00 to so02, soa0, soa1: ti000, ti001, ti010, ti011, ti020, ti021, ti030, ti031, ti040, ti041, ti050, ti051, ti50, ti51, tip00, tip01: to00 to to05, to50, to51, toh0, toh1, top00, top01: txd0 to txd2: v dd : v ss : wait: wr0: wr1: x1, x2: xt1, xt2: port ct port dh port dl read strobe regulator control reset real-time output port receive data serial clock serial clock serial data serial input serial output timer input timer output transmit data power supply ground wait lower byte write strobe upper byte write strobe crystal for main clock crystal for subclock chapter 1 introduction preliminary user?s manual u17702ej1v0ud 22 1.6 function block configuration (1) internal block diagram nmi to00 to to05 ti000, ti001, ti010, ti011, ti020, ti021, ti030, ti031, ti040, ti041, ti050, ti051 so00 to so02 si00 to si02 sck00 to sck02 intp0 to intp7 intc 16-bit timer/event counter 0: 6 ch top00, top01 tip00, tip01 16-bit timer/ event counter p: 1 ch to50, to51 ti50, ti51 8-bit timer/event counter 5: 2 ch toh0, toh1 txd0 to txd2 rxd0 to rxd2 asck0 rtp00 to rtp05, rtp10 to rtp15 kr0 to kr7 uart : 3 ch csia : 2 ch rto: 2 ch sda0, sda1 scl0, scl1 i 2 c : 2 ch watchdog timer: 2 ch key interrupt function regulator watch timer note 1 note 2 ram rom pc general-purpose registers 32 bits 32 multiplier 16 16 32 alu system registers 32-bit barrel shifter cpu hldrq hldak astb rd wait wr0, wr1 cs0 to cs3 a0 to a23 ad0 to ad15 port a/d converter d/a converter pdl0 to pdl15 pdh0 to pdh7 pct0 to pct7 pcs0 to pcs7 pcm0 to pcm5 pcd0 to pcd3 p90 to p915 p80, p81 p70 to p715 p60 to p615 p50 to p55 p40 to p42 p30 to p39 p10, p11 p00 to p06 ano0, ano1 av ref1 regc av ref0 av ss ani0 to ani15 v dd flmd0 flmd1 bv dd bv ss ev dd ev ss v ss instruction queue bcu soa0, soa1 sia0, sia1 scka0, scka1 csi0: 3 ch 8-bit timer h: 2 ch dma cg pll clkout x1 x2 xt1 xt2 reset drst note 3 dms note 3 ddi note 3 dck note 3 ddo note 3 on-chip debug function note 3 notes 1. pd70f3733: 128 kb (flash memory) pd70f3734: 256 kb (flash memory) 2. pd70f3733: 6 kb pd70f3734: 16 kb 3. only in the pd70f3734 chapter 1 introduction preliminary user?s manual u17702ej1v0ud 23 (2) internal units (a) cpu the cpu uses five-stage pipeline control to enable single-clock execution of address calculations, arithmetic logic operations, data transfers, and almost all other types of instruction processing. other dedicated on-chip hardware, such as a multiplier (16 bits 16 bits 32 bits) and a barrel shifter (32 bits) help accelerate complex processing. (b) bus control unit (bcu) the bcu starts a required external bus cycle bas ed on the physical address obtained by the cpu. when an instruction is fetched from external memo ry space and the cpu does not send a bus cycle start request, the bcu generates a prefet ch address and prefetches the inst ruction code. the prefetched instruction code is stored in an internal instruction queue. (c) rom this consists of a 256 kb or 128 kb flash memory mapped to the address spaces from 0000000h to 003ffffh or 0000000h to 0 01ffffh, respectively. rom can be accessed by the cpu in one cl ock cycle during instruction fetch. (d) ram this consists of a 16 kb or 6 kb ram mapped to th e address spaces from 3ffb000h to 3ffefffh or 3ffb000h to 3ffc7ffh. ram can be accessed by the cpu in on e clock cycle during data access. (e) interrupt controller (intc) this controller handles hardware interrupt requests (nmi, intp0 to intp7) from on-chip peripheral hardware and external hardware. eight levels of inte rrupt priorities can be spec ified for these interrupt requests, and multiplexed servicing control can be performed. (f) clock generator (cg) a main clock oscillator and subclock oscillator ar e provided and generate the main clock oscillation frequency (f x ) and subclock frequency (f xt ), respectively. there are two modes: in the clock-through mode, f x is used as the main clock frequency (f xx ) as is. in the pll mode, f x is used multiplied by 4. the cpu clock frequency (f cpu ) can be selected from among f xx , f xx /2, f xx /4, f xx /8, f xx /16, f xx /32, and f xt . (g) timer/counter six 16-bit timer/event counter 0 channels, one 16-bit timer/event counter p channel, and two 8-bit timer/event counter 5 channels ar e incorporated, enabling measurement of pulse intervals and frequency as well as programmable pulse output. two 8-bit timer/event counter 5 channels can be connec ted in cascade to configure a 16-bit timer. two 8-bit timer h channels enabling programmable pulse output are provided on chip. (h) watch timer this timer counts the reference time (0.5 seconds) for counting the clock from the subclock (32.768 khz) or f brg (32.768 khz) from the clock generator. at t he same time, the watch timer can be used as an interval timer. chapter 1 introduction preliminary user?s manual u17702ej1v0ud 24 (i) watchdog timer two watchdog timer channels are provided on chip to detect program loops and system abnormalities. watchdog timer 1 can be used as an interval timer. when used as a watchdog timer, it generates a non- maskable interrupt request signal (intwdt1) or system reset signal (wdtres1) after an overflow occurs. when used as an interval timer, it generates a mask able interrupt request signal (intwdtm1) after an overflow occurs. watchdog timer 2 operates by default following reset release. it generates a non-maskable interrupt request signal (intwdt2) or system rese t signal (wdtres2) after an overflow occurs. (j) serial interface (sio) the v850es/kj2 includes four kinds of serial interf aces: an asynchronous serial interface (uartn), a clocked serial interface (csi0n), a clocked serial interface with an automatic transmit/receive function (csiam), and an i 2 c bus interface (i 2 cm). the v850es/kj2 can simultaneously use up to nine channels. for uartn, data is transferred via the txdn and rxdn pins. for csi0n, data is transferred via the so0n, si0n, and sck0n pins. for csiam, data is transferred via the soam, siam, and sckam pins. for i 2 cm, data is transferred via the sdam and sclm pins. remark n = 0 to 2 m = 0, 1 (k) a/d converter this high-speed, high-resolution 10-bit a/d conver ter includes 16 analog input pins. conversion is performed using the successive approximation method. (l) d/a converter two 8-bit resolution d/a converter channels are incl uded on chip. the d/a converter uses the r-2r ladder method. (m) dma controller a 4-channel dma controller is provided on chip. this controller transfers data between the internal ram, on-chip peripheral i/o devices, and external memory in response to interrupt requests sent by on-chip peripheral i/o. (n) key interrupt function a key interrupt request signal (intkr) can be generated by inputting a falling edge to the eight key input pins. (o) real-time output function this function transfers 6-bit data set beforehand to output latches upon occurrence of a timer compare register match signal. a 2-channel 6-bit data real-time out put function is provided on chip. (p) on-chip debug function an on-chip debug function that uses the jtag (joint test action group) communication specifications is provided. switching between the normal port functi on and on-chip debugging function is done with the control pin input level and the on-chip debug mode register (ocdm). the on-chip debug function is available only in the pd70f3734. chapter 1 introduction preliminary user?s manual u17702ej1v0ud 25 (q) ports as shown below, the following ports have general-p urpose port functions and control pin functions. port i/o alternate function p0 7-bit i/o nmi, external interrupt, timer output p1 2-bit i/o d/a converter analog output p3 10-bit i/o serial interface, timer i/o p4 3-bit i/o serial interface p5 6-bit i/o serial interface, timer i/o, ke y interrupt function, real-time output function p6 16-bit i/o serial interface, timer i/o, real-time output function p7 16-bit input a/d converter analog input p8 2-bit i/o serial interface p9 16-bit i/o external address bus, se rial interface, timer i/o, external interrupt, key interrupt function pcd 4-bit i/o ? pcm 6-bit i/o external bus control signal pcs 8-bit i/o chip select output pct 8-bit i/o external bus control signal pdh 8-bit i/o external address bus pdl 16-bit i/o external address/data bus chapter 1 introduction preliminary user?s manual u17702ej1v0ud 26 1.7 overview of functions part number pd70f3733 pd70f3734 rom 128 kb (single-power flash memory) 256 kb (single-power flash memory) internal memory high-speed ram 6 kb 16 kb buffer ram 64 bytes logical space 64 mb memory space external memory area 15 mb external bus interface address bus: 24 bits data bus: 8/16 bits multiplex bus mode/separate bus mode general-purpose registers 32 bits 32 registers ceramic/crystal/external clock when pll not used 2 to 10 mhz: 2.7 to 5.5 v regc pin connected directly to v dd 2 to 5 mhz: 4.5 to 5.5 v, 2 to 4 mhz: 4.0 to 5.5 v, 2 to 2.5 mhz: 2.7 to 5.5 v main clock (oscillation frequency) when pll used 10 f capacitor connected to regc pin 2 to 4 mhz: 4.0 to 5.5 v subclock (oscillation frequency) crystal/external clock (32.768 khz) minimum instruction execution time 50 ns (when main clock operated at (f xx ) = 20 mhz) dsp function 32 32 = 64: 200 to 250 ns (at 20 mhz) 32 32 + 32 = 32: 300 ns (at 20 mhz) 16 16 = 32: 50 to 100 ns (at 20 mhz) 16 16 + 32 = 32: 150 ns (at 20 mhz) i/o ports 128 ? input: 16 ? i/o: 112 (among these, n-ch open-drain output se lectable: 12, fixed to n-ch open-drain output: 6) timer 16-bit timer/counter p: 1 channel 16-bit timer/event counter 0: 6 channels 8-bit timer/event counter 5: 2 channels (16-bit timer/event counter: usable as 1 channel) 8-bit timer h: 2 channels watch timer: 1 channel 8-bit interval timer: 1 channel watchdog timer: 2 channels real-time output port 2 channels: 4 bits 1, 2 bits 1, or 6 bits 1 a/d converter 10-bit resolution 16 channels d/a converter 8-bit resolution 2 channels dma controller 4 channels serial interface csi: 3 channels csia (with automatic transmit/receive function): 2 channels uart: 2 channels uart/i 2 c bus: 1 channel i 2 c bus: 1 channel dedicated baud rate generator: 3 channels interrupt sources external: 9 (9) note , internal: 47 power save function stop/idle/halt/sub-idle mode on-chip debug function none provided operating supply voltage 4.5 to 5.5 v (at 20 mhz)/4.0 to 5.5 v (at 16 mhz)/2.7 to 5.5 v (at 10 mhz) package 144-pin plastic lq fp (fine pitch) (20 20 mm) note the figure in parentheses indicates the number of exte rnal interrupts for which stop mode can be released. preliminary user?s manual u17702ej1v0ud 27 chapter 2 pin functions the names and functions of the pins of the v850es/kj2 are described be low, divided into port pins and non-port pins. the pin i/o buffer power supplies are divided into three systems; av ref0 /av ref1 , bv dd , and ev dd . the relationship between these power supplies and the pins is shown below. table 2-1. pin i/o buffer power supplies power supply corresponding pins av ref0 port 7 av ref1 port 1 bv dd ports cd, cm, cs, ct, dh, dl ev dd reset, ports 0, 3 to 6, 8, 9 2.1 list of pin functions (1) port pins (1/4) pin name pin no. i/o pull-up resistor function alternate function p00 6 toh0 p01 7 toh1 p02 17 nmi p03 18 intp0 p04 19 intp1 p05 note 1 20 intp2/drst note 2 p06 21 i/o yes port 0 i/o port input/output can be specified in 1-bit units. intp3 p10 3 ano0 p11 4 i/o yes port 1 i/o port input/output can be specified in 1-bit units. ano1 p30 25 txd0/to02 p31 26 rxd0/intp7/to03 p32 27 asck0/adtrg/to01 p33 28 ti000/to00/tip00/top00 p34 29 ti001/to00/tip01/top01 p35 30 yes ti010/to01 p36 31 ? p37 32 ? p38 35 sda0 p39 36 i/o no port 3 i/o port input/output can be specified in 1-bit units. p36 to p39 are fixed to n-ch open-drain output. scl0 notes 1. care must be exercised in processing the p05 pin when reset is released. for details, refer to 4.6.3 cautions on p05 pin . 2. only in the pd70f3734 chapter 2 pin functions preliminary user?s manual u17702ej1v0ud 28 (2/4) pin name pin no. i/o pull-up resistor function alternate function p40 22 si00/rxd2 note 1 p41 23 so00/txd2 p42 24 i/o yes port 4 i/o port input/output can be specified in 1-bit units. p41 and p42 can be specified as n-ch open- drain output in 1-bit units. sck00 p50 37 ti011/rtp00/kr0 p51 38 ti50/rtp01/kr1 p52 39 to50/rtp02/kr2/ddi note 2 p53 40 sia0/rtp03/kr3/ddo note 2 p54 41 soa0/rtp04/kr4/dck note 2 p55 42 i/o yes port 5 i/o port input/output can be specified in 1-bit units. p54 and p55 can be specified as n-ch open- drain output in 1-bit units. scka0/rtp05/kr5/dms note 2 p60 43 rtp10 p61 44 rtp11 p62 45 rtp12 p63 46 rtp13 p64 47 rtp14 p65 48 rtp15 p66 49 si02 p67 50 so02 p68 51 sck02 p69 52 ti040 p610 53 ti041 p611 54 to04 p612 55 ti050 p613 56 yes ti051/to05 p614 57 ? p615 58 i/o no port 6 i/o port input/output can be specified in 1-bit units. p67 and p68 can be specified as n-ch open- drain output in 1-bit units. p614 and p615 are fixed to n-ch open-drain output. ? p70 144 ani0 p71 143 ani1 p72 142 ani2 p73 141 ani3 p74 140 ani4 p75 139 ani5 p76 138 ani6 p77 137 ani7 p78 136 ani8 p79 135 ani9 p710 134 input no port 7 input port ani10 notes 1. the v850es/kj2 also assigns the rxd2 pin function to the p80 pin. if the p40 and p80 pins are used as the rxd2 pin simultaneously, the uart2 re ceive operation may not be performed correctly. therefore, do not use the p40 and p80 pins as the rxd2 pin simultaneously. 2. only in the pd70f3734 chapter 2 pin functions preliminary user?s manual u17702ej1v0ud 29 (3/4) pin name pin no. i/o pull-up resistor function alternate function p711 133 ani11 p712 132 ani12 p713 131 ani13 p714 130 ani14 p715 129 input no port 7 input port ani15 p80 59 rxd2 note /sda1 p81 60 i/o yes port 8 i/o port input/output can be specified in 1-bit units. n-ch open-drain output can be specified in 1- bit units. txd2/scl1 p90 61 a0/txd1/kr6 p91 62 a1/rxd1/kr7 p92 63 a2/ti020/to02 p93 64 a3/ti021 p94 65 a4/ti030/to03 p95 66 a5/ti031 p96 67 a6/ti51/to51 p97 68 a7/si01 p98 69 a8/so01 p99 70 a9/sck01 p910 71 a10/sia1 p911 72 a11/soa1 p912 73 a12/scka1 p913 74 a13/intp4 p914 75 a14/intp5 p915 76 i/o yes port 9 i/o port input/output can be specified in 1-bit units. p98, p99, p911, and p912 can be specified as n-ch open-drain output in 1-bit units. a15/intp6 pcd0 77 ? pcd1 78 ? pcd2 79 ? pcd3 80 i/o yes port cd i/o port input/output can be specified in 1-bit units. ? pcm0 85 wait pcm1 86 clkout pcm2 87 hldak pcm3 88 hldrq pcm4 89 ? pcm5 90 i/o yes port cm i/o port input/output can be specified in 1-bit units. ? pcs0 81 cs0 pcs1 82 cs1 pcs2 83 cs2 pcs3 84 cs3 pcs4 91 i/o yes port cs i/o port input/output can be specified in 1-bit units. ? note the v850es/kj2 also assigns the rxd2 pin function to the p40 pin. if the p40 and p80 pins are used as the rxd2 pin simultaneously, the uart2 receive operat ion may not be performed co rrectly. therefore, do not use the p40 and p80 pins as the rxd2 pin simultaneously. chapter 2 pin functions preliminary user?s manual u17702ej1v0ud 30 (4/4) pin name pin no. i/o pull-up resistor function alternate function pcs5 92 ? pcs6 93 ? pcs7 94 i/o yes port cs i/o port input/output can be specified in 1-bit units. ? pct0 95 wr0 pct1 96 wr1 pct2 97 ? pct3 98 ? pct4 99 rd pct5 100 ? pct6 101 astb pct7 102 i/o yes port ct i/o port input/output can be specified in 1-bit units. ? pdh0 121 a16 pdh1 122 a17 pdh2 123 a18 pdh3 124 a19 pdh4 125 a20 pdh5 126 a21 pdh6 127 a22 pdh7 128 i/o yes port dh i/o port input/output can be specified in 1-bit units. a23 pdl0 105 ad0 pdl1 106 ad1 pdl2 107 ad2 pdl3 108 ad3 pdl4 109 ad4 pdl5 110 ad5/flmd1 pdl6 111 ad6 pdl7 112 ad7 pdl8 113 ad8 pdl9 114 ad9 pdl10 115 ad10 pdl11 116 ad11 pdl12 117 ad12 pdl13 118 ad13 pdl14 119 ad14 pdl15 120 i/o yes port dl i/o port input/output can be specified in 1-bit units. ad15 chapter 2 pin functions preliminary user?s manual u17702ej1v0ud 31 (2) non-port pins (1/5) pin name pin no. i/o pull-up resistor function alternate function a0 61 p90/txd1/kr6 a1 62 p91/rxd1/kr7 a2 63 p92/ti020/to02 a3 64 p93/ti021 a4 65 p94/ti030/to03 a5 66 p95/ti031 a6 67 p96/ti51/to51 a7 68 p97/si01 a8 69 p98/so01 a9 70 p99/sck01 a10 71 p910/sia1 a11 72 p911/soa1 a12 73 p912/scka1 a13 74 p913/intp4 a14 75 p914/intp5 a15 76 output yes address bus for external memory (when using a separate bus) p915/intp6 a16 121 pdh0 a17 122 pdh1 a18 123 pdh2 a19 124 pdh3 a20 125 pdh4 a21 126 pdh5 a22 127 pdh6 a23 128 output yes address bus for external memory pdh7 ad0 105 pdl0 ad1 106 pdl1 ad2 107 pdl2 ad3 108 pdl3 ad4 109 pdl4 ad5 110 pdl5/flmd1 ad6 111 pdl6 ad7 112 pdl7 ad8 113 pdl8 ad9 114 pdl9 ad10 115 pdl10 ad11 116 pdl11 ad12 117 pdl12 ad13 118 pdl13 ad14 119 pdl14 ad15 120 i/o yes address/data bus for external memory pdl15 chapter 2 pin functions preliminary user?s manual u17702ej1v0ud 32 (2/5) pin name pin no. i/o pull-up resistor function alternate function adtrg 27 input yes a/d converter external trigger input p32/asck0/to01 ani0 144 p70 ani1 143 p71 ani2 142 p72 ani3 141 p73 ani4 140 p74 ani5 139 p75 ani6 138 p76 ani7 137 p77 ani8 136 p78 ani9 135 p79 ani10 134 p710 ani11 133 p711 ani12 132 p712 ani13 131 p713 ani14 130 p714 ani15 129 input no analog voltage input for a/d converter p715 ano0 3 p10 ano1 4 output yes analog voltage output for d/a converter p11 asck0 27 input yes uart0 serial clock input p32/adtrg/to01 astb 101 output yes address strobe signal output for external memory pct6 av ref0 1 ? ? reference voltage for a/d converter and positive power supply for alternate-function ports ? av ref1 5 ? ? reference voltage for d/a converter and positive power supply for alternate-function ports ? av ss 2 ? ? ground potential for a/d and d/a converters and alternate-function ports ? bv dd 104 ? ? positive power supply for bus interface and alternate-function ports ? bv ss 103 ? ? ground potential for bus interface and alternate-function ports ? clkout 86 output yes internal system clock output pcm1 cs0 81 pcs0 cs1 82 pcs1 cs2 83 pcs2 cs3 84 output yes chip select output pcs3 dck note 41 input yes debug clock input p54/soa0/rtp04/kr4 ddi note 39 input yes debug data input p52/to50/rtp02/kr2 ddo note 40 output yes debug data output p53/sia0/rtp03/kr3 dms note 42 input yes debug mode select input p55/scka0/rtp05/kr5 drst note 20 input yes debug reset input p05/intp2 note only in the pd70f3734 chapter 2 pin functions preliminary user?s manual u17702ej1v0ud 33 (3/5) pin name pin no. i/o pull-up resistor function alternate function ev dd 34 ? ? positive power supply for external ? ev ss 33 ? ? ground potential for external ? flmd0 8 no ? flmd1 110 input yes flash programming mode setting pin pdl5/ad5 hldak 87 output yes bus hold acknowledge output pcm2 hldrq 88 input yes bus hold request input pcm3 intp0 18 p03 intp1 19 p04 intp2 20 external interrupt request input (maskable, analog noise elimination) p05/drst note intp3 21 external interrupt request input (maskable, digital + anal og noise elimination) p06 intp4 74 p913/a13 intp5 75 p914/a14 intp6 76 p915/a15 intp7 26 input yes external interrupt request input (maskable, analog noise elimination) p31/rxd0/to03 kr0 37 p50/ti011/rtp00 kr1 38 p51/ti50/rtp01 kr2 39 p52/to50/rtp02/ddi note kr3 40 p53/sia0/rtp03/ddo note kr4 41 p54/soa0/rtp04/dck note kr5 42 p55/scka0/rtp05/dms note kr6 61 p90/a0/txd1 kr7 62 input yes key return input p91/a1/rxd1 nmi 17 input yes external interrupt input (non-maskable, analog noise elimination) p02 rd 99 output yes read strobe signal output for external memory pct4 regc 10 ? ? connecting capacitor for regulator output stabilization ? reset 14 input ? system reset input ? rtp00 37 p50/ti011/kr0 rtp01 38 p51/ti50/kr1 rtp02 39 p52/to50/kr2/ddi note rtp03 40 p53/sia0/kr3/ddo note rtp04 41 p54/soa0/kr4/dck note rtp05 42 p55/scka0/kr5/dms note rtp10 43 p60 rtp11 44 p61 rtp12 45 p62 rtp13 46 p63 rtp14 47 p64 rtp15 48 output yes real-time output port p65 rxd0 26 input yes serial receive da ta input for uart0 p31/intp7/to03 note only in the pd70f3734 chapter 2 pin functions preliminary user?s manual u17702ej1v0ud 34 (4/5) pin name pin no. i/o pull-up resistor function alternate function rxd1 62 serial receive data input for uart1 p91/a1/kr7 22 p40 note 1 /si00 rxd2 59 input yes serial receive data input for uart2 p80 note 1 /sda1 sck00 24 p42 sck01 70 p99/a9 sck02 51 p68 scka0 42 p55/rtp05/kr5/dms note 2 scka1 73 i/o yes serial clock i/o for cs i00 to csi02, csia0, csia1 n-ch open-drain output can be specified in 1- bit units. p912/a12 scl0 36 no serial clock i/o for i 2 c0 fixed to n-ch open-drain output p39 scl1 60 i/o yes serial clock i/o for i 2 c1 n-ch open-drain output can be specified p81/txd2 sda0 35 no serial transmit/receive data i/o for i 2 c0 fixed to n-ch open-drain output p38 sda1 59 i/o yes serial transmit/receive data i/o for i 2 c1 n-ch open-drain output can be specified p80/rxd2 si00 22 serial receive data input for csi00 p40/rxd2 si01 68 serial receive data input for csi01 p97/a7 si02 49 serial receive data input for csi02 p66 sia0 40 serial receive data input for csia0 p53/rtp03/kr3/ddo note 2 sia1 71 input yes serial receive data input for csia1 p910/a10 so00 23 p41/txd2 so01 69 p98/a8 so02 50 p67 soa0 41 p54/rtp04/kr4/dck note 2 soa1 72 output yes serial transmit data output for csi00 to csi02, csia0, csia1 n-ch open-drain output can be specified in 1- bit units. p911/a11 ti000 28 capture trigger input/external event input for tm00 p33/to00/tip00/top00 ti001 29 capture trigger input for tm00 p34/to00/tip01/top01 ti010 30 capture trigger input/external event input for tm01 p35/to01 ti011 37 capture trigger input for tm01 p50/rtp00/kr0 ti020 63 capture trigger input/external event input for tm02 p92/a2/to02 ti021 64 capture trigger input for tm02 p93/a3 ti030 65 capture trigger input/external event input for tm03 p94/a4/to03 ti031 66 capture trigger input for tm03 p95/a5 ti040 52 capture trigger input/external event input for tm04 p69 ti041 53 capture trigger input for tm04 p610 ti050 55 capture trigger input/external event input for tm05 p612 ti051 56 input yes capture trigger input for tm05 p613/to05 notes 1. the v850es/kj2 assigns the rxd2 pin function to the p40 and p80 pi ns. if the p40 and p80 pins are used as the rxd2 pin simultaneously, the uart2 re ceive operation may not be performed correctly. therefore, do not use the p40 and p80 pins as the rxd2 pin simultaneously. 2. only in the pd70f3734 chapter 2 pin functions preliminary user?s manual u17702ej1v0ud 35 (5/5) pin name pin no. i/o pull-up resistor function alternate function ti50 38 external event input for tm50 p51/rtp01/kr1 ti51 67 external event input for tm51 p96/a6/to51 tip00 28 capture trigger input/external event input/ external trigger input (tmp0) p33/ti000/to00/top00 tip01 29 input yes capture trigger input for tmp0 p34/ti001/to00/top01 28 p33/ti000/tip00/top00 to00 29 timer output for tm00 p34/ti001/tip01/top01 27 p32/asck0/adtrg to01 30 timer output for tm01 p35/ti010 25 p30/txd0 to02 63 timer output for tm02 p92/a2/ti020 26 p31/rxd0/intp7 to03 65 timer output for tm03 p94/a4/ti030 to04 54 timer output for tm04 p611 to05 56 timer output for tm05 p613/ti051 to50 39 timer output for tm50 p52/rtp02/kr2/ddi note to51 67 timer output for tm51 p96/a6/ti51 toh0 6 timer output for tmh0 p00 toh1 7 timer output for tmh1 p01 top00 28 p33/ti000/to00/tip00 top01 29 output yes timer output for tmp0 p34/ti001/to00/tip01 txd0 25 serial transmit data output for uart0 p30/to02 txd1 61 serial transmit data output for uart1 p90/a0/kr6 23 p41/so00 txd2 60 output yes serial transmit data output for uart2 p81/scl1 v dd 9 ? ? positive power s upply pin for internal ? v ss 11 ? ? ground potential for internal ? wait 85 input yes external wait input pcm0 wr0 95 write strobe for external memory (lower 8 bits) pct0 wr1 96 output yes write strobe for external memory (higher 8 bits) pct1 x1 12 input no ? x2 13 ? no connecting resonator for main clock ? xt1 15 input no ? xt2 16 ? no connecting resonator for subclock ? note only in the pd70f3734 chapter 2 pin functions preliminary user?s manual u17702ej1v0ud 36 2.2 pin status the address bus becomes undefined during accesses to the internal ram and rom. the data bus goes into the high-impedance state without data output. the external bus control signal becomes inactive. during peripheral i/o access, the address bus outputs t he addresses of the on-chip peripheral i/os that are accessed. the data bus goes into t he high-impedance state without data output. the external bus control signal becomes inactive. table 2-2. pin operation status in operation modes operating status pin reset note 1 halt mode idle mode/ stop mode idle state note 2 bus hold ad0 to ad15 (pdl0 to pdl15) hi-z note 3 hi-z held hi-z a0 to a15 (p90 to p915) hi-z undefined note 4 hi-z held hi-z a16 to a23 (pdh0 to pdh7) hi -z undefined hi-z held hi-z wait (pcm0) hi-z ? ? ? ? clkout (pcm1) hi-z operat ing l operating operating cs0 to cs3 (pcs0 to pcs3) hi-z h h held hi-z wr0, wr1 (pct0, pct1) hi-z h h h hi-z rd (pct4) hi-z h h h hi-z astb (pct6) hi-z h h h hi-z hldak (pcm2) hi-z operating h h l hldrq (pcm3) hi-z o perating ? ? operating notes 1. since the bus control pin is also used as a port pin, it is initialized to the port mode (input) after reset. 2. the pin statuses in the idle stat e inserted after the t3 state in the multiplex bus mode and after the t2 state in the separate bus mode are listed. 3. in separate bus mode: hi-z in multiplex bus mode: undefined 4. only in separate bus mode remark hi-z: high impedance h: high-level output l: low-level output ?: input without sampling (in put acknowledgment not possible) chapter 2 pin functions preliminary user?s manual u17702ej1v0ud 37 2.3 pin i/o circuits and recommend ed connection of unused pins (1/3) pin alternate function pin no. i/o circuit type recommended connection p00 toh0 6 p01 toh1 7 5-a p02 nmi 17 p03, p04 intp0, intp1 18, 19 intp2 note 1 5-w p05 intp2/drst note 2 20 5-af p06 intp3 21 5-w input: independently connect to ev dd or ev ss via a resistor. output: leave open. p10 ano0 3 p11 ano1 4 12-b input: independently connect to av ref1 or av ss via a resistor. output: leave open. p30 txd0/to02 25 5-a p31 rxd0/intp7/to03 26 p32 asck0/adtrg/to01 27 p33 ti000/to00/tip00/top00 28 p34 ti001/to00/tip01/top01 29 p35 ti010/to01 30 5-w p36, p37 ? 31, 32 13-ah p38 sda0 35 p39 scl0 36 13-ae p40 si00/rxd2 22 5-w p41 so00/txd2 23 10-e p42 sck00 24 10-f p50 ti011/rtp00/kr0 37 p51 ti50/rtp01/kr1 38 p52 to50/rtp02/kr2/ddi note 2 39 p53 sia0/rtp03/kr3/ddo note 2 40 8-a p54 soa0/rtp04/kr4/dck note 2 41 p55 scka0/rtp05/kr5/dms note 2 42 10-a p60 to p65 rtp10 to rtp15 43 to 48 5-a p66 si02 49 5-w p67 so02 50 10-e p68 sck02 51 10-f p69 ti040 52 p610 ti041 53 5-w p611 to04 54 5-a p612 ti050 55 p613 ti051/to05 56 5-w p614, p615 ? 57, 58 13-ah input: independently connect to ev dd or ev ss via a resistor. output: leave open. p70 to p715 ani0 to ani15 144 to 129 9-c connect to av ref0 or av ss . notes 1. only in the pd70f3733 2. only in the pd70f3734 chapter 2 pin functions preliminary user?s manual u17702ej1v0ud 38 (2/3) pin alternate function pin no. i/o circuit type recommended connection p80 rxd2/sda1 59 p81 txd2/scl1 60 10-f p90 a0/txd1/kr6 61 p91 a1/rxd1/kr7 62 p92 a2/ti020/to02 63 8-a p93 a3/ti021 64 5-w p94 a4/ti030/to03 65 8-a p95 a5/ti031 66 5-w p96 a6/ti51/to51 67 8-a p97 a7/si01 68 5-w p98 a8/so01 69 10-e p99 a9/sck01 70 10-f p910 a10/sia1 71 5-w p911 a11/soa1 72 10-e p912 a12/scka1 73 10-f p913 to p915 a13/intp4 to a15/intp6 74 to 76 5-w input: independently connect to ev dd or ev ss via a resistor. output: leave open. pcd0 to pcd3 ? 77 to 80 5-a pcm0 wait 85 pcm1 clkout 86 pcm2 hldak 87 pcm3 hldrq 88 pcm4, pcm5 ? 89, 90 5-a pcs0, pcs1 cs0, cs1 81, 82 pcs2, pcs3 cs2, cs3 83, 84 pcs4 to pcs7 ? 91 to 94 5-a pct0 wr0 95 pct1 wr1 96 pct2, pct3 ? 97, 98 pct4 rd 99 pct5 ? 100 pct6 astb 101 pct7 ? 102 5-a pdl0 to pdl4 ad0 to ad4 105 to 109 pdl5 ad5/flmd1 110 pdl6 to pdl15 ad6 to ad15 111 to 120 5-a pdh0 to pdh7 a16 to a23 121 to 128 5-a input: independently connect to bv dd or bv ss via a resistor. output: leave open. av ref0 ? 1 ? directly connect to v dd . av ref1 ? 5 ? directly connect to v dd . av ss ? 2 ? ? chapter 2 pin functions preliminary user?s manual u17702ej1v0ud 39 (3/3) pin alternate function pin no. i/o circuit type recommended connection bv dd ? 104 ? ? bv ss ? 103 ? ? ev dd ? 34 ? ? ev ss ? 33 ? ? reset ? 14 2 connect to ev dd via a resistor. flmd0 ? 8 ? directly connect to ev ss or v ss or pull down with a 10 k ? resistor. v dd ? 9 ? ? v ss ? 11 ? ? x1 ? 12 ? ? x2 ? 13 ? ? xt1 ? 15 16 directly connect to v ss note . xt2 ? 16 16 leave open. note be sure to set the psmr.xtstp bit to 1 when this pin is not used. chapter 2 pin functions preliminary user?s manual u17702ej1v0ud 40 2.4 pin i/o circuits (1/2) type 2 type 9-c type 5-a type 10-a type 5-w type 10-e type 8-a schmitt-triggered input with hysteresis characteristics in data output disable p-ch in/out v dd n-ch input enable p-ch v dd pull-up enable in comparator + ? av ref0 (threshold voltage) p-ch av ss n-ch input enable pull-up enable data output disable input enable v dd p-ch v dd p-ch in/out n -ch data output disable v dd p-ch in/out n-ch open drain pull-up enable v dd p-ch data output disable v dd p-ch in/out n-ch open drain input enable pull-up enable v dd p-ch pull-up enable data output disable v dd p-ch v dd p-ch in/out n-ch v ss v ss v ss v ss v ss type 5- af pull-up enable pull-down enable data output disable input enable v dd p-ch v dd p-ch in/out n -ch n -ch chapter 2 pin functions preliminary user?s manual u17702ej1v0ud 41 (2/2) type 12-b type 13-ab type 13-ad type 16 p-ch feedback cut-off xt1 xt2 pull-up enable data output disable input enable av ref1 p-ch av ref1 p-ch in/out n-ch p-ch n-ch analog output voltage av ss data output disable input enable in/out n -ch v ss output disable rd in/out n-ch data medium-voltage input buffer v dd p-ch v ss port read type 10-f data output disable v dd p-ch in/out n-ch open drain input enable pull-up enable v dd p-ch v ss remark read v dd as ev dd or bv dd . also, read v ss as ev ss or bv ss . preliminary user?s manual u17702ej1v0ud 42 chapter 3 cpu functions the cpu of the v850es/kj2 is based on the risc architec ture and executes most instructions in one clock cycle by using 5-stage pipeline control. 3.1 features { number of instructions: 83 { minimum instruction execution time: 50.0 ns (@ 20 mhz operation: 4.5 to 5.5 v, regc = v dd ) 62.5 ns (@ 16 mhz operation: 4.0 to 5.5 v, regc = 10 f) 100 ns (@ 10 mhz operation: 2.7 to 5.5 v, regc = v dd ) { memory space program (physical address) space: 64 mb linear data (logical address) space: 4 gb linear ? memory block division function: 2 mb, 2 mb, 4 mb, 8 mb/total of 4 blocks { general-purpose registers: 32 bits 32 { internal 32-bit architecture { 5-stage pipeline control { multiply/divide instructions { saturated operation instructions { 32-bit shift instruction: 1 clock { load/store instruction with long/short format { four types of bit manipulation instructions ? set1 ? clr1 ? not1 ? tst1 chapter 3 cpu functions preliminary user?s manual u17702ej1v0ud 43 3.2 cpu register set the cpu registers of the v850es/kj2 can be classified in to two categories: a general-purpose program register set and a dedicated system register set. all the registers have 32-bit width. for details, refer to the v850es architecture user?s manual . (1) program register set (2) system register set r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13 r14 r15 r16 r17 r18 r19 r20 r21 r22 r23 r24 r25 r26 r27 r28 r29 r30 r31 (zero register) (assembler-reserved register) (stack pointer (sp)) (global pointer (gp)) (text pointer (tp)) (element pointer (ep)) (link pointer (lp)) pc (program counter) psw (program status word) ecr (interrupt source register) fepc fepsw (nmi status saving register) (nmi status saving register) eipc eipsw (interrupt status saving register) (interrupt status saving register) 31 0 31 0 31 0 ctbp (callt base pointer) dbpc dbpsw (exception/debug trap status saving register) (exception/debug trap status saving register) ctpc ctpsw (callt execution status saving register) (callt execution status saving register) chapter 3 cpu functions preliminary user?s manual u17702ej1v0ud 44 3.2.1 program register set the program register set includes general-p urpose registers and a program counter. (1) general-purpose registers (r0 to r31) thirty-two general-purpose registers, r0 to r31, are available. all of these registers c an be used as a data variable or address variable. however, r0 and r30 are implicitly us ed by instructions and care must be ex ercised when using these registers. r0 always holds 0 and is used for operations that use 0 and offset 0 addressing. r30 is used as a base pointer when performing memory access with the sld and sst instructions. also, r1, r3 to r5, and r31 are implicitly used by the assembler and c compiler. t herefore, before using these registers, their contents mu st be saved so that they are not lost, and they must be restor ed to the registers after the registers have been used. there are cases when r2 is used by the real-time os. if r2 is not used by the real-time os, r2 can be used as a variable register. table 3-1. program registers name usage operation r0 zero register always holds 0 r1 assembler-reserved regist er working register for generating 32-bit immediate r2 address/data variable register (when r2 is not used by the real-time os to be used) r3 stack pointer used to generate stack frame when function is called r4 global pointer used to acce ss global variable in data area r5 text pointer register to indicate the start of the text area (area for placing program code) r6 to r29 address/data variable register r30 element pointer base pointer when memory is accessed r31 link pointer used by compiler when calling function pc program counter holds instruction address during program execution (2) program counter (pc) this register holds the address of the in struction under execution. the lower 26 bits of this register are valid, and bits 31 to 26 are fixed to 0. if a carry occu rs from bit 25 to bit 26, it is ignored. bit 0 is fixed to 0, and branching to an odd address cannot be performed. 31 26 25 1 0 pc fixed to 0 instruction address under execution 0 after reset 00000000h chapter 3 cpu functions preliminary user?s manual u17702ej1v0ud 45 3.2.2 system register set system registers control the status of the cpu and hold interrupt information. read from and write to system regist ers are performed by setting the system register numbers shown below with the system register load/st ore instructions (ldsr, stsr instructions). table 3-2. system register numbers operand specification enabled system register no. system register name ldsr instruction stsr instruction 0 interrupt status saving register (eipc) note 1 yes yes 1 interrupt status saving register (eipsw) note 1 yes yes 2 nmi status saving register (fepc) note 1 yes yes 3 nmi status saving register (fepsw) note 1 yes yes 4 interrupt source register (ecr) no yes 5 program status word (psw) yes yes 6 to 15 reserved numbers for future function expansion (the operation is not guaranteed if accessed.) no no 16 callt execution status saving register (ctpc) yes yes 17 callt execution status saving register (ctpsw) yes yes 18 exception/debug trap status saving register (dbpc) yes note 2 yes note 2 19 exception/debug trap status saving register (dbpsw) yes note 2 yes note 2 20 callt base pointer (ctbp) yes yes 21 to 31 reserved numbers for future function expansion (the operation is not guaranteed if accessed.) no no notes 1. since only one set of these registers is available, the contents of this register must be saved by the program when multiple interrupt servicing is enabled. 2. these registers can be accessed only during the interval between the execution of the dbtrap instruction or illegal opcode and the dbret instruction. caution even if bit 0 of eipc, fepc, or ctpc is set (1) by the ldsr instruction, bit 0 is ignored during return with the reti instruction following interrupt servicing (because bit 0 of pc is fixed to 0). when setting a value to eipc, fepc, and ctpc, set an even number (bit 0 = 0). chapter 3 cpu functions preliminary user?s manual u17702ej1v0ud 46 (1) interrupt status saving registers (eipc, eipsw) there are two interrupt status sa ving registers, eipc and eipsw. upon occurrence of a software exception or a maskable interrupt, the contents of the program counter (pc) are saved to eipc and the contents of the program status word (psw) are saved to eipsw (upon occurrence of a non-maskable interrupt (nmi), t he contents are saved to the nmi status saving registers (fepc, fepsw)). the address of the next instruction fo llowing the instruction executed when a software exception or maskable interrupt occurs is saved to eipc, e xcept for some instructions (refer to 21.9 period in which interrupts are not acknowledged by cpu ). the current psw contents are saved to eipsw. since there is only one set of interrupt status saving registers, the contents of these registers must be saved by the program when multiple interrupt servicing is enabled. bits 31 to 26 of eipc and bits 31 to 8 of eipsw are rese rved (fixed to 0) for future function expansion. when the reti instruction is execut ed, the values in eipc and eipsw are restored to the pc and psw, respectively. 31 0 eipc (pc contents saved) 0 0 after reset 0xxxxxxxh (x: undefined) 26 25 0 0 0 0 31 0 eipsw (psw contents saved) 0 0 after reset 000000xxh (x: undefined) 8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7 chapter 3 cpu functions preliminary user?s manual u17702ej1v0ud 47 (2) nmi status saving registers (fepc, fepsw) there are two nmi status saving registers, fepc and fepsw. upon occurrence of a non-maskable interrupt (nmi), the contents of the program co unter (pc) are saved to fepc and the contents of the program status word (psw) are saved to fepsw. the address of the next instruction fo llowing the instruction executed when a non-maskable interrupt occurs is saved to fepc, except fo r some instructions. the current psw contents are saved to fepsw. since there is only one set of nmi stat us saving registers, the contents of these registers must be saved by the program when multiple interrupt servicing is performed. bits 31 to 26 of fepc and bits 31 to 8 of fepsw are re served (fixed to 0) for future function expansion. 31 0 fepc (pc contents saved) 0 0 after reset 0xxxxxxxh (x: undefined) 26 25 0 0 0 0 31 0 fepsw (psw contents saved) 0 0 after reset 000000xxh (x: undefined) 8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7 (3) interrupt source register (ecr) upon occurrence of an interrupt or an exception, the inte rrupt source register (ecr) holds the source of an interrupt or an exception. the value held by ecr is the exception code c oded for each interrupt source. this register is a read-only register, and thus data cannot be written to it using the ldsr instruction. 31 0 ecr fecc eicc after reset 00000000h 16 15 bit position bit name description 31 to 16 fecc non-maskable interrupt (nmi) exception code 15 to 0 eicc exception, maskable interrupt exception code chapter 3 cpu functions preliminary user?s manual u17702ej1v0ud 48 (4) program status word (psw) the program status word (psw) is a collection of flags that indicate the program status (instruction execution result) and the cpu status. when the contents of this register are changed using the ldsr instruct ion, the new contents become valid immediately following completion of ldsr instruction execution. interrupt request acknowledgment is held pending while a write to the psw is being executed by the ldsr instruction. bits 31 to 8 are reserved (fixed to 0) for future function expansion. (1/2) 31 0 psw rfu after reset 00000020h 87 np 6 ep 5 id 4 sat 3 cy 2 ov 1 sz bit position flag name description 31 to 8 rfu reserved field. fixed to 0. 7 np indicates that non-maskable interrupt (nmi) servici ng is in progress. this flag is set to 1 when an nmi request is acknowledged, and disables multiple interrupts. 0: nmi servicing not in progress 1: nmi servicing in progress 6 ep indicates that exception processing is in prog ress. this flag is set to 1 when an exception occurs. moreover, interrupt requests can be acknowledged even when this bit is set. 0: exception processing not in progress 1: exception processing in progress 5 id indicates whether maskable interrupt r equest acknowledgment is enabled. 0: interrupt enabled 1: interrupt disabled 4 sat note indicates that the result of executing a saturated operation instruction has overflowed and that the calculation result is saturated. since this is a cumulative flag, it is set to 1 when the result of a saturated operation instruction becomes saturated, and it is not cleared to 0 even if the operation results of successive instructions do no t become saturated. this flag is neither set nor cleared when arithmetic operation instructions are executed. 0: not saturated 1: saturated 3 cy indicates whether carry or borrow occu rred as the result of an operation. 0: no carry or borrow occurred 1: carry or borrow occurred 2 ov note indicates whether overflow o ccurred during an operation. 0: no overflow occurred 1: overflow occurred. 1 s note indicates whether the result of an operation is negative. 0: operation result is positive or 0. 1: operation result is negative. 0 z indicates whether operation result is 0. 0: operation result is not 0. 1: operation result is 0. remark note is explained on the following page. chapter 3 cpu functions preliminary user?s manual u17702ej1v0ud 49 (2/2) note during saturated operation, the saturated operation results are det ermined by the contents of the ov flag and s flag. the sat flag is set (to 1) only when the ov flag is set (to 1) during saturated operation. flag status operation result status sat ov s saturated operation result maximum positive value exceeded 1 1 0 7fffffffh maximum negative value exceeded 1 1 1 80000000h positive (maximum value not exceeded) 0 negative (maximum value not exceeded) holds value before operation 0 1 actual operation result (5) callt execution status saving registers (ctpc, ctpsw) there are two callt execut ion status saving registers, ctpc and ctpsw. when the callt instruction is execut ed, the contents of the program count er (pc) are saved to ctpc, and the program status word (psw) contents are saved to ctpsw. the contents saved to ctpc consist of the address of the next instructi on after the callt instruction. the current psw contents are saved to ctpsw. bits 31 to 26 of ctpc and bits 31 to 8 of ctpsw are re served (fixed to 0) for future function expansion. 31 0 ctpc (pc contents saved) 0 0 after reset 0xxxxxxxh (x: undefined) 26 25 0 0 0 0 31 0 ctpsw (psw contents saved) 0 0 after reset 000000xxh (x: undefined) 8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7 chapter 3 cpu functions preliminary user?s manual u17702ej1v0ud 50 (6) exception/debug trap status saving registers (dbpc, dbpsw) there are two exception/de bug trap status saving registers, dbpc and dbpsw. upon occurrence of an exception trap or debug trap, the contents of the program counter (pc) are saved to dbpc, and the program status word (psw) contents are saved to dbpsw. the contents saved to dbpc consist of the address of the next instructi on after the instruction executed when an exception trap or debug trap occurs. the current psw contents are saved to dbpsw. bits 31 to 26 of dbpc and bits 31 to 8 of dbpsw are re served (fixed to 0) for future function expansion. 31 0 dbpc (pc contents saved) 0 0 after reset 0xxxxxxxh (x: undefined) 26 25 0 0 0 0 31 0 dbpsw (psw contents saved) 0 0 after reset 000000xxh (x: undefined) 8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7 (7) callt base pointer (ctbp) the callt base pointer (ctbp) is used to specify table addresses and generate target addresses (bit 0 is fixed to 0). bits 31 to 26 are reserved (fixed to 0) for future function expansion. 31 0 ctbp (base address) 0 0 after reset 0xxxxxxxh (x: undefined) 26 25 0 0 0 0 0 chapter 3 cpu functions preliminary user?s manual u17702ej1v0ud 51 3.3 operating modes the v850es/kj2 has the following operating modes. (1) normal operating mode after the system has been released from the reset state, t he pins related to the bus in terface are set to the port mode, execution branches to the reset entry address of the internal rom, and instruction processing is started. (2) flash memory programming mode when this mode is specified, the internal flash me mory can be programmed by using a flash programmer. (a) specifying operating mode the operating mode is specified acco rding to the status (input leve l) of the flmd0 and flmd1 pins. in the normal operating mode, input a low level to the flmd0 pin during the reset period. a high level is input to the flmd0 pin by the flash programmer in the flash memory programming mode if a flash programmer is connected. in the self-programming mode, input a high level to this pin from an external circuit. fix the specification of these pins in the application system and do not change the setting of these pins during operation. flmd0 flmd1 operating mode l normal operating mode h l flash memory programming mode h h setting prohibited remark h: high level l: low level : don?t care chapter 3 cpu functions preliminary user?s manual u17702ej1v0ud 52 3.4 address space 3.4.1 cpu address space for instruction addressing, up to a combined total of 16 mb of external memory area and internal rom area, plus an internal ram area, are supported in a linear addres s space (program space) of up to 64 mb. for operand addressing (data access), up to 4 gb of a linear address spac e (data space) is supported. the 4 gb address space, however, is viewed as 64 images of a 64 mb physical addre ss space. this means that the same 64 mb physical address space is accessed regardless of the value of bits 31 to 26. figure 3-1. address space image program space internal ram area access-prohibited area reserved area external memory area internal rom area (external memory) data space image 63 image 1 image 0 on-chip peripheral i/o area internal ram area access-prohibited area external memory area internal rom area (external memory) 16 mb 4 gb 64 mb 64 mb chapter 3 cpu functions preliminary user?s manual u17702ej1v0ud 53 3.4.2 wraparound of cpu address space (1) program space of the 32 bits of the program counter (p c), the higher 6 bits are fixed to 0 and only the lower 26 bits are valid. even if a carry or borrow occurs from bit 25 to bit 26 as a result of branch address calc ulation, the higher 6 bits ignore this and remain 0. therefore, the lower-limit address of the program space, 0000 0000h, and the upper-limit address, 03ffffffh, are contiguous addresses, and the program space is wrapped around at the boundary of these addresses. caution no instructions can be fetched from the 4 kb area of 03fff000h to 03ffffffh because this area is an on-chip peripheral i/o area. the refore, do not execute any branch operation instructions in which the destination addres s will reside in any part of this area. 03fffffeh 03ffffffh 00000000h 00000001h program space program space (+) direction (?) direction (2) data space the result of an operand address calculation that exceeds 32 bits is ignored. therefore, the lower-limit addre ss of the data space, address 0000 0000h, and the upper-limit address, ffffffffh, are contiguous addresses, and the data space is wrapped around at t he boundary of these addresses. fffffffeh ffffffffh 00000000h 00000001h data space data space (+) direction (?) direction chapter 3 cpu functions preliminary user?s manual u17702ej1v0ud 54 3.4.3 memory map the v850es/kj2 has reserved areas as shown below. figure 3-2. data memory map (physical addresses) 3ffffffh 3fec000h 3febfffh 1000000h 0ffffffh 0800000h 07fffffh 0400000h 03fffffh 0200000h 01fffffh 0000000h 01fffffh 0100000h 00fffffh 3fff000h 3ffefffh 3fff000h 3ffefffh 3ffffffh 0000000h 3fec000h (80 kb) access-prohibited area external memory area (8 mb) internal rom area note (1 mb) external memory area (1 mb) internal ram area (60 kb) on-chip peripheral i/o area (4 kb) access-prohibited area external memory area (4 mb) external memory area (2 mb) (2 mb) cs0 cs1 cs2 cs3 note fetch access and read access to addresses 0000000h to 00fffffh is performed for the internal rom area, but in the case of data write access, it is performed for an external memory area. chapter 3 cpu functions preliminary user?s manual u17702ej1v0ud 55 figure 3-3. program memory map 03ff0000h 03feffffh 03fff000h 03ffefffh 03ffffffh 01000000h 00ffffffh 00800000h 007fffffh 00400000h 003fffffh 00100000h 000fffffh 00200000h 001fffffh 00000000h internal ram area (60 kb) access-prohibited area (program fetch disabled area) access-prohibited area (program fetch disabled area) external memory area (8 mb) external memory area (4 mb) external memory area (1 mb) external memory area (2 mb) internal rom area (1 mb) cs0 cs1 cs2 cs3 chapter 3 cpu functions preliminary user?s manual u17702ej1v0ud 56 3.4.4 areas (1) internal rom area an area of 1 mb from 0000000h to 00fffffh is reserved for the internal rom area. (a) internal rom (256 kb) a 256 kb area from 0000000h to 003ffffh is provided in the fo llowing products. addresses 0040000h to 00fffffh are an access-prohibited area. ? pd70f3734 figure 3-4. internal rom area (256 kb) 00fffffh 0040000h 003ffffh 0000000h access-prohibited area internal rom area (256 kb) chapter 3 cpu functions preliminary user?s manual u17702ej1v0ud 57 (b) internal rom (128 kb) a 128 kb area from 0000000h to 001ffffh is provided in the fo llowing products. addresses 0020000h to 00fffffh are an access-prohibited area. ? pd70f3733 figure 3-5. internal rom area (128 kb) 00fffffh 0020000h 001ffffh 0000000h access-prohibited area internal rom area (128 kb) (2) internal ram area an area of 60 kb maximum from 3ff0000h to 3ffef ffh is reserved for the internal ram area. (a) internal ram (16 kb) a 16 kb area from 3ffb000h to 3ffefffh is provided as physical internal ram. addresses 3ff0000h to 3ffafffh ar e an access-prohibited area. ? pd70f3734 figure 3-6. internal ram area (16 kb) internal ram area (16 kb) access-prohibited area 3ffefffh physical address space fffefffh logical address space 3ffb000h 3ffafffh fffb000h fffafffh 3ff0000h fff0000h chapter 3 cpu functions preliminary user?s manual u17702ej1v0ud 58 (b) internal ram (6 kb) a 6 kb area from 3ffb000h to 3ffc7ffh is provided as physical internal ram. addresses 3ff0000h to 3ffafffh and 3ffc800h to 3ffefffh are an access-prohibited area. ? pd70f3733 figure 3-7. internal ram area (6 kb) access-prohibited area access-prohibited area 3ffefffh 3ffc800h 3ffc7ffh 3ff0000h fffefffh fffc800h fffc7ffh fff0000h physical address space logical address space internal ram area (6 kb) 3ffb000h 3ffafffh fffb000h fffafffh chapter 3 cpu functions preliminary user?s manual u17702ej1v0ud 59 (3) on-chip peripheral i/o area a 4 kb area from 3fff000h to 3ffffffh is rese rved as the on-chip peripheral i/o area. figure 3-8. on-chip peripheral i/o area 3ffffffh 3fff000h on-chip peripheral i/o area (4 kb) fffffffh ffff000h physical address space logical address space peripheral i/o registers assigned with functions such as on-chip peripheral i/o operation mode specification and state monitoring are mapped to the on-chip peripheral i/o area. program fetches are not allowed in this area. cautions 1. if word access of a register is atte mpted, halfword access to th e word area is performed twice, first for the lower bits , then for the higher bits, ignoring the lower 2 address bits. 2. if a register that can be accessed in byte units is accessed in halfword units, the higher 8 bits become undefined if the access is a read operation. if a write access is performed, only the data in the lower 8 bits is written to the register. 3. addresses that are not defined as registers are reserved for future expansion. if these addresses are accessed, the operation is undefined and not guaranteed. (4) external memory area 15 mb (0100000h to 0ffffffh) are provided as the external memory area. for details, refer to chapter 5 bus control function . chapter 3 cpu functions preliminary user?s manual u17702ej1v0ud 60 3.4.5 recommended use of address space the architecture of the v850es/kj2 r equires that a register that serves as a pointer be secured for address generation when operand data in t he data space is accessed. the address stored in this pointer 32 kb can be directly accessed by an instruction for operand data. be cause the number of general-pur pose registers that can be used as a pointer is limited, however, by keeping the performance from dropping during address calculation when a pointer value is changed, as many general-purpose regist ers as possible can be secured for variables, and the program size can be reduced. (1) program space of the 32 bits of the pc (program count er), the higher 6 bits are fixed to 0, and only the lower 26 bits are valid. regarding the program space, theref ore, a 64 mb space of contiguous addresses starting from 00000000h unconditionally corresponds to the memory map. to use the internal ram area as the pr ogram space, access following addresses. ram size access address 6 kb 3ffb000h to 3ffc7ffh 16 kb 3ffb000h to 3ffefffh (2) data space with the v850es/kj2, it seems that there are sixty-four 64 mb addres s spaces on the 4 gb cpu address space. therefore, the least signific ant bit (bit 25) of a 26-bit address is sign-extended to 32 bits and allocated as an address. chapter 3 cpu functions preliminary user?s manual u17702ej1v0ud 61 (a) application example of wraparound if r = r0 (zero register) is specified for the ld/st disp16 [r] instruction, a range of addresses 00000000h 32 kb can be addressed by sign-extended disp16. all the resources, including the internal hardware, can be addressed by one pointer. the zero register (r0) is a register fixed to 0 by har dware, and practically elimin ates the need for registers dedicated to pointers. example : pd70f3734 internal rom area on-chip peripheral i/o area access-prohibited area 3 2 kb 4 kb 12 kb (r = ) 0001ffffh 00007fffh 00000000h fffff000h ffffefffh ffff8000h internal ram area ffffb000h ffffafffh 16 kb chapter 3 cpu functions preliminary user?s manual u17702ej1v0ud 62 figure 3-9. recommended memory map data space program space on-chip peripheral i/o on-chip peripheral i/o internal ram internal ram internal rom external memory use prohibited external memory use prohibited internal ram on-chip peripheral i/o note program space 64 mb internal rom internal rom ffffffffh fffff000h ffffefffh fffec000h fffebfffh 04000000h 03ffffffh 03fff000h 03ffefffh 03ffb000h 03ffafffh 03fec000h 03febfffh 01000000h 00ffffffh 00040000h 0003ffffh 00100000h 000fffffh 00000000h xfffffffh xffff000h xfffefffh xfffb000h xfffafffh xfff0000h xffeffffh x0100000h x00fffffh x0000000h note access to this area is prohibited. to access the on-chip peripheral i/o in th is area, specify addresses ffff000h to fffffffh. remarks 1. indicates the recommended area. 2. this figure is the recommended memory map of the pd70f3734. chapter 3 cpu functions preliminary user?s manual u17702ej1v0ud 63 3.4.6 peripheral i/o registers (1/13) operable bit unit address function register name symbol r/w 1 8 16 after reset fffff004h port dl register pdl r/w 0000h note fffff004h port dl register l pdll r/w 00h note fffff005h port dl register h pdlh r/w 00h note fffff006h port dh register pdh r/w 00h note fffff008h port cs register pcs r/w 00h note fffff00ah port ct register pct r/w 00h note fffff00ch port cm register pcm r/w 00h note fffff00eh port cd register pcd r/w 00h note fffff024h port dl mode register pmdl r/w ffffh fffff024h port dl mode register l pmdll r/w ffh fffff025h port dl mode register h pmdlh r/w ffh fffff026h port dh mode register pmdh r/w ffh fffff028h port cs mode register pmcs r/w ffh fffff02ah port ct mode register pmct r/w ffh fffff02ch port cm mode register pmcm r/w ffh fffff02eh port cd mode register pmcd r/w ffh fffff044h port dl mode control register pmcdl r/w 0000h fffff044h port dl mode control register l pmcdll r/w 00h fffff045h port dl mode control register h pmcdlh r/w 00h fffff046h port dh mode control register pmcdh r/w 00h fffff048h port cs mode control register pmccs r/w 00h fffff04ah port ct mode control register pmcct r/w 00h fffff04ch port cm mode control register pmccm r/w 00h fffff066h bus size configuration register bsc r/w 5555h fffff06eh system wait control register vswc r/w 77h fffff080h dma source address register 0l dsa0l r/w undefined fffff082h dma source address register 0h dsa0h r/w undefined fffff084h dma destination address register 0l dda0l r/w undefined fffff086h dma destination address register 0h dda0h r/w undefined fffff088h dma source address register 1l dsa1l r/w undefined fffff08ah dma source address register 1h dsa1h r/w undefined fffff08ch dma destination address register 1l dda1l r/w undefined fffff08eh dma destination address register 1h dda1h r/w undefined fffff090h dma source address register 2l dsa2l r/w undefined fffff092h dma source address register 2h dsa2h r/w undefined fffff094h dma destination address register 2l dda2l r/w undefined fffff096h dma destination address register 2h dda2h r/w undefined fffff098h dma source address register 3l dsa3l r/w undefined fffff09ah dma source address register 3h dsa3h r/w undefined fffff09ch dma destination address register 3l dda3l r/w undefined note the output latch is 00h or 0000h. when input, the pin status is read. chapter 3 cpu functions preliminary user?s manual u17702ej1v0ud 64 (2/13) operable bit unit address function register name symbol r/w 1 8 16 after reset fffff09eh dma destination address register 3h dda3h r/w undefined fffff0c0h dma byte count register 0 dbc0 r/w undefined fffff0c2h dma byte count register 1 dbc1 r/w undefined fffff0c4h dma byte count register 2 dbc2 r/w undefined fffff0c6h dma byte count register 3 dbc3 r/w undefined fffff0d0h dma addressing control register 0 dadc0 r/w 0000h fffff0d2h dma addressing control register 1 dadc1 r/w 0000h fffff0d4h dma addressing control register 2 dadc2 r/w 0000h fffff0d6h dma addressing control register 3 dadc3 r/w 0000h fffff0e0h dma channel control register 0 dchc0 r/w 00h fffff0e2h dma channel control register 1 dchc1 r/w 00h fffff0e4h dma channel control register 2 dchc2 r/w 00h fffff0e6h dma channel control register 3 dchc3 r/w 00h fffff100h interrupt mask register 0 imr0 r/w ffffh fffff100h interrupt mask register 0l imr0l r/w ffh fffff101h interrupt mask register 0h imr0h r/w ffh fffff102h interrupt mask register 1 imr1 r/w ffffh fffff102h interrupt mask register 1l imr1l r/w ffh fffff103h interrupt mask register 1h imr1h r/w ffh fffff104h interrupt mask register 2 imr2 r/w ffffh fffff104h interrupt mask register 2l imr2l r/w ffh fffff105h interrupt mask register 2h imr2h r/w ffh fffff106h interrupt mask register 3 imr3 r/w ffffh fffff106h interrupt mask register 3l imr3l r/w ffh fffff107h interrupt mask register 3h imr3h r/w ffh fffff110h interrupt control register wdt1ic r/w 47h fffff112h interrupt control register pic0 r/w 47h fffff114h interrupt control register pic1 r/w 47h fffff116h interrupt control register pic2 r/w 47h fffff118h interrupt control register pic3 r/w 47h fffff11ah interrupt control register pic4 r/w 47h fffff11ch interrupt control register pic5 r/w 47h fffff11eh interrupt control register pic6 r/w 47h fffff120h interrupt control register tm0ic00 r/w 47h fffff122h interrupt control register tm0ic01 r/w 47h fffff124h interrupt control register tm0ic10 r/w 47h fffff126h interrupt control register tm0ic11 r/w 47h fffff128h interrupt control register tm5ic0 r/w 47h fffff12ah interrupt control register tm5ic1 r/w 47h fffff12ch interrupt control register csi0ic0 r/w 47h fffff12eh interrupt control register csi0ic1 r/w 47h chapter 3 cpu functions preliminary user?s manual u17702ej1v0ud 65 (3/13) operable bit unit address function register name symbol r/w 1 8 16 after reset fffff130h interrupt control register sreic0 r/w 47h fffff132h interrupt control register sric0 r/w 47h fffff134h interrupt control register stic0 r/w 47h fffff136h interrupt control register sreic1 r/w 47h fffff138h interrupt control register sric1 r/w 47h fffff13ah interrupt control register stic1 r/w 47h fffff13ch interrupt control register tmhic0 r/w 47h fffff13eh interrupt control register tmhic1 r/w 47h fffff140h interrupt control register csiaic0 r/w 47h fffff142h interrupt control register iicic0 r/w 47h fffff144h interrupt control register adic r/w 47h fffff146h interrupt control register kric r/w 47h fffff148h interrupt control register wtiic r/w 47h fffff14ah interrupt control register wtic r/w 47h fffff14ch interrupt control register brgic r/w 47h fffff14eh interrupt control register tm0ic20 r/w 47h fffff150h interrupt control register tm0ic21 r/w 47h fffff152h interrupt control register tm0ic30 r/w 47h fffff154h interrupt control register tm0ic31 r/w 47h fffff156h interrupt control register csiaic1 r/w 47h fffff158h interrupt control register tm0ic40 r/w 47h fffff15ah interrupt control register tm0ic41 r/w 47h fffff15ch interrupt control register tm0ic50 r/w 47h fffff15eh interrupt control register tm0ic51 r/w 47h fffff160h interrupt control register csi0ic2 r/w 47h fffff162h interrupt control register sreic2 r/w 47h fffff164h interrupt control register sric2 r/w 47h fffff166h interrupt control register stic2 r/w 47h fffff168h interrupt control register iicic1 r/w 47h fffff172h interrupt control register pic7 r/w 47h fffff174h interrupt control register tp0ovic r/w 47h fffff176h interrupt control register tp0ccic0 r/w 47h fffff178h interrupt control register tp0ccic1 r/w 47h fffff17ah interrupt control register dmaic0 r/w 47h fffff17ch interrupt control register dmaic1 r/w 47h fffff17eh interrupt control register dmaic2 r/w 47h fffff180h interrupt control register dmaic3 r/w 47h fffff1fah in-service priority register ispr r 00h fffff1fch command register prcmd w undefined fffff1feh power save control register psc r/w 00h chapter 3 cpu functions preliminary user?s manual u17702ej1v0ud 66 (4/13) operable bit unit address function register name symbol r/w 1 8 16 after reset fffff200h a/d converter mode register adm r/w 00h fffff201h analog input channel specification register ads r/w 00h fffff202h power fail comparison mode register pfm r/w 00h fffff203h power fail comparison threshold register pft r/w 00h fffff204h a/d conversion result register adcr r undefined fffff205h a/d conversion result register h adcrh r undefined fffff280h d/a conversion value setting register 0 dacs0 r/w 00h fffff282h d/a conversion value setting register 1 dacs1 r/w 00h fffff284h d/a converter mode register dam r/w 00h fffff300h key return mode register krm r/w 00h fffff30ah selector operation control register 1 selcnt1 r/w 00h fffff318h digital noise elimination control register nfc r/w 00h fffff400h port 0 register p0 r/w 00h note fffff402h port 1 register p1 r/w 00h note fffff406h port 3 register p3 r/w 0000h note fffff406h port 3 register l p3l r/w 00h note fffff407h port 3 register h p3h r/w 00h note fffff408h port 4 register p4 r/w 00h note fffff40ah port 5 register p5 r/w 00h note fffff40ch port 6 register p6 r/w 0000h note fffff40ch port 6 register l p6l r/w 00h note fffff40dh port 6 register h p6h r/w 00h note fffff40eh port 7 register p7 r undefined fffff40eh port 7 register l p7l r undefined fffff40fh port 7 register h p7h r undefined fffff410h port 8 register p8 r/w 00h note fffff412h port 9 register p9 r/w 0000h note fffff412h port 9 register l p9l r/w 00h note fffff413h port 9 register h p9h r/w 00h note fffff420h port 0 mode register pm0 r/w ffh fffff422h port 1 mode register pm1 r/w ffh fffff426h port 3 mode register pm3 r/w ffffh fffff426h port 3 mode register l pm3l r/w ffh fffff427h port 3 mode register h pm3h r/w ffh fffff428h port 4 mode register pm4 r/w ffh fffff42ah port 5 mode register pm5 r/w ffh fffff42ch port 6 mode register pm6 r/w ffffh fffff42ch port 6 mode register l pm6l r/w ffh fffff42dh port 6 mode register h pm6h r/w ffh fffff430h port 8 mode register pm8 r/w ffh note the output latch is 00h or 0000h. when input, the pin status is read. chapter 3 cpu functions preliminary user?s manual u17702ej1v0ud 67 (5/13) operable bit unit address function register name symbol r/w 1 8 16 after reset fffff432h port 9 mode register pm9 r/w ffffh fffff432h port 9 mode register l pm9l r/w ffh fffff433h port 9 mode register h pm9h r/w ffh fffff440h port 0 mode control register pmc0 r/w 00h fffff446h port 3 mode control register pmc3 r/w 0000h fffff446h port 3 mode control register l pmc3l r/w 00h fffff447h port 3 mode control register h pmc3h r/w 00h fffff448h port 4 mode control register pmc4 r/w 00h fffff44ah port 5 mode control register pmc5 r/w 00h fffff44ch port 6 mode control register pmc6 r/w 0000h fffff44ch port 6 mode control register l pmc6l r/w 00h fffff44dh port 6 mode control register h pmc6h r/w 00h fffff450h port 8 mode control register pmc8 r/w 00h fffff452h port 9 mode control register pmc9 r/w 0000h fffff452h port 9 mode control register l pmc9l r/w 00h fffff453h port 9 mode control register h pmc9h r/w 00h fffff466h port 3 function control register pfc3 r/w 00h fffff468h port 4 function control register pfc4 r/w 00h fffff46ah port 5 function control register pfc5 r/w 00h fffff46dh port 6 function control register pfc6h r/w 00h fffff470h port 8 function control register pfc8 r/w 00h fffff472h port 9 function control register pfc9 r/w 0000h fffff472h port 9 function control register l pfc9l r/w 00h fffff473h port 9 function control register h pfc9h r/w 00h fffff484h data wait control register 0 dwc0 r/w 7777h fffff488h address wait control register awc r/w ffffh fffff48ah bus cycle control register bcc r/w aaaah fffff580h 8-bit timer h mode register 0 tmhmd0 r/w 00h fffff581h 8-bit timer h carrier control register 0 tmcyc0 r/w 00h fffff582h 8-bit timer h compare register 00 cmp00 r/w 00h fffff583h 8-bit timer h compare register 01 cmp01 r/w 00h fffff590h 8-bit timer h mode register 1 tmhmd1 r/w 00h fffff591h 8-bit timer h carrier control register 1 tmcyc1 r/w 00h fffff592h 8-bit timer h compare register 10 cmp10 r/w 00h fffff593h 8-bit timer h compare register 11 cmp11 r/w 00h fffff5a0h tmp0 control register 0 tp0ctl0 r/w 00h fffff5a1h tmp0 control register 1 tp0ctl1 r/w 00h fffff5a2h tmp0 i/o control register 0 tp0ioc0 r/w 00h fffff5a3h tmp0 i/o control register 1 tp0ioc1 r/w 00h fffff5a4h tmp0 i/o control register 2 tp0ioc2 r/w 00h fffff5a5h tmp0 option register 0 tp0opt0 r/w 00h fffff5a6h tmp0 capture/compare register 0 tp0ccr0 r/w 0000h chapter 3 cpu functions preliminary user?s manual u17702ej1v0ud 68 (6/13) operable bit unit address function register name symbol r/w 1 8 16 after reset fffff5a8h tmp0 capture/compare register 1 tp0ccr1 r/w 0000h fffff5aah tmp0 counter read buffer register tp0cnt r 0000h fffff5c0h 16-bit timer counter 5 tm5 r 0000h fffff5c0h 8-bit timer counter 50 tm50 r 00h fffff5c1h 8-bit timer counter 51 tm51 r 00h fffff5c2h 16-bit timer compare register 5 cr5 r/w 0000h fffff5c2h 8-bit timer compare register 50 cr50 r/w 00h fffff5c3h 8-bit timer compare register 51 cr51 r/w 00h fffff5c4h timer clock selection register 5 tcl5 r/w 0000h fffff5c4h timer clock selection register 50 tcl50 r/w 00h fffff5c5h timer clock selection register 51 tcl51 r/w 00h fffff5c6h 16-bit timer mode control register 5 tmc5 r/w 0000h fffff5c6h 8-bit timer mode control register 50 tmc50 r/w 00h fffff5c7h 8-bit timer mode control register 51 tmc51 r/w 00h fffff600h 16-bit timer counter 00 tm00 r 0000h fffff602h 16-bit timer capture/compare register 000 cr000 r/w 0000h fffff604h 16-bit timer capture/compare register 001 cr001 r/w 0000h fffff606h 16-bit timer mode control register 00 tmc00 r/w 00h fffff607h prescaler mode register 00 prm00 r/w 00h fffff608h capture/compare control register 00 crc00 r/w 00h fffff609h 16-bit timer output control register 00 toc00 r/w 00h fffff610h 16-bit timer counter 01 tm01 r 0000h fffff612h 16-bit timer capture/compare register 010 cr010 r/w 0000h fffff614h 16-bit timer capture/compare register 011 cr011 r/w 0000h fffff616h 16-bit timer mode control register 01 tmc01 r/w 00h fffff617h prescaler mode register 01 prm01 r/w 00h fffff618h capture/compare control register 01 crc01 r/w 00h fffff619h 16-bit timer output control register 01 toc01 r/w 00h fffff620h 16-bit timer counter 02 tm02 r 0000h fffff622h 16-bit timer capture/compare register 020 cr020 r/w 0000h fffff624h 16-bit timer capture/compare register 021 cr021 r/w 0000h fffff626h 16-bit timer mode control register 02 tmc02 r/w 00h fffff627h prescaler mode register 02 prm02 r/w 00h fffff628h capture/compare control register 02 crc02 r/w 00h fffff629h 16-bit timer output control register 02 toc02 r/w 00h fffff630h 16-bit timer counter 03 tm03 r 0000h fffff632h 16-bit timer capture/compare register 030 cr030 r/w 0000h fffff634h 16-bit timer capture/compare register 031 cr031 r/w 0000h fffff636h 16-bit timer mode control register 03 tmc03 r/w 00h fffff637h prescaler mode register 03 prm03 r/w 00h fffff638h capture/compare control register 03 crc03 r/w 00h fffff639h 16-bit timer output control register 03 toc03 r/w 00h chapter 3 cpu functions preliminary user?s manual u17702ej1v0ud 69 (7/13) operable bit unit address function register name symbol r/w 1 8 16 after reset fffff640h 16-bit timer counter 04 tm04 r 0000h fffff642h 16-bit timer capture/compare register 040 cr040 r/w 0000h fffff644h 16-bit timer capture/compare register 041 cr041 r/w 0000h fffff646h 16-bit timer mode control register 04 tmc04 r/w 00h fffff647h prescaler mode register 04 prm04 r/w 00h fffff648h capture/compare control register 04 crc04 r/w 00h fffff649h 16-bit timer output control register 04 toc04 r/w 00h fffff650h 16-bit timer counter 05 tm05 r 0000h fffff652h 16-bit timer capture/compare register 050 cr050 r/w 0000h fffff654h 16-bit timer capture/compare register 051 cr051 r/w 0000h fffff656h 16-bit timer mode control register 05 tmc05 r/w 00h fffff657h prescaler mode register 05 prm05 r/w 00h fffff658h capture/compare control register 05 crc05 r/w 00h fffff659h 16-bit timer output control register 05 toc05 r/w 00h fffff680h watch timer operation mode register wtm r/w 00h fffff6c0h oscillation stabilization time selection register osts r/w 01h fffff6c1h watchdog timer clock sele ction register wdcs r/w 00h fffff6c2h watchdog timer mode register 1 wdtm1 r/w 00h fffff6d0h watchdog timer mode register 2 wdtm2 r/w 67h fffff6d1h watchdog timer enable register wdte r/w 9ah fffff6e0h real-time output buffer register l0 rtbl0 r/w 00h fffff6e2h real-time output buffer register h0 rtbh0 r/w 00h fffff6e4h real-time output port mode register 0 rtpm0 r/w 00h fffff6e5h real-time output port control register 0 rtpc0 r/w 00h fffff6f0h real-time output bu ffer register l1 rtbl1 r/w 00h fffff6f2h real-time output bu ffer register h1 rtbh1 r/w 00h fffff6f4h real-time output port mode register 1 rtpm1 r/w 00h fffff6f5h real-time output port control register 1 rtpc1 r/w 00h fffff706h port 3 function control expansion register pfce3 r/w 00h fffff802h system status register sys r/w 00h fffff806h pll control register pllctl r/w 01h fffff810h dma trigger factor register 0 dtfr0 r/w 00h fffff812h dma trigger factor register 1 dtfr1 r/w 00h fffff814h dma trigger factor register 2 dtfr2 r/w 00h fffff816h dma trigger factor register 3 dtfr3 r/w 00h fffff820h power save mode register psmr r/w 00h fffff828h processor clock control register pcc r/w 03h fffff8b0h interval timer brg mode register prsm r/w 00h fffff8b1h interval timer brg compare register prscm r/w 00h fffff9fch on-chip debug mode register ocdm r/w 01h chapter 3 cpu functions preliminary user?s manual u17702ej1v0ud 70 (8/13) operable bit unit address function register name symbol r/w 1 8 16 after reset fffffa00h asynchronous serial interface mode register 0 asim0 r/w 01h fffffa02h receive buffer register 0 rxb0 r ffh fffffa03h asynchronous serial interfac e status register 0 asis0 r 00h fffffa04h transmit buffer register 0 txb0 r/w ffh fffffa05h asynchronous serial interface transmit status register 0 asif0 r 00h fffffa06h clock select register 0 cksr0 r/w 00h fffffa07h baud rate generator control register 0 brgc0 r/w ffh fffffa10h asynchronous serial interface mode register 1 asim1 r/w 01h fffffa12h receive buffer register 1 rxb1 r ffh fffffa13h asynchronous serial interf ace status register 1 asis1 r 00h fffffa14h transmit buffer register 1 txb1 r/w ffh fffffa15h asynchronous serial interface transmit status register 1 asif1 r 00h fffffa16h clock select register 1 cksr1 r/w 00h fffffa17h baud rate generator control register 1 brgc1 r/w ffh fffffa20h asynchronous serial interface mode register 2 asim2 r/w 01h fffffa22h receive buffer register 2 rxb2 r ffh fffffa23h asynchronous serial interf ace status register 2 asis2 r 00h fffffa24h transmit buffer register 2 txb2 r/w ffh fffffa25h asynchronous serial interface transmit status register 2 asif2 r 00h fffffa26h clock select register 2 cksr2 r/w 00h fffffa27h baud rate generator control register 2 brgc2 r/w ffh fffffb00h tip00 noise elimination control register p0nfc r/w 00h fffffb04h tip01 noise elimination control register p1nfc r/w 00h fffffc00h external interrupt falling edge specification register 0 intf0 r/w 00h fffffc06h external interrupt falling edge specification register 3 intf3 r/w 00h fffffc13h external interrupt falling edge specification register 9h intf9h r/w 00h fffffc20h external interrupt rising edge specification register 0 intr0 r/w 00h fffffc26h external interrupt rising edge specification register 3 intr3 r/w 00h fffffc33h external interrupt rising edge specification register 9h intr9h r/w 00h fffffc40h pull-up resistor option register 0 pu0 r/w 00h fffffc42h pull-up resistor option register 1 pu1 r/w 00h fffffc46h pull-up resistor option register 3 pu3 r/w 00h fffffc48h pull-up resistor option register 4 pu4 r/w 00h fffffc4ah pull-up resistor option register 5 pu5 r/w 00h fffffc4ch pull-up resistor option register 6 pu6 r/w 0000h fffffc4ch pull-up resistor option register 6l pu6l r/w 00h fffffc4dh pull-up resistor option register 6h pu6h r/w 00h fffffc50h pull-up resistor option register 8 pu8 r/w 00h fffffc52h pull-up resistor option register 9 pu9 r/w 0000h fffffc52h pull-up resistor option register 9l pu9l r/w 00h fffffc53h pull-up resistor option register 9h pu9h r/w 00h chapter 3 cpu functions preliminary user?s manual u17702ej1v0ud 71 (9/13) operable bit unit address function register name symbol r/w 1 8 16 after reset fffffc67h port 3 function register h pf3h r/w 00h fffffc68h port 4 function register pf4 r/w 00h fffffc6ah port 5 function register pf5 r/w 00h fffffc6ch port 6 function register pf6 r/w 0000h fffffc6ch port 6 function register l pf6l r/w 00h fffffc6dh port 6 function register h pf6h r/w 00h fffffc70h port 8 function register pf8 r/w 00h fffffc73h port 9 function register h pf9h r/w 00h fffffd00h clocked serial inte rface mode register 00 csim00 r/w 00h fffffd01h clocked serial interface clock selection register 0 csic0 r/w 00h fffffd02h clocked serial interfac e receive buffer register 0 sirb0 r 0000h fffffd02h clocked serial interfac e receive buffer register 0l sirb0l r 00h fffffd04h clocked serial interface transmit buffer register 0 sotb0 r/w 0000h fffffd04h clocked serial interfac e transmit buffer register 0l sotb0l r/w 00h fffffd06h clocked serial interface read -only receive buffer register 0 sirbe0 r 0000h fffffd06h clocked serial interface read -only receive buffer register 0l sirbe0l r 00h fffffd08h clocked serial interface init ial transmit buffer register 0 sotbf0 r/w 0000h fffffd08h clocked serial interface in itial transmit buffer register 0l sotbf0l r/w 00h fffffd0ah serial i/o shift register 0 sio00 r/w 00h fffffd0ah serial i/o shift register 0l sio00l r/w 0000h fffffd10h clocked serial inte rface mode register 01 csim01 r/w 00h fffffd11h clocked serial interface clock selection register 1 csic1 r/w 00h fffffd12h clocked serial interfac e receive buffer register 1 sirb1 r 0000h fffffd12h clocked serial interfac e receive buffer register 1l sirb1l r 00h fffffd14h clocked serial interface transmit buffer register 1 sotb1 r/w 0000h fffffd14h clocked serial interfac e transmit buffer register 1l sotb1l r/w 00h fffffd16h clocked serial interface read -only receive buffer register 1 sirbe1 r 0000h fffffd16h clocked serial interface read -only receive buffer register 1l sirbe1l r 00h fffffd18h clocked serial interface init ial transmit buffer register 1 sotbf1 r/w 0000h fffffd18h clocked serial interface in itial transmit buffer register 1l sotbf1l r/w 00h fffffd1ah serial i/o shift register 1 sio01 r/w 00h fffffd1ah serial i/o shift register 1l sio01l r/w 0000h fffffd20h clocked serial inte rface mode register 02 csim02 r/w 00h fffffd21h clocked serial interface clock selection register 2 csic2 r/w 00h fffffd22h clocked serial interfac e receive buffer register 2 sirb2 r 0000h fffffd22h clocked serial interfac e receive buffer register 2l sirb2l r 00h fffffd24h clocked serial interface transmit buffer register 2 sotb2 r/w 0000h fffffd24h clocked serial interfac e transmit buffer register 2l sotb2l r/w 00h fffffd26h clocked serial interface read -only receive buffer register 2 sirbe2 r 0000h fffffd26h clocked serial interface read -only receive buffer register 2l sirbe2l r 00h chapter 3 cpu functions preliminary user?s manual u17702ej1v0ud 72 (10/13) operable bit unit address function register name symbol r/w 1 8 16 after reset fffffd28h clocked serial interface init ial transmit buffer register 2 sotbf2 r/w 0000h fffffd28h clocked serial interface in itial transmit buffer register 2l sotbf2l r/w 00h fffffd2ah serial i/o shift register 2 sio02 r/w 00h fffffd2ah serial i/o shift register 2l sio02l r/w 0000h fffffd40h serial operation mode specification register 0 csima0 r/w 00h fffffd41h serial status register 0 csis0 r/w 00h fffffd42h serial trigger register 0 csit0 r/w 00h fffffd43h divisor selection register 0 brgca0 r/w 03h fffffd44h automatic data transfer address point specification register 0 adtp0 r/w 00h fffffd45h automatic data transfer interval specification register 0 adti0 r/w 00h fffffd46h serial i/o shift register a0 sioa0 r/w 00h fffffd47h automatic data transfer address count register 0 adtc0 r 00h fffffd50h serial operation mode specification register 1 csima1 r/w 00h fffffd51h serial status register 1 csis1 r/w 00h fffffd52h serial trigger register 1 csit1 r/w 00h fffffd53h divisor selection register 1 brgca1 r/w 03h fffffd54h automatic data transfer address point specification register 1 adtp1 r/w 00h fffffd55h automatic data transfer interval specification register 1 adti1 r/w 00h fffffd56h serial i/o shift register a1 sioa1 r/w 00h fffffd57h automatic data transfer address count register 1 adtc1 r 00h fffffd80h iic shift register 0 iic0 r/w 00h fffffd82h iic control register 0 iicc0 r/w 00h fffffd83h slave address register 0 sva0 r/w 00h fffffd84h iic clock selection register 0 iiccl0 r/w 00h fffffd85h iic function expansion register 0 iicx0 r/w 00h fffffd86h iic status register 0 iics0 r 00h fffffd8ah iic flag register 0 iicf0 r/w 00h fffffd90h iic shift register 1 iic1 r/w 00h fffffd92h iic control register 1 iicc1 r/w 00h fffffd93h slave address register 1 sva1 r/w 00h fffffd94h iic clock selection register 1 iiccl1 r/w 00h fffffd95h iic function expansion register 1 iicx1 r/w 00h fffffd96h iic status register 1 iics1 r 00h fffffd9ah iic flag register 1 iicf1 r/w 00h fffffe00h csia0 buffer ram 0 csia0b0 r/w undefined fffffe00h csia0 buffer ram 0l csia0b0l r/w undefined fffffe01h csia0 buffer ram 0h csia0b0h r/w undefined fffffe02h csia0 buffer ram 1 csia0b1 r/w undefined fffffe02h csia0 buffer ram 1l csia0b1l r/w undefined fffffe03h csia0 buffer ram 1h csia0b1h r/w undefined chapter 3 cpu functions preliminary user?s manual u17702ej1v0ud 73 (11/13) operable bit unit address function register name symbol r/w 1 8 16 after reset fffffe04h csia0 buffer ram 2 csia0b2 r/w undefined fffffe04h csia0 buffer ram 2l csia0b2l r/w undefined fffffe05h csia0 buffer ram 2h csia0b2h r/w undefined fffffe06h csia0 buffer ram 3 csia0b3 r/w undefined fffffe06h csia0 buffer ram 3l csia0b3l r/w undefined fffffe07h csia0 buffer ram 3h csia0b3h r/w undefined fffffe08h csia0 buffer ram 4 csia0b4 r/w undefined fffffe08h csia0 buffer ram 4l csia0b4l r/w undefined fffffe09h csia0 buffer ram 4h csia0b4h r/w undefined fffffe0ah csia0 buffer ram 5 csia0b5 r/w undefined fffffe0ah csia0 buffer ram 5l csia0b5l r/w undefined fffffe0bh csia0 buffer ram 5h csia0b5h r/w undefined fffffe0ch csia0 buffer ram 6 csia0b6 r/w undefined fffffe0ch csia0 buffer ram 6l csia0b6l r/w undefined fffffe0dh csia0 buffer ram 6h csia0b6h r/w undefined fffffe0eh csia0 buffer ram 7 csia0b7 r/w undefined fffffe0eh csia0 buffer ram 7l csia0b7l r/w undefined fffffe0fh csia0 buffer ram 7h csia0b7h r/w undefined fffffe10h csia0 buffer ram 8 csia0b8 r/w undefined fffffe10h csia0 buffer ram 8l csia0b8l r/w undefined fffffe11h csia0 buffer ram 8h csia0b8h r/w undefined fffffe12h csia0 buffer ram 9 csia0b9 r/w undefined fffffe12h csia0 buffer ram 9l csia0b9l r/w undefined fffffe13h csia0 buffer ram 9h csia0b9h r/w undefined fffffe14h csia0 buffer ram a csia0ba r/w undefined fffffe14h csia0 buffer ram al csia0bal r/w undefined fffffe15h csia0 buffer ram ah csia0bah r/w undefined fffffe16h csia0 buffer ram b csia0bb r/w undefined fffffe16h csia0 buffer ram bl csia0bbl r/w undefined fffffe17h csia0 buffer ram bh csia0bbh r/w undefined fffffe18h csia0 buffer ram c csia0bc r/w undefined fffffe18h csia0 buffer ram cl csia0bcl r/w undefined fffffe19h csia0 buffer ram ch csia0bch r/w undefined fffffe1ah csia0 buffer ram d csia0bd r/w undefined fffffe1ah csia0 buffer ram dl csia0bdl r/w undefined fffffe1bh csia0 buffer ram dh csia0bdh r/w undefined fffffe1ch csia0 buffer ram e csia0be r/w undefined fffffe1ch csia0 buffer ram el csia0bel r/w undefined fffffe1dh csia0 buffer ram eh csia0beh r/w undefined chapter 3 cpu functions preliminary user?s manual u17702ej1v0ud 74 (12/13) operable bit unit address function register name symbol r/w 1 8 16 after reset fffffe1eh csia0 buffer ram f csia0bf r/w undefined fffffe1eh csia0 buffer ram fl csia0bfl r/w undefined fffffe1fh csia0 buffer ram fh csia0bfh r/w undefined fffffe20h csia1 buffer ram 0 csia1b0 r/w undefined fffffe20h csia1 buffer ram 0l csia1b0l r/w undefined fffffe21h csia1 buffer ram 0h csia1b0h r/w undefined fffffe22h csia1 buffer ram 1 csia1b1 r/w undefined fffffe22h csia1 buffer ram 1l csia1b1l r/w undefined fffffe23h csia1 buffer ram 1h csia1b1h r/w undefined fffffe24h csia1 buffer ram 2 csia1b2 r/w undefined fffffe24h csia1 buffer ram 2l csia1b2l r/w undefined fffffe25h csia1 buffer ram 2h csia1b2h r/w undefined fffffe26h csia1 buffer ram 3 csia1b3 r/w undefined fffffe26h csia1 buffer ram 3l csia1b3l r/w undefined fffffe27h csia1 buffer ram 3h csia1b3h r/w undefined fffffe28h csia1 buffer ram 4 csia1b4 r/w undefined fffffe28h csia1 buffer ram 4l csia1b4l r/w undefined fffffe29h csia1 buffer ram 4h csia1b4h r/w undefined fffffe2ah csia1 buffer ram 5 csia1b5 r/w undefined fffffe2ah csia1 buffer ram 5l csia1b5l r/w undefined fffffe2bh csia1 buffer ram 5h csia1b5h r/w undefined fffffe2ch csia1 buffer ram 6 csia1b6 r/w undefined fffffe2ch csia1 buffer ram 6l csia1b6l r/w undefined fffffe2dh csia1 buffer ram 6h csia1b6h r/w undefined fffffe2eh csia1 buffer ram 7 csia1b7 r/w undefined fffffe2eh csia1 buffer ram 7l csia1b7l r/w undefined fffffe2fh csia1 buffer ram 7h csia1b7h r/w undefined fffffe30h csia1 buffer ram 8 csia1b8 r/w undefined fffffe30h csia1 buffer ram 8l csia1b8l r/w undefined fffffe31h csia1 buffer ram 8h csia1b8h r/w undefined fffffe32h csia1 buffer ram 9 csia1b9 r/w undefined fffffe32h csia1 buffer ram 9l csia1b9l r/w undefined fffffe33h csia1 buffer ram 9h csia1b9h r/w undefined fffffe34h csia1 buffer ram a csia1ba r/w undefined fffffe34h csia1 buffer ram al csia1bal r/w undefined fffffe35h csia1 buffer ram ah csia1bah r/w undefined fffffe36h csia1 buffer ram b csia1bb r/w undefined fffffe36h csia1 buffer ram bl csia1bbl r/w undefined fffffe37h csia1 buffer ram bh csia1bbh r/w undefined chapter 3 cpu functions preliminary user?s manual u17702ej1v0ud 75 (13/13) operable bit unit address function register name symbol r/w 1 8 16 after reset fffffe38h csia1 buffer ram c csia1bc r/w undefined fffffe38h csia1 buffer ram cl csia1bcl r/w undefined fffffe39h csia1 buffer ram ch csia1bch r/w undefined fffffe3ah csia1 buffer ram d csia1bd r/w undefined fffffe3ah csia1 buffer ram dl csia1bdl r/w undefined fffffe3bh csia1 buffer ram dh csia1bdh r/w undefined fffffe3ch csia1 buffer ram e csia1be r/w undefined fffffe3ch csia1 buffer ram el csia1bel r/w undefined fffffe3dh csia1 buffer ram eh csia1beh r/w undefined fffffe3eh csia1 buffer ram f csia1bf r/w undefined fffffe3eh csia1 buffer ram fl csia1bfl r/w undefined fffffe3fh csia1 buffer ram fh csia1bfh r/w undefined ffffff44h pull-up resistor option register dl pudl r/w 0000h ffffff44h pull-up resistor option register dll pudll r/w 00h ffffff45h pull-up resistor option register dlh pudlh r/w 00h ffffff46h pull-up resistor option register dh pudh r/w 00h ffffff48h pull-up resistor option register cs pucs r/w 00h ffffff4ah pull-up resistor option register ct puct r/w 00h ffffff4ch pull-up resistor option register cm pucm r/w 00h ffffff4eh pull-up resistor option register cd pucd r/w 00h ffffffbeh external bus interface mode control register eximc r/w 00h chapter 3 cpu functions preliminary user?s manual u17702ej1v0ud 76 3.4.7 special registers special registers are registers that prevent invalid da ta from being written when an inadvertent program loop occurs. the v850es/kj2 has the following four special registers. ? power save control register (psc) ? processor clock control register (pcc) ? watchdog timer mode register (wdtm1) ? on-chip debug mode register (ocdm) moreover, there is also the prcmd r egister, which is a protection register for write operations to the special registers that prevents the application system from unexpectedly stopping due to an inadvertent program loop. write access to the special registers is performed with a specia l sequence and illegal store oper ations are notified to the sys register. (1) setting data to special registers setting data to a special registers is done in the following sequence. <1> prepare the data to be set to the specia l register in a general-purpose register. <2> write the data prepared in st ep <1> to the prcmd register. <3> write the setting data to the special regi ster (using following instructions). ? store instruction (st/sst instruction) ? bit manipulation instruction (set1/clr1/not1 instruction) <4> to <8> insert nop inst ructions (5 instructions) note . [description example] when using psc register (standby mode setting) st.b r11,psmr[r0] ; psmr register setting (idle, stop mode setting) <1> mov 0x02,r10 <2> st.b r10,prcmd[r0] ; prcmd register write <3> st.b r10,psc[r0] ; psc register setting <4> nop note ; dummy instruction <5> nop note ; dummy instruction <6> nop note ; dummy instruction <7> nop note ; dummy instruction <8> nop note ; dummy instruction (next instruction) no special sequence is required to read special registers. note when switching to the idle mode or the stop m ode (psc.stp bit = 1), 5 nop instructions must be inserted immediately after switching is performed. chapter 3 cpu functions preliminary user?s manual u17702ej1v0ud 77 cautions 1. interrupts are not acknowledged for the store instruction for the prcmd register. this is because continuous execution of store instructi ons by the program in steps <2> and <3> above is assumed. if another instruction is placed between step <2> and <3>, the above sequence may not be realized when an interrupt is acknowle dged for that instruction, which may cause malfunction. 2. the data written to the prcmd register is dummy data, but use the same register as the general-purpose register used for setting data to the special register (step <3>) when writing to the prcmd register (step <2>). the same applies to when using a general- purpose register for addressing. (2) command register (prcmd) the prcmd register is an 8-bit register used to prevent data from being written to registers that may have a large influence on the system, possibly causing the application system to unexpectedly stop, when an inadvertent program loop occurs. only the first write operat ion to the special register following the execution of a previously executed writ e operation to the prcmd register, is valid. as a result, register values can be overwritten onl y using a preset sequence, preventing invalid write operations. this register can only be written in 8-bit units (if it is read, an undefined value is returned). 7 reg7 prcmd 6 reg6 5 reg5 4 reg4 3 reg3 2 reg2 1 reg1 0 reg0 after reset: undefined w address: fffff1fch (3) system status register (sys) this register is allocated with status flags showing the operat ing state of the entire system. this register can be read or writt en in 8-bit or 1-bit units. 0 protection error has not occurred protection error has occurred prerr 0 1 detection of protection error sys 0 0 0 0 0 0 prerr after reset: 00h r/w address: fffff802h < > chapter 3 cpu functions preliminary user?s manual u17702ej1v0ud 78 the operation conditions of the prerr flag are described below. (a) set conditions (prerr = 1) (i) when a write operation to the s pecial register takes place without write operation being performed to the prcmd register (when step <3> is performed without performing step <2> as described in 3.4.7 (1) setting data to special registers ). (ii) when a write operation (including bit manipulation instruction) to an on-chip peripheral i/o register other than a special register is performed follo wing write to the prcmd register (when <3> in 3.4.7 (1) setting data to special registers is not a special register). remark regarding the special registers other than the wdtm register (pcc and psc registers), even if on-chip peripheral i/o register read (except bit ma nipulation instruction) (internal ram access, etc.) is performed in between wr ite to the prcmd register and wr ite to a special register, the prerr flag is not set and setting data can be written to the special register. (b) clear conditions (prerr = 0) (i) when 0 is written to the prerr flag (ii) when system reset is performed cautions 1. if 0 is written to the prerr bit of the sys register that is not a special register immediately following write to the prcmd re gister, the prerr bi t becomes 0 (write priority). 2. if data is written to the prcmd register that is not a special register immediately following write to the prcmd regist er, the prerr bit becomes 1. chapter 3 cpu functions preliminary user?s manual u17702ej1v0ud 79 3.4.8 cautions (1) waits on register access be sure to set the following regist er before using the v850es/kj2. ? system wait control register (vswc) after setting the vswc register, set t he other registers as required. when using an external bus, set the vswc register and then set the various pins to the control mode by setting the port-related registers. (a) system wait control register (vswc) the vswc register controls the bus access wait ti me for the on-chip perip heral i/o registers. access to the on-chip peripheral i/o register lasts 3 cl ocks (during no wait), but in the v850es/kj2, waits are required according to the internal system clo ck frequency. set the values shown below to the vswc register according to the internal system clock frequency that is used. this register can be read or written in 8-bit units (address: fffff06eh, after reset: 77h). operation conditions internal system clock frequency (f clk ) vswc register setting number of waits 32 khz f clk < 16.6 mhz 00h 0 (no waits) 4.5 v regc = v dd 5.5 v 16.6 mhz f clk 20 mhz 01h 1 4.0 v regc = v dd < 4.5 v 32 khz f clk 16 mhz 00h 0 (no waits) 32 khz f clk < 8.3 mhz 00h 0 (no waits) regc = 10 f, 4.0 v v dd 5.5 v 8.3 mhz f clk 16 mhz 01h 1 32 khz f clk < 8.3 mhz 00h 0 (no waits) 2.7 v regc = v dd < 4.0 v 8.3 mhz f clk 10 mhz 01h 1 remark f x : main clock oscillation frequency (b) access to special on-chip peripheral i/o register this product has two types of internal system buses. one type is for the cpu bus and the ot her is for the peripheral bus to interface with low-speed peripheral hardware. since the cpu bus clock and peripheral bus clock are asynchronous, if a conflict occurs during access between the cpu and peripheral hardware, illegal data may be passed unexpectedly. therefore, when accessing peripheral hardware that may cause a conf lict, the number of access cycles is changed so that the data is received/passed correctly in the cpu. as a result, the cpu does not shift to the next instruction processing and enters t he wait status. when this wait stat us occurs, the number of execution clocks of the instruction is increased by the number of wait clocks. note this with caution when performing real-time processing. when accessing a special on-chip peripheral i/o regist er, additional waits may be required further to the waits set by the vswc register. the access conditions at that time and the method to calculate the number of waits to be inserted (number of cpu clocks) are shown below. number of waits to be inserted = (2 + m) k (clocks) number of accesses to specific on-chip peripheral i/o register = 3 + m + (2 + m) k (clocks) chapter 3 cpu functions preliminary user?s manual u17702ej1v0ud 80 peripheral function register name access k wdtm1 write 1 to 5 watchdog timer 1 (wdt1) chapter 3 cpu functions preliminary user?s manual u17702ej1v0ud 81 cautions 1. if fetched from the internal rom or internal ram, the number of waits is as shown above. if fetched from the external memory, the number of waits may be decreased below these. the effect of the external memory access cycles varies depending on the wait settings and the like. however, the number of waits shown above is the maximum value, so no higher value is generated. 2. when the cpu operates on the subclock and no clock is input to the x1 pin, do not access a register in which a wait occurs. if a wait occurs, it can only be released by a reset. remarks 1. in the calculation for the number of waits: f cpu : cpu clock frequency f xx : main clock frequency m: set value of bits 2 to 0 of the vswc register when the vswc register = 00h: m = 0 when the vswc register = 01h: m = 1 2. n = 0, 1 chapter 3 cpu functions preliminary user?s manual u17702ej1v0ud 82 (2) restriction on conflict between sld instruction and interrupt request (a) description if a conflict occurs between the dec ode operation of an instruction in <2> immediately before the sld instruction following an instruction in <1> and an interrupt request before the instruction in <1> is complete, the execution result of t he instruction in <1> may not be stored in a register. instruction <1> ? ld instruction: ld.b, ld.h, ld.w, ld.bu, ld.hu ? sld instruction: sld.b, sld.h, sld.w, sld.bu, sld.hu ? multiplication instruction: mul, mulh, mulhi, mulu instruction <2> mov reg1, reg2 satadd reg1, reg2 and reg1, reg2 add reg1, reg2 mulh reg1, reg2 not reg1, reg2 satadd imm5, reg2 tst reg1, reg2 add imm5, reg2 shr imm5, reg2 satsubr reg1, reg2 or reg1, reg2 subr reg1, reg2 cmp reg1, reg2 sar imm5, reg2 satsub reg1, reg2 xor reg1, reg2 sub reg1, reg2 cmp imm5, reg2 shl imm5, reg2 preliminary user?s manual u17702ej1v0ud 83 chapter 4 port functions 4.1 features { input-only ports: 16 pins { i/o ports: 112 pins ? fixed to n-ch open-drain output: 6 (medium: 4) ? switchable to n-ch open-drain output: 12 { input/output can be specified in 1-bit units 4.2 basic port configuration the v850es/kj2 incorporates a total of 128 i/o port pins cons isting of ports 0, 1, 3 to 9, cd, cm, cs, ct, dh, and dl (including 16 input-only port pins). the port configuration is shown below. p00 p06 port 0 p90 p915 port 9 pcd0 pcd3 port cd pcm0 pcm5 port cm pcs0 pcs7 port cs pct0 pct7 port ct pdh0 pdh7 port dh pdl0 pdl15 port dl p30 p39 port 3 p40 p42 port 4 p50 p55 port 5 p60 p615 port 6 p70 p715 port 7 p80 p81 port 8 p10 p11 port 1 table 4-1. pin i/o buffer power supplies of v850es/kj2 power supply corresponding pins av ref0 port 7 av ref1 port 1 bv dd ports cd, cm, cs, ct, dh, dl ev dd reset, ports 0, 3 to 6, 8, 9 chapter 4 port functions preliminary user?s manual u17702ej1v0ud 84 4.3 port configuration table 4-2. port configuration item configuration control registers port n register (pn: n = 0, 1, 3 to 9, cd, cm, cs, ct, dl, dh) port n mode register (pmn: n = 0, 1, 3 to 6, 8, 9, cd, cm, cs, ct, dl, dh) port n mode control register (pmcn: n = 0, 3 to 6, 8, 9, cm, cs, ct, dl, dh) port n function control register (pfcn: n = 3, 5, 6, 8, 9) port n function register (pfn: n = 3 to 6, 8, 9) port 3 function control expansion register (pfce3) pull-up resistor option register (pun: n = 0, 1, 3 to 6, 8, 9, cd, cm, cs, ct, dl, dh) ports input only: 16 i/o: 112 pull-up resistors software control: 106 (1) port n register (pn) data i/o with external devices is performed by writing to and reading from the pn regist er. the pn register is configured of a port latch that re tains the output data and a circ uit that reads the pin status. each bit of the pn register corresponds to one pin of port n and can be read or written in 1-bit units. pn7 0 is output 1 is output pnm 0 1 control of output data (in output mode) pn6 pn5 pn4 pn3 pn2 pn1 pn0 0 1 2 3 7 5 6 7 pn after reset: 00h note (output latch) r/w note input-only port pins are undefined. writing to and reading from the pn register are executed as follows depending on the setting of each register. chapter 4 port functions preliminary user?s manual u17702ej1v0ud 85 table 4-3. reading to/writing from pn register setting of pmcn register setting of pmn register wr iting to pn register reading from pn register output mode (pmnm bit = 0) write to the output latch note . the contents of the output latch are output from the pin. the value of the output latch is read. port mode (pmcnm bit = 0) input mode (pmnm bit = 1) write to the output latch note . the status of the pin is not affected. the pin status is read. output mode (pmnm bit = 0) write to the output latch note . the status of the pin is not affected. the pin operates as an alternate-function pin. ? when alternate function is output the output status of the alternate function is read. ? when alternate function is input the output latch value is read. alternate-function mode (pmcnm bit = 1) input mode (pmnm bit = 1) write to the output latch note . the status of the pin is not affected. the pin operates as an alternate-function pin. the pin status is read. note the value written to the output latch is retained until a new value is written to the output latch. (2) port n mode register (pmn) pmn specifies the input m ode/output mode of the port. each bit of the pmn register corresponds to one pin of port n and can be specified in 1-bit units. pmn7 output mode input mode pmnm 0 1 control of i/o mode pmn6 pmn5 pmn4 pmn3 pmn2 pmn1 pmn0 pmn after reset: ffh r/w chapter 4 port functions preliminary user?s manual u17702ej1v0ud 86 (3) port n mode control register (pmcn) pmcn specifies the port mode/alternate function. each bit of the pmcn register corresponds to one pin of port n and can be specified in 1-bit units. port mode alternate function mode pmcnm 0 1 specification of operation mode pmcn7 pmcn6 pmcn5 pmcn4 pmcn3 pmcn2 pmcn1 pmcn0 pmcn after reset: 00h r/w (4) port n function control register (pfcn) pfcn is a register that specifies the alternate function to be us ed when one pin has two or more alternate functions. each bit of the pfcn register corresponds to one pin of port n and can be specified in 1-bit units. pfcn7 pfcn6 pfcn5 pfcn4 pfcn3 pfcn2 pfcn1 pfcn0 pfcn after reset: 00h r/w alternate function 1 alternate function 2 pfcnm 0 1 specification of alternate function chapter 4 port functions preliminary user?s manual u17702ej1v0ud 87 (5) port n function control expansion register (pfcen) pfcen is a register that specifies t he alternate function to be used when one pin has three or more alternate functions. each bit of the pfcen register corresponds to one pin of port n and can be specified in 1-bit units. pfcn7 pfcn6 pfcn5 pfcn4 pfcn3 pfcn2 pfcn1 pfcn0 pfcen7 pfcen6 pfcen5 pfcen4 pfcen3 pfcen2 pfcen1 pfcen0 after reset: 00h r/w pfcen pfcn alternate function 1 alternate function 2 alternate function 3 alternate function 4 pfcenm 0 0 1 1 specification of alternate function pfcnm 0 1 0 1 (6) port n function register (pfn) pfn is a register that specifies normal output/n-ch open-drain output. each bit of the pfn register corresponds to one pin of port n and can be specified in 1-bit units. pfn7 pfn6 pfn5 pfn4 pfn3 pfn2 pfn1 pfn0 normal output (cmos output) n-ch open-drain output pfnm note 0 1 control of normal output/n-ch open-drain output pfn after reset: 00h r/w note the pfnm bit is valid only when the pmn.pmnm bit is 0 (output mode) regardl ess of the setting of the pmcn register. when the pmnm bit is 1 (input mode) , the set value in the pfn register is invalid. example <1> when the value of t he pfn register is valid pfnm bit = 1 ? n-ch open-drain output is specified. pmnm bit = 0 ? output mode is specified. pmcnm bit = 0 or 1 <2> when the value of the pfn register is invalid pfnm bit = 0 ? n-ch open-drain output is specified. pmnm bit = 1 ? input mode is specified. pmcnm bit = 0 or 1 chapter 4 port functions preliminary user?s manual u17702ej1v0ud 88 (7) pull-up resistor option register (pun) pun is a register that specifies the c onnection of an on-chip pull-up resistor. each bit of the pun register corresponds to one pin of port n and can be specified in 1-bit units. pun7 pun6 pun5 pun4 pun3 pun2 pun1 pun0 pun after reset: 00h r/w not connected connected punm 0 1 control of on-chip pull-up resistor connection chapter 4 port functions preliminary user?s manual u17702ej1v0ud 89 (8) port settings set the ports as follows. figure 4-1. register settings and pin functions pmcn register output mode input mode pmn register ?0? ?1? ?0? ?1? ?0? ?1? (a) (b) (c) (d) alternate function (when two alternate functions are available) port mode alternate function 1 alternate function 2 pfcn register alternate function (when three or more alternate functions are available) alternate function 1 alternate function 2 alternate function 3 alternate function 4 pfcn register pfcen register pfcenm 0 1 0 1 0 0 1 1 (a) (b) (c) (d) pfcnm remark switch to the alternate functi on using the following procedure. <1> set the pfcn and pfcen registers. <2> set the pmcn register. <3> set the intrn or intfn register (t o specify an external interrupt pin). if the pmcn register is set first, an unintende d function may be set while the pfcn and pfcen registers are being set. chapter 4 port functions preliminary user?s manual u17702ej1v0ud 90 4.3.1 port 0 port 0 is a 7-bit i/o port for which i/o se ttings can be controlled in 1-bit units. port 0 includes the following alternate functions. table 4-4. alternate-function pins of port 0 pin no. pin name alternate function i/o pull note 1 remark block type 6 p00 note 2 toh0 output d0-u 7 p01 toh1 output ? d0-u 17 p02 nmi input d1-suil 18 p03 intp0 input d1-suil 19 p04 intp1 input d1-suil p05 notes 2, 3 intp2 input d1-suil 20 p05 notes 3, 4 intp2/drst note 4 input analog noise elimination od11-suil 21 p06 intp3 input yes analog/digital noise elimination d1-suil notes 1. software pull-up function 2. only in the pd70f3733 3. in the v850es/kj2, care must be exercised in processing the p05 pin when reset is released. for details, see 4.6.3 cautions on p05 pin . 4. only in the pd70f3734 caution p02 to p06 have hysteresis characteristics when the alternate f unction is input, but not in the port mode. chapter 4 port functions preliminary user?s manual u17702ej1v0ud 91 (1) port 0 register (p0) 0 0 is output 1 is output p0n 0 1 control of output data (in output mode) (n = 0 to 6) p0 p06 p05 note p04 p03 p02 p01 p00 after reset: 00h (output latch) r/w address: fffff400h note in the v850es/kj2, care must be exercised in processing the p05 pin when reset is released. for details, refer to 4.6.3 cautions on p05 pin . (2) port 0 mode register (pm0) 1 output mode input mode pm0n 0 1 control of i/o mode (n = 0 to 6) pm0 pm06 pm05 note pm04 pm03 pm02 pm01 pm00 after reset: ffh r/w address: fffff420h note in the v850es/kj2, care must be exercised in processing the p05 pin when reset is released. for details, refer to 4.6.3 cautions on p05 pin . chapter 4 port functions preliminary user?s manual u17702ej1v0ud 92 (3) port 0 mode control register (pmc0) 0 pmc0 pmc06 pmc05 note pmc04 pmc03 pmc02 pmc01 pmc00 i/o port intp3 input pmc06 0 1 specification of p06 pin operation mode i/o port intp2 input pmc05 0 1 specification of p05 pin operation mode i/o port intp1 input pmc04 0 1 specification of p04 pin operation mode i/o port intp0 input pmc03 0 1 specification of p03 pin operation mode i/o port nmi input pmc02 0 1 specification of p02 pin operation mode i/o port toh1 output pmc01 0 1 specification of p01 pin operation mode i/o port toh0 output pmc00 0 1 specification of p00 pin operation mode after reset: 00h r/w address: fffff440h note in the v850es/kj2, care must be exercised in processing the p05 pin when reset is released. for details, refer to 4.6.3 cautions on p05 pin . (4) pull-up resistor option register 0 (pu0) 0 not connected connected pu0n 0 1 control of on-chip pull-up resistor connection (n = 0 to 6) pu0 pu06 pu05 note pu04 pu03 pu02 pu01 pu00 after reset: 00h r/w address: fffffc40h note in the v850es/kj2, care must be exercised in processing the p05 pin when reset is released. for details, refer to 4.6.3 cautions on p05 pin . this is valid only when the ocdm.ocdm bit = 0. chapter 4 port functions preliminary user?s manual u17702ej1v0ud 93 4.3.2 port 1 port 1 is a 2-bit i/o port for which i/o se ttings can be controlled in 1-bit units. port 1 includes the following alternate functions. table 4-5. alternate-function pins of port 1 pin no. pin name alternate function i/o pull note remark block type 3 p10 ano0 output c-ua 4 p11 ano1 output yes ? c-ua note software pull-up function (1) port 1 register (p1) 0 0 is output 1 is output p1n 0 1 control of output data (in output mode) (n = 0, 1) p1 0 0 0 0 0 p11 p10 after reset: 00h (output latch) r/w address: fffff402h (2) port 1 mode register (pm1) caution when used as the ano0 and ano 1 pins, set pm1 = ffh all together. 1 output mode input mode pm1n 0 1 control of i/o mode (n = 0, 1) pm1 1 1 1 1 1 pm11 pm10 after reset: ffh r/w address: fffff422h chapter 4 port functions preliminary user?s manual u17702ej1v0ud 94 (3) pull-up resistor option register 1 (pu1) 0 not connected connected pu1n 0 1 control of on-chip pull-up resistor connection (n = 0, 1) pu1 0 0 0 0 0 pu11 pu10 after reset: 00h r/w address: fffffc42h chapter 4 port functions preliminary user?s manual u17702ej1v0ud 95 4.3.3 port 3 port 3 is a 10-bit i/o port for which i/o setti ngs can be controlled in 1-bit units. port 3 includes the following alternate functions. table 4-6. alternate-function pins of port 3 pin no. pin name alternate function i/o pull note remark block type 25 p30 txd0/to02 output e00-u 26 p31 rxd0/intp7/to03 i/o e10-suihl 27 p32 asck0/adtrg/to01 i/o e10-sul 28 p33 ti000/to00/tip00/ top00 i/o g1010-sul 29 p34 ti001/to00/tip01/ top01 i/o g1010-sul 30 p35 ti010/to01 i/o yes ? e10-sul 31 p36 ? ? c-n 32 p37 ? ? c-n 35 p38 sda0 i/o d2-snfh 36 p39 scl0 i/o no n-ch open-drain output d2-snfh note software pull-up function caution p31 to p35, p38, and p39 have hysteresis characteristics when th e alternate function is input, but not in the port mode. chapter 4 port functions preliminary user?s manual u17702ej1v0ud 96 (1) port 3 register (p3) 0 is output 1 is output p3n 0 1 control of output data (in output mode) (n = 0 to 9) p3 (p3h note ) after reset: 00h (output latch) r/w address: p3 fffff406h, p3l fffff406h, p3h fffff407h p37 p36 p35 p34 p33 p32 p31 p30 0 0 0 0 0 0 p39 p38 8 9 10 11 12 13 14 15 (p3l) note when reading from or writing to bits 8 to 15 of the p3 register in 8-bit or 1-bit units, specify these bits as bits 0 to 7 of the p3h register. remark the p3 register can be read or written in 16-bit units. however, when the higher 8 bits and the lowe r 8 bits of the p3 register are used as the p3h register and as the p3l register, re spectively, this register can be read or written in 8-bit or 1-bit units. (2) port 3 mode register (pm3) pm37 output mode input mode pm3n 0 1 control of i/o mode (n = 0 to 9) pm36 pm35 pm34 pm33 pm32 pm31 pm30 after reset: ffffh r/w address: pm3 fffff426h, pm3l fffff426h, pm3h fffff427h 1 pm3 (pm3h note ) 1 1 1 1 1 pm39 pm38 8 9 10 11 12 13 14 15 (pm3l) note when reading from or writing to bits 8 to 15 of the pm3 register in 8-bit or 1-bit units, specify these bits as bits 0 to 7 of the pm3h register. remark the pm3 register can be read or written in 16-bit units. when the higher 8 bits and the lower 8 bits of the pm3 register are used as the pm3h register and as the pm3l register, respective ly, this register can be read or written in 8-bit or 1-bit units. chapter 4 port functions preliminary user?s manual u17702ej1v0ud 97 (3) port 3 mode control register (pmc3) pmc3 (pmc3h note ) i/o port scl0 i/o pmc39 0 1 specification of p39 pin operation mode i/o port sda0 i/o pmc38 0 1 specification of p38 pin operation mode i/o port ti010 input/to01 output pmc35 0 1 specification of p35 pin operation mode i/o port ti001 input/to00 output/tip01 input/top01 output pmc34 0 1 specification of p34 pin operation mode i/o port ti000 input/to00 output/tip00 input/top00 output pmc33 0 1 specification of p33 pin operation mode i/o port asck0 input/adtrg input/to01 output pmc32 0 1 specification of p32 pin operation mode i/o port rxd0 input/intp7 input/to03 output pmc31 0 1 specification of p31 pin operation mode i/o port txd0 output/to02 output pmc30 0 1 specification of p30 pin operation mode after reset: 0000h r/w address: pmc3 fffff446h, pmc3l fffff446h, pmc3h fffff447h 0 0 pmc35 pmc34 pmc33 pmc32 pmc31 pmc30 0 0 0 0 0 0 pmc39 pmc38 8 9 10 11 12 13 14 15 (pmc3l) note when reading from or writing to bits 8 to 15 of the pmc3 register in 8-bit or 1-bit units, specify these bits as bits 0 to 7 of the pmc3h register. remark the pmc3 register can be read or written in 16-bit units. when the higher 8 bits and the lower 8 bits of the pmc3 register are used as the pmc3h register and as the pmc3l register, respectively, this register can be read or written in 8-bit or 1-bit units. chapter 4 port functions preliminary user?s manual u17702ej1v0ud 98 (4) port 3 function register h (pf3h) 0 when used as normal port (n-ch open-drain output) when used as alternate-function (n-ch open-drain output) pf3n 0 1 specification of normal port/alternate function (n = 8, 9) pf3h 0 0 0 0 0 pf39 pf38 after reset: 00h r/w address: fffffc67h caution when using p38 and p39 as n-ch open-drai n-output alternate-function pins, set in the following sequence. be sure to set the port latch to 1 before setting the pin to n-ch open-drain output. p3n bit = 1 pf3n bit = 1 pmc3n bit = 1 (5) port 3 function control register (pfc3) pfc3 after reset: 00h r/w address: fffff466h 0 0 pfc35 pfc34 pfc33 pfc32 pfc31 pfc30 remark for details of specification of alternate-function pins, refer to 4.3.3 (7) specifying alternate-function pins of port 3 . (6) port 3 function contro l expansion register (pfce3) pfce3 after reset: 00h r/w address: fffff706h 0 0 0 pfce34 pfce33 0 0 0 remark for details of specification of alternate-function pins, refer to 4.3.3 (7) specifying alternate-function pins of port 3 . chapter 4 port functions preliminary user?s manual u17702ej1v0ud 99 (7) specifying alternate-function pins of port 3 pfc35 specification of alter nate-function pin of p35 pin 0 ti010 input 1 to01 output pfce34 pfc34 specification of alte rnate-function pin of p34 pin 0 0 ti001 input 0 1 to00 output 1 0 tip01 input 1 1 top01 output pfce33 pfc33 specification of alte rnate-function pin of p33 pin 0 0 ti000 input 0 1 to00 output 1 0 tip00 input 1 1 top00 output pfc32 specification of alter nate-function pin of p32 pin 0 asck0/adtrg note 1 input 1 to01 output pfc31 specification of alter nate-function pin of p31 pin 0 rxd0/intp7 note 2 input 1 to03 output pfc30 specification of alter nate-function pin of p30 pin 0 txd0 output 1 to02 output notes 1. the asck0 and adtrg pins are alternate-function pins. when using the pin as the asck0 pin, disable the trigger input of the alternate-function adtrg pin (clear the ads.trg bit to 0 or set the ads.adtmd bit to 1). when using the pin as the adtrg pin, do not set the uart0 operation clock to external input (set the cksr0.tps03 to cksr0.tps00 bits to other than 1011). 2. the intp7 and rxd0 pins are alternate-function pi ns. when using the pin as the rxd0 pin, disable edge detection of the alternate-function intp7 pi n (clear the intf3.intf31 and intr3.intr31 bits to 0). when using the pin as the intp7 pin, stop the uart0 receive operation (c lear the asim0.rxe0 bit to 0). chapter 4 port functions preliminary user?s manual u17702ej1v0ud 100 (8) pull-up resistor option register 3 (pu3) 0 not connected connected pu3n 0 1 control of on-chip pull-up resistor connection (n = 0 to 5) pu3 0 pu35 pu34 pu33 pu32 pu31 pu30 after reset: 00h r/w address: fffffc46h chapter 4 port functions preliminary user?s manual u17702ej1v0ud 101 4.3.4 port 4 port 4 is a 3-bit i/o port for which i/o se ttings can be controll ed in 1-bit units. port 4 includes the following alternate functions. table 4-7. alternate-function pins of port 4 pin no. pin name alternate function i/o pull note remark block type 22 p40 si00/rxd2 input ? e11-sulh 23 p41 so00/txd2 output e00-uf 24 p42 sck00 i/o yes n-ch open-drain output can be selected. d2-sufl note software pull-up function cautions 1. p40 and p42 have hysteresis characteristi cs when the altern ate function is in put, but not in the port mode. 2. the v850es/kj2 also assigns the rxd2 pin func tion to the p80 pin. if the p40 and p80 pins are used as the rxd2 pin simultaneously , the uart2 receive operation may not be performed correctly. therefore, do not u se the p40 and p80 pins as the rxd2 pin simultaneously. (1) port 4 register (p4) 0 0 is output 1 is output p4n 0 1 control of output data (in output mode) (n = 0 to 2) p4 0 0 0 0 p42 p41 p40 after reset: 00h (output latch) r/w address: fffff408h (2) port 4 mode register (pm4) 1 output mode input mode pm4n 0 1 control of i/o mode (n = 0 to 2) pm4 1 1 1 1 pm42 pm41 pm40 after reset: ffh r/w address: fffff428h chapter 4 port functions preliminary user?s manual u17702ej1v0ud 102 (3) port 4 mode control register (pmc4) 0 pmc4 0 0 0 0 pmc42 pmc41 pmc40 i/o port sck00 i/o pmc42 0 1 specification of p42 pin operation mode i/o port so00 output/txd2 output pmc41 0 1 specification of p41 pin operation mode i/o port si00 input/rxd2 input pmc40 0 1 specification of p40 pin operation mode after reset: 00h r/w address: fffff448h (4) port 4 function control register (pfc4) 0 pfc4 0 0 0 0 0 pfc41 pfc40 so00 output txd2 output pfc41 0 1 specification of alternate-function pin of p41 pin specification of alternate-function pin of p40 pin si00 input rxd2 input pfc40 0 1 after reset: 00h r/w address: fffff468h chapter 4 port functions preliminary user?s manual u17702ej1v0ud 103 (5) port 4 function register (pf4) 0 normal output n-ch open-drain output pf4n 0 1 control of normal output/n-ch open-drain output (n = 1, 2) pf4 0 0 0 0 pf42 pf41 0 after reset: 00h r/w address: fffffc68h caution when using p41 and p42 as n-ch open- drain-output alternate-function pins, set in the following sequence. be sure to set the port latch to 1 before setting the pin to n-ch open-drain output. p4n bit = 1 pf4n bit = 1 pmc4n bit = 1 (6) pull-up resistor option register 4 (pu4) 0 not connected connected pu4n 0 1 control of on-chip pull-up resistor connection (n = 0 to 2) pu4 0 0 0 0 pu42 pu41 pu40 after reset: 00h r/w address: fffffc48h chapter 4 port functions preliminary user?s manual u17702ej1v0ud 104 4.3.5 port 5 port 5 is a 6-bit i/o port for which i/o se ttings can be controll ed in 1-bit units. port 5 includes the following alternate functions. table 4-8. alternate-function pins of port 5 pin no. pin name alternate function i/o pull note 1 remark block type 37 p50 ti011/rtp00/kr0 i/o e10-sult 38 p51 ti50/rtp01/kr1 i/o e10-sult p52 note 2 to50/rtp02/kr2 i/o e00-sut 39 p52 note 3 to50/rtp02/kr2/ddi note 4 i/o oe001-sut p53 note 2 sia0/rtp03/kr3 i/o e10-sult 40 p53 note 3 sia0/rtp03/kr3/ddo note 4 i/o ? oe100-sult p54 note 2 soa0/rtp04/kr4 i/o e00-suft 41 p54 note 3 soa0/rtp04/kr4/dck note 4 i/o oe001-suft p55 note 2 scka0/rtp05/kr5 i/o e20-suflt 42 p55 note 3 soka0/rtp05/kr5/dms note 4 i/o yes n-ch open-drain output can be selected. oe201-suflt notes 1. software pull-up function 2. only in the pd70f3733 3. only in the pd70f3734 4. the ddi, ddo, dck, and dms pins are for on-chip debugging ( pd70f3734 only). if on-chip debugging is not used, fix the p05 /intp2/drst pin to low level between when the reset signal of the reset pin is released and wh en the ocdm.ocdm0 bit is cleared (0). for details, see 4.6.3 cautions on p05 pin . (1) port 5 register (p5) 0 is output 1 is output p5n 0 1 control of output data (in output mode) (n = 0 to 5) p5 after reset: 00h (output latch) r/w address: fffff40ah 0 0 p55 p54 p53 p52 p51 p50 chapter 4 port functions preliminary user?s manual u17702ej1v0ud 105 (2) port 5 mode register (pm5) 1 output mode input mode pm5n 0 1 control of i/o mode (n = 0 to 5) 1 pm55 pm54 pm53 pm52 pm51 pm50 after reset: ffh r/w address: fffff42ah pm5 chapter 4 port functions preliminary user?s manual u17702ej1v0ud 106 (3) port 5 mode control register (pmc5) i/o port/kr5 input scka0 i/o/rtp05 output pmc55 0 1 specification of p55 pin operation mode i/o port/kr4 input soa0 output/rtp04 output pmc54 0 1 specification of p54 pin operation mode 0 0 pmc55 pmc54 pmc53 pmc52 pmc51 pmc50 after reset: 00h r/w address: fffff44ah pmc5 i/o port/kr3 input sia0 input/rtp03 output pmc53 0 1 specification of p53 pin operation mode i/o port/kr2 input to50 output/rtp02 output pmc52 0 1 specification of p52 pin operation mode i/o port/kr1 input ti50 input/rtp01 output pmc51 0 1 specification of p51 pin operation mode i/o port/kr0 input ti011 input/rtp00 output pmc50 0 1 specification of p50 pin operation mode (4) port 5 function register 5 (pf5) 0 normal output n-ch open-drain output pf5n 0 1 control of normal output/n-ch open-drain output (n = 4, 5) pf5 0 pf55 pf54 0 0 0 0 after reset: 00h r/w address: fffffc6ah cautions 1. always set bits 0 to 3, 6, and 7 of the pf5 register to 0. 2. when using p54 and p55 as n-ch open-dr ain-output alternate-function pins, set in the following sequence. be sure to set the port latch to 1 before setting the pin to n-ch open-drain output. p5n bit = 1 pf5n bit = 1 pmc5n bit = 1 chapter 4 port functions preliminary user?s manual u17702ej1v0ud 107 (5) port 5 function control register (pfc5) pfc5 scka0 i/o rtp05 output pfc55 0 1 specification of alternate-function pin of p55 pin sia0 input rtp03 output pfc53 0 1 specification of alternate-function pin of p53 pin soa0 output rtp04 output pfc54 0 1 specification of alternate-function pin of p54 pin after reset: 00h r/w address: fffff46ah 0 0 pfc55 pfc54 pfc53 pfc52 pfc51 pfc50 to50 output rtp02 output pfc52 0 1 specification of alternate-function pin of p52 pin ti50 input rtp01 output pfc51 0 1 specification of alternate-function pin of p51 pin ti011 input rtp00 output pfc50 0 1 specification of alternate-function pin of p50 pin (6) pull-up resistor option register 5 (pu5) 0 not connected connected pu5n 0 1 control of on-chip pull-up resistor connection (n = 0 to 5) 0 pu55 pu54 pu53 pu52 pu51 pu50 after reset: 00h r/w address: fffffc4ah pu5 chapter 4 port functions preliminary user?s manual u17702ej1v0ud 108 4.3.6 port 6 port 6 is a 16-bit i/o port for which i/o setti ngs can be controlled in 1-bit units. port 6 includes the following alternate functions. table 4-9. alternate-function pins of port 6 pin no. pin name alternate function i/o pull note remark block type 43 p60 rtp10 output d0-u 44 p61 rtp11 output d0-u 45 p62 rtp12 output d0-u 46 p63 rtp13 output d0-u 47 p64 rtp14 output d0-u 48 p65 rtp15 output d0-u 49 p66 si02 input ? d1-sul 50 p67 so02 output d0-uf 51 p68 sck02 i/o n-ch open-drain output d2-sufl 52 p69 ti040 input d1-sul 53 p610 ti041 input d1-sul 54 p611 to04 output d0-u 55 p612 ti050 input d1-sul 56 p613 ti051/to05 i/o yes e10-sul 57 p614 ? ? c-n 58 p615 ? ? no ? c-n note software pull-up function caution p66, p68, p69, p610, p612, and p613 have h ysteresis characteristics when the alternate function is input, but not in the port mode. chapter 4 port functions preliminary user?s manual u17702ej1v0ud 109 (1) port 6 register (p6) 0 is output 1 is output p6n 0 1 control of output data (in output mode) (n = 0 to 15) p6 (p6h note ) after reset: 00h (output latch) r/w address: p6 fffff40ch, p6l fffff40ch, p6h fffff40dh p67 p66 p65 p64 p63 p62 p61 p60 p615 p614 p613 p612 p611 p610 p69 p68 8 9 10 11 12 13 14 15 (p6l) note when reading from or writing to bits 8 to 15 of the p6 register in 8-bit or 1-bit units, specify these bits as bits 0 to 7 of the p6h register. remark the p6 register can be read or written in 16-bit units. however, when the higher 8 bits and the lower 8 bits of the p6 register are used as the p6h register and as the p6l register, re spectively, this register can be read or written in 8-bit or 1-bit units. (2) port 6 mode register (pm6) pm67 output mode input mode pm6n 0 1 control of i/o mode (n = 0 to 15) pm66 pm65 pm64 pm63 pm62 pm61 pm60 after reset: ffffh r/w address: pm6 fffff42ch, pm6l fffff42ch, pm6h fffff42dh pm615 pm6 (pm6h note ) pm614 pm613 pm612 pm611 pm610 pm69 pm68 8 9 10 11 12 13 14 15 (pm6l) note when reading from or writing to bits 8 to 15 of the pm6 register in 8-bit or 1-bit units, specify these bits as bits 0 to 7 of the pm6h register. remark the pm6 register can be read or written in 16-bit units. however, when the higher 8 bits and the lo wer 8 bits of the pm6 register are used as the pm6h register and as the pm6l register, re spectively, this register can be read or written in 8-bit or 1-bit units. chapter 4 port functions preliminary user?s manual u17702ej1v0ud 110 (3) port 6 mode control register (pmc6) pmc6 (pmc6h note ) i/o port ti051 input/to05 output pmc613 0 1 specification of p613 pin operation mode i/o port ti041 input pmc610 0 1 specification of p610 pin operation mode i/o port ti040 input pmc69 0 1 specification of p69 pin operation mode i/o port sck02 i/o pmc68 0 1 specification of p68 pin operation mode i/o port so02 output pmc67 0 1 specification of p67 pin operation mode i/o port si02 input pmc66 0 1 specification of p66 pin operation mode i/o port rtp1n output pmc6n 0 1 specification of p6n pin operation mode (n = 0 to 5) after reset: 0000h r/w address: pmc6 fffff44ch, pmc6l fffff44ch, pmc6h fffff44dh pmc67 pmc66 pmc65 pmc64 pmc63 pmc62 pmc61 pmc60 0 0 pmc613 pmc612 pmc611 pmc610 pmc69 pmc68 8 9 10 11 12 13 14 15 i/o port ti050 input pmc612 0 1 specification of p612 pin operation mode i/o port to04 output pmc611 0 1 specification of p611 pin operation mode (pmc6l) note when reading from or writing to bits 8 to 15 of the pmc6 register in 8-bit or 1-bit units, specify these bits as bits 0 to 7 of the pmc6h register. remark the pmc6 register can be read or written in 16-bit units. however, when the higher 8 bits and the lo wer 8 bits of the pmc6 register are used as the pmc6h register and as the pmc6l r egister, respectively, this register can be read or written in 8-bit or 1-bit units. chapter 4 port functions preliminary user?s manual u17702ej1v0ud 111 (4) port 6 function register (pf6) normal output n-ch open-drain output pf6n 0 1 control of normal output/n-ch open-drain output (n = 7, 8) pf6 (pf6h note ) after reset: 0000h r/w address: pf6 fffffc6ch, pf6l fffffc6ch, pf6h fffffc6dh pf67 0 0 0 0 0 0 0 0 0 0 0 0 0 0 pf68 8 9 10 11 12 13 14 15 (pf6l) note when reading from or writing to bits 8 to 15 of the pf6 register in 8-bit or 1-bit units, specify these bits as bits 0 to 7 of the pf6h register. caution always set pf6 register bits 0 to 6 and 9 to 15 to 0. remark the pf6 register can be read or written in 16-bit units. however, when the higher 8 bits and the lo wer 8 bits of the pf6 register are used as the pf6h register and as the pf6l register, respectively, this register can be read or written in 8-bit or 1-bit units. (5) port 6 function control register (pfc6h) pfc6h ti051 input to05 output pfc613 0 1 specification of alternate-function pin of p613 pin after reset: 00h r/w address: fffff46dh 0 0 pfc613 0 0 0 0 0 chapter 4 port functions preliminary user?s manual u17702ej1v0ud 112 (6) pull-up resistor option register 6 (pu6) not connected connected pu6n 0 1 control of on-chip pull-up resistor connection (n = 0 to 13) pu6 (pu6h note ) after reset: 0000h r/w address: pu6 fffffc4ch, pu6l fffffc4ch, pu6h fffffc4dh pu67 pu66 pu65 pu64 pu63 pu62 pu61 pu60 0 0 pu613 pu612 pu611 pu610 pu69 pu68 8 9 10 11 12 13 14 15 (pu6l) note when reading from or writing to bits 8 to 15 of the pu6 register in 8-bit or 1-bit units, specify these bits as bits 0 to 7 of the pu6h register. remark the pu6 register can be read or written in 16-bit units. however, when the higher 8 bits and the lowe r 8 bits of the pu6 register are used as the pu6h register and as the pu6l register, respectively, this register can be read or written in 8-bit or 1-bit units. chapter 4 port functions preliminary user?s manual u17702ej1v0ud 113 4.3.7 port 7 port 7 is a 16-bit input-only port for which all the pins are fixed to input. port 7 includes the following alternate functions. table 4-10. alternate-function pins of port 7 pin no. pin name alternate function i/o pull note remark block type 144 p70 ani0 input a-a 143 p71 ani1 input a-a 142 p72 ani2 input a-a 141 p73 ani3 input a-a 140 p74 ani4 input a-a 139 p75 ani5 input a-a 138 p76 ani6 input a-a 137 p77 ani7 input a-a 136 p78 ani8 input a-a 135 p79 ani9 input a-a 134 p710 ani10 input a-a 133 p711 ani11 input a-a 132 p712 ani12 input a-a 131 p713 ani13 input a-a 130 p714 ani14 input a-a 129 p715 ani15 input no ? a-a note software pull-up function (1) port 7 register (p7) p715 input low level input high level p7n 0 1 input data read (n = 0 to 15) p7 (p7h note ) p714 p713 p712 p711 p710 p79 p78 after reset: undefined r address: p7 fffff40eh, p7l fffff40eh, p7h fffff40fh p77 p76 p75 p74 p73 p72 p71 p70 8 9 10 11 12 13 14 15 (p7l) note when reading from bits 8 to 15 of the p7 register in 8-bit or 1-bit units, specify these bits as bits 0 to 7 of the p7h register. remark the p7 register can be read only in 16-bit units. however, when the higher 8 bits of the p7 register are used as the p7h register and the lower 8 bits as the p7l register, they can be read only in 8-bit units. chapter 4 port functions preliminary user?s manual u17702ej1v0ud 114 4.3.8 port 8 port 8 is a 2-bit i/o port for which i/o se ttings can be controlled in 1-bit units. port 8 includes the following alternate functions. table 4-11. alternate-function pins of port 8 pin no. pin name alternate function i/o pull note remark block type 59 p80 rxd2/sda1 i/o e12-sufhh 60 p81 txd2/scl1 i/o yes n-ch open-drain output can be selected. e02-sufh note software pull-up function cautions 1. p80 and p81 have hysteresis characteristi cs when the altern ate function is in put, but not in the port mode. 2. the v850es/kj2 also assigns the rxd2 pin func tion to the p40 pin. if the p40 and p80 pins are used as the rxd2 pin simultaneously , the uart2 receive operation may not be performed correctly. therefore, do not u se the p40 and p80 pins as the rxd2 pin simultaneously. (1) port 8 register (p8) 0 0 is output 1 is output p8n 0 1 control of output data (in output mode) (n = 0, 1) p8 0 0 0 0 0 p81 p80 after reset: 00h (output latch) r/w address: fffff410h (2) port 8 mode register (pm8) 1 output mode input mode pm8n 0 1 control of i/o mode (n = 0, 1) 1 1 1 1 1 pm81 pm80 after reset: ffh r/w address: fffff430h pm8 chapter 4 port functions preliminary user?s manual u17702ej1v0ud 115 (3) port 8 mode control register (pmc8) 0 0 0 0 0 0 pmc81 pmc80 after reset: 00h r/w address: fffff450h pmc8 i/o port txd2 output/scl1 i/o pmc81 0 1 specification of p81 pin operation mode i/o port rxd2 input/sda1 i/o pmc80 0 1 specification of p80 pin operation mode (4) port 8 function register (pf8) 0 normal output n-ch open-drain output pf8n 0 1 control of normal output/n-ch open-drain output (n = 0, 1) pf8 0 0 0 0 0 pf81 pf80 after reset: 00h r/w address: fffffc70h caution when using p80 and p81 as n-ch open-dr ain-output alternate-function pins, set in the following sequence. be sure to set the port latch to 1 be fore setting the pin to n-ch open-drain output. p8n bit = 1 pfc8n bit = 0/1 pf8n bit = 1 pmc8n bit = 1 chapter 4 port functions preliminary user?s manual u17702ej1v0ud 116 (5) port 8 function control register (pfc8) pfc8 txd2 output scl1 i/o pfc81 0 1 specification of alternate-function pin of p81 pin rxd2 input sda1 i/o pfc80 0 1 specification of alternate-function pin of p80 pin after reset: 00h r/w address: fffff470h 0 0 0 0 0 0 pfc81 pfc80 (6) pull-up resistor option register 8 (pu8) 0 not connected connected pu8n 0 1 control of on-chip pull-up resistor connection (n = 0, 1) 0 0 0 0 0 pu81 pu80 after reset: 00h r/w address: fffffc50h pu8 chapter 4 port functions preliminary user?s manual u17702ej1v0ud 117 4.3.9 port 9 port 9 is a 16-bit i/o port for which i/o setti ngs can be controlled in 1-bit units. port 9 includes the following alternate functions. table 4-12. alternate-function pins of port 9 pin no. pin name alternate function i/o pull note remark block type 61 p90 a0/txd1/kr6 i/o e00-sutz 62 p91 a1/rxd1/kr7 i/o e01-suhtz 63 p92 a2/ti020/to02 i/o e00-sutz 64 p93 a3/ti021 i/o e01-sulz 65 p94 a4/ti030/to03 i/o e00-sutz 66 p95 a5/ti031 i/o e01-sulz 67 p96 a6/ti51/to51 i/o e00-sutz 68 p97 a7/si01 i/o ? e01-sulz 69 p98 a8/so01 output e00-ufz 70 p99 a9/sck01 i/o n-ch open-drain output can be specified. e02-suflz 71 p910 a10/sia1 i/o ? e01-sulz 72 p911 a11/soa1 output e00-ufz 73 p912 a12/scka1 i/o n-ch open-drain output can be specified. e02-suflz 74 p913 a13/intp4 i/o e01-suilz 75 p914 a14/intp5 i/o e01-suilz 76 p915 a15/intp6 i/o yes analog noise elimination e01-suilz note software pull-up function caution p93, p95, p97, p99, p910, and p912 to p915 have hysteresis characteri stics when the alternate function is input, but not in the port mode. chapter 4 port functions preliminary user?s manual u17702ej1v0ud 118 (1) port 9 register (p9) 0 is output 1 is output p9n 0 1 control of output data (in output mode) (n = 0 to 15) after reset: 00h (output latch) r/w address: p9h fffff412h, p9l fffff412h, p9h fffff413h p915 p9 (p9h note ) p914 p913 p912 p911 p910 p99 p98 p97 p96 p95 p94 p93 p92 p91 p90 8 9 10 11 12 13 14 15 (p9l) note when reading from or writing to bits 8 to 15 of the p9 register in 8-bit or 1-bit units, specify these bits as bits 0 to 7 of the p9h register. remark the p9 register can be read or written in 16-bit units. however, when the higher 8 bits and the lower 8 bits of the p9 register are used as the p9h register and as the p9l register, re spectively, these registers can be read or written in 8-bit or 1-bit units. (2) port 9 mode register (pm9) pm97 output mode input mode pm9n 0 1 control of i/o mode (n = 0 to 15) pm96 pm95 pm94 pm93 pm92 pm91 pm90 after reset: ffffh r/w address: pm9 fffff432h, pm9l fffff432h, pm9h fffff433h pm915 pm9 (pm9h note ) pm914 pm913 pm912 pm911 pm910 pm99 pm98 8 9 10 11 12 13 14 15 (pm9l) note when reading from or writing to bits 8 to 15 of the pm9 register in 8-bit or 1-bit units, specify these bits as bits 0 to 7 of the pm9h register. remark the pm9 register can be read or written in 16-bit units. however, when the higher 8 bits and the lo wer 8 bits of the pm9 register are used as the pm9h register and as the pm9l register, re spectively, this register can be read or written in 8-bit or 1-bit units. (3) port 9 mode control register (pmc9) caution when using port 9 as the a0 to a15 pins, set the pmc9 register to ffffh in 16-bit units. chapter 4 port functions preliminary user?s manual u17702ej1v0ud 119 (1/2) i/o port a15 output/intp6 input pmc915 0 1 specification of p915 pin operation mode pmc97 pmc96 pmc95 pmc94 pmc93 pmc92 pmc91 pmc90 after reset: 0000h r/w address: pmc9 fffff452h, pmc9l fffff452h, pmc9h fffff453h pmc915 pmc9 (pmc9h note ) pmc914 pmc913 pmc912 pmc911 pmc910 pmc99 pmc98 8 9 10 11 12 13 14 15 i/o port a14 output/intp5 input pmc914 0 1 specification of p914 pin operation mode i/o port a11 output/soa1 output pmc911 0 1 specification of p911 pin operation mode i/o port a10 output/sia1 input pmc910 0 1 specification of p910 pin operation mode i/o port a9 output/sck01 i/o pmc99 0 1 specification of p99 pin operation mode i/o port a13 output/intp4 input pmc913 0 1 specification of p913 pin operation mode i/o port a12 output/scka1 i/o pmc912 0 1 specification of p912 pin operation mode i/o port a8 output/so01 output pmc98 0 1 specification of p98 pin operation mode (pmc9l) note when reading from or writing to bits 8 to 15 of the pmc9 register in 8-bit or 1-bit units, specify these bits as bits 0 to 7 of the pmc9h register. remark the pmc9 register can be read or written in 16-bit units. however, when the higher 8 bits and the lo wer 8 bits of the pmc9 register are used as the pmc9h register and as the pmc9l r egister, respectively, these registers can be read or written in 8-bit or 1-bit units. chapter 4 port functions preliminary user?s manual u17702ej1v0ud 120 (2/2) i/o port a7 output/si01 input pmc97 0 1 specification of p97 pin operation mode i/o port/ti51 input a6 output/to51 output pmc96 0 1 specification of p96 pin operation mode i/o port a5 output/ti031 input pmc95 0 1 specification of p95 pin operation mode i/o port/ti030 input a4 output/to03 output pmc94 0 1 specification of p94 pin operation mode i/o port a3 output/ti021 input pmc93 0 1 specification of p93 pin operation mode i/o port/ti020 input a2 output/to02 output pmc92 0 1 specification of p92 pin operation mode i/o port/kr7 input a1 output/rxd1 input pmc91 0 1 specification of p91 pin operation mode i/o port/kr6 input a0 output/txd1 output pmc90 0 1 specification of p90 pin operation mode chapter 4 port functions preliminary user?s manual u17702ej1v0ud 121 (4) port 9 function register h (pf9h) 0 normal output n-ch open-drain output pf9n 0 1 control of normal output/n-ch open-drain output (n = 8, 9, 11, 12) pf9h 0 0 pf912 pf911 0 pf99 pf98 after reset: 00h r/w address: fffffc73h caution when using p98, p99, p911, and p912 as n-ch open-drain-output alternate- function pins, set in the following sequence. be sure to set the port latch to 1 be fore setting the pin to n-ch open-drain output. p9n bit = 1 pfc9n bit = 0/1 pf9n bit = 1 pmc9n bit = 1 (5) port 9 function control register (pfc9) caution when using port 9 as the a0 to a15 pins, set the pfc9 register to 0000h in 16-bit units. chapter 4 port functions preliminary user?s manual u17702ej1v0ud 122 (1/2) pfc9 (pfc9h note ) a15 output intp6 input pfc915 0 1 specification of alternate-function pin of p915 pin a14 output intp5 input pfc914 0 1 specification of alternate-function pin of p914 pin a13 output intp4 input pfc913 0 1 specification of alternate-function pin of p913 pin a12 output scka1 i/o pfc912 0 1 specification of alternate-function pin of p912 pin after reset: 0000h r/w address: pfc9 fffff472h, pfc9l fffff472h, pfc9h fffff473h pfc97 pfc96 pfc95 pfc94 pfc93 pfc92 pfc91 pfc90 pfc915 pfc914 pfc913 pfc912 pfc911 pfc910 pfc99 pfc98 8 9 10 11 12 13 14 15 a11 output soa1 output pfc911 0 1 specification of alternate-function pin of p911 pin a10 output sia1 input pfc910 0 1 specification of alternate-function pin of p910 pin a9 output sck01 i/o pfc99 0 1 specification of alternate-function pin of p99 pin a8 output so01 output pfc98 0 1 specification of alternate-function pin of p98 pin (pfc9l) note when reading from or writing to bits 8 to 15 of the pfc9 register in 8-bit or 1-bit units, specify these bits as bits 0 to 7 of the pfc9h register. remark the pfc9 register can be read or written in 16-bit units. however, when the higher 8 bits and the lo wer 8 bits of the pfc9 register are used as the pfc9h register and as t he pfc9l register, respective ly, these registers can be read or written in 8-bit or 1-bit units. chapter 4 port functions preliminary user?s manual u17702ej1v0ud 123 (2/2) a7 output si01 input pfc97 0 1 specification of alternate-function pin of p97 pin a6 output to51 output pfc96 0 1 specification of alternate-function pin of p96 pin a5 output ti031 input pfc95 0 1 specification of alternate-function pin of p95 pin a4 output to03 output pfc94 0 1 specification of alternate-function pin of p94 pin a3 output ti021 input pfc93 0 1 specification of alternate-function pin of p93 pin a2 output to02 output pfc92 0 1 specification of alternate-function pin of p92 pin a1 output rxd1 input pfc91 0 1 specification of alternate-function pin of p91 pin a0 output txd1 output pfc90 0 1 specification of alternate-function pin of p90 pin chapter 4 port functions preliminary user?s manual u17702ej1v0ud 124 (6) pull-up resistor option register 9 (pu9) not connected connected pu9n 0 1 control of on-chip pull-up resistor connection (n = 0 to 15) pu9 (pu9h note ) after reset: 0000h r/w address: pu9 fffffc52h, pu9l fffffc52h, pu9h fffffc53h pu97 pu96 pu95 pu94 pu93 pu92 pu91 pu90 pu915 pu914 pu913 pu912 pu911 pu910 pu99 pu98 8 9 10 11 12 13 14 15 (pu9l) note when reading from or writing to bits 8 to 15 of the pu9 register in 8-bit or 1-bit units, specify these bits as bits 0 to 7 of the pu9h register. remark the pu9 register can be read or written in 16-bit units. however, when the higher 8 bits and the lo wer 8 bits of the pu9 register are used as the pu9h register and as the pu9l register, respectively, these registers can be read or written in 8-bit or 1-bit units. chapter 4 port functions preliminary user?s manual u17702ej1v0ud 125 4.3.10 port cd port cd is a 4-bit i/o port for which i/o setti ngs can be controlled in 1-bit units. port cd does not have alternate-function pins. table 4-13. alternate-function pins of port cd pin no. pin name alternate function i/o pull note remark block type 77 pcd0 ? ? c-u 78 pcd1 ? ? c-u 79 pcd2 ? ? c-u 80 pcd3 ? ? yes ? c-u note software pull-up function chapter 4 port functions preliminary user?s manual u17702ej1v0ud 126 (1) port cd register (pcd) 0 0 is output 1 is output pcdn 0 1 control of output data (in output mode) (n = 0 to 3) pcd 0 0 0 pcd3 pcd2 pcd1 pcd0 after reset: 00h (output latch) r/w address: fffff00eh (2) port cd mode register (pmcd) 1 output mode input mode pmcdn 0 1 control of i/o mode (n = 0 to 3) pmcd 1 1 1 pmcd3 pmcd2 pmcd1 pmcd0 after reset: ffh r/w address: fffff02eh (3) pull-up resistor option register cd (pucd) 0 not connected connected pucdn 0 1 control of on-chip pull-up resistor connection (n = 0 to 3) pucd 0 0 0 pucd3 pucd2 pucd1 pucd0 after reset: 00h r/w address: ffffff4eh chapter 4 port functions preliminary user?s manual u17702ej1v0ud 127 4.3.11 port cm port cm is a 6-bit i/o port for which i/o se ttings can be controlled in 1-bit units. port cm includes the following alternate functions. table 4-14. alternate-function pins of port cm pin no. pin name alternate function i/o pull note remark block type 85 pcm0 wait input d1-uh 86 pcm1 clkout output d0-u 87 pcm2 hldak output d0-u 88 pcm3 hldrq input d1-uh 89 pcm4 ? ? c-u 90 pcm5 ? ? yes ? c-u note software pull-up function (1) port cm register (pcm) 0 is output 1 is output pcmn 0 1 control of output data (in output mode) (n = 0 to 5) after reset: 00h (output latch) r/w address: fffff00ch 0 pcm 0 pcm5 pcm4 pcm3 pcm2 pcm1 pcm0 (2) port cm mode register (pmcm) output mode input mode pmcmn 0 1 control of i/o mode (n = 0 to 5) after reset: ffh r/w address: fffff02ch 1 pmcm 1 pmcm5 pmcm4 pmcm3 pmcm2 pmcm1 pmcm0 chapter 4 port functions preliminary user?s manual u17702ej1v0ud 128 (3) port cm mode control register (pmccm) 0 pmccm 0 0 0 pmccm3 pmccm2 pmccm1 pmccm0 i/o port hldrq input pmccm3 0 1 specification of pcm3 pin operation mode i/o port hldak output pmccm2 0 1 specification of pcm2 pin operation mode i/o port clkout output pmccm1 0 1 specification of pcm1 pin operation mode i/o port wait input pmccm0 0 1 specification of pcm0 pin operation mode after reset: 00h r/w address: fffff04ch (4) pull-up resistor option register cm (pucm) not connected connected pucmn 0 1 control of on-chip pull-up resistor connection (n = 0 to 5) after reset: 00h r/w address: ffffff4ch 0 pucm 0 pucm5 pucm4 pucm3 pucm2 pucm1 pucm0 chapter 4 port functions preliminary user?s manual u17702ej1v0ud 129 4.3.12 port cs port cs is an 8-bit i/o port for which i/o setti ngs can be controlled in 1-bit units. port cs includes the following alternate functions. table 4-15. alternate-function pins of port cs pin no. pin name alternate function i/o pull note remark block type 81 pcs0 cs0 output d0-uz 82 pcs1 cs1 output d0-uz 83 pcs2 cs2 output d0-uz 84 pcs3 cs3 output d0-uz 91 pcs4 ? ? c-u 92 pcs5 ? ? c-u 93 pcs6 ? ? c-u 94 pcs7 ? ? yes ? c-u note software pull-up function (1) port cs register (pcs) 0 is output 1 is output pcsn 0 1 control of output data (in output mode) (n = 0 to 7) after reset: 00h (output latch) r/w address: fffff008h pcs7 pcs pcs6 pcs5 pcs4 pcs3 pcs2 pcs1 pcs0 (2) port cs mode register (pmcs) pmcs7 output mode input mode pmcsn 0 1 control of i/o mode (n = 0 to 7) pmcs pmcs6 pmcs5 pmcs4 pmcs3 pmcs2 pmcs1 pmcs0 after reset: ffh r/w address: fffff028h chapter 4 port functions preliminary user?s manual u17702ej1v0ud 130 (3) port cs mode control register (pmccs) 0 i/o port csn output pmccsn 0 1 specification of pcsn pin operation mode (n = 0 to 3) pmccs 0 0 0 pmccs3 pmccs2 pmccs1 pmccs0 after reset: 00h r/w address: fffff048h (4) pull-up resistor option register cs (pucs) pucs7 not connected connected pucsn 0 1 control of on-chip pull-up resistor connection (n = 0 to 7) pucs pucs6 pucs5 pucs4 pucs3 pucs2 pucs1 pucs0 after reset: 00h r/w address: ffffff48h chapter 4 port functions preliminary user?s manual u17702ej1v0ud 131 4.3.13 port ct port ct is an 8-bit i/o port for which i/o se ttings can be controlled in 1-bit units. port ct includes the following alternate functions. table 4-16. alternate-function pins of port ct pin no. pin name alternate function i/o pull note remark block type 95 pct0 wr0 output d0-uz 96 pct1 wr1 output d0-uz 97 pct2 ? ? c-u 98 pct3 ? ? c-u 99 pct4 rd output d0-uz 100 pct5 ? ? c-u 101 pct6 astb output d0-uz 102 pct7 ? ? yes ? c-u note software pull-up function (1) port ct register (pct) pct7 0 is output 1 is output pctn 0 1 control of output data (in output mode) (n = 0 to 7) pct pct6 pct5 pct4 pct3 pct2 pct1 pct0 after reset: 00h (output latch) r/w address: fffff00ah (2) port ct mode register (pmct) pmct7 output mode input mode pmctn 0 1 control of i/o mode (n = 0 to 7) pmct pmct6 pmct5 pmct4 pmct3 pmct2 pmct1 pmct0 after reset: ffh r/w address: fffff02ah chapter 4 port functions preliminary user?s manual u17702ej1v0ud 132 (3) port ct mode control register (pmcct) 0 pmcct pmcct6 0 pmcct4 0 0 pmcct1 pmcct0 i/o port astb output pmcct6 0 1 specification of pct6 pin operation mode i/o port rd output pmcct4 0 1 specification of pct4 pin operation mode i/o port wr1 output pmcct1 0 1 specification of pct1 pin operation mode i/o port wr0 output pmcct0 0 1 specification of pct0 pin operation mode after reset: 00h r/w address: fffff04ah (4) pull-up resistor option register ct (puct) puct7 not connected connected puctn 0 1 control of on-chip pull-up resistor connection (n = 0 to 7) puct puct6 puct5 puct4 puct3 puct2 puct1 puct0 after reset: 00h r/w address: ffffff4ah chapter 4 port functions preliminary user?s manual u17702ej1v0ud 133 4.3.14 port dh port dh is an 8-bit i/o port for which i/o setti ngs can be controlled in 1-bit units. port dh includes the following alternate functions. table 4-17. alternate-function pins of port dh pin no. pin name alternate function i/o pull note remark block type 121 pdh0 a16 output d0-uz 122 pdh1 a17 output d0-uz 123 pdh2 a18 output d0-uz 124 pdh3 a19 output d0-uz 125 pdh4 a20 output d0-uz 126 pdh5 a21 output d0-uz 127 pdh6 a22 output d0-uz 128 pdh7 a23 output yes ? d0-uz note software pull-up function (1) port dh register (pdh) 0 is output 1 is output pdhn 0 1 control of output data (in output mode) (n = 0 to 7) pdh after reset: 00h (output latch) r/w address: fffff006h pdh7 pdh6 pdh5 pdh4 pdh3 pdh2 pdh1 pdh0 (2) port dh mode register (pmdh) pmdh7 output mode input mode pmdhn 0 1 control of i/o mode (n = 0 to 7) pmdh6 pmdh5 pmdh4 pmdh3 pmdh2 pmdh1 pmdh0 after reset: ffh r/w address: fffff026h pmdh chapter 4 port functions preliminary user?s manual u17702ej1v0ud 134 (3) port dh mode control register (pmcdh) i/o port am output (address bus output) (m = 16 to 23) pmcdhn 0 1 specification of pdhn pin operation mode (n = 0 to 7) pmcdh7 pmcdh6 pmcdh5 pmcdh4 pmcdh3 pmcdh2 pmcdh1 pmcdh0 after reset: 00h r/w address: fffff046h pmcdh caution when specifying the por t/alternate function for each bi t, pay careful attention to the operation of the alternate functions. (4) pull-up resistor option register dh (pudh) not connected connected pudhn 0 1 control of on-chip pull-up resistor connection (n = 0 to 7) pudh7 pudh6 pudh5 pudh4 pudh3 pudh2 pudh1 pudh0 after reset: 00h r/w address: ffffff46h pudh chapter 4 port functions preliminary user?s manual u17702ej1v0ud 135 4.3.15 port dl port dl is a 16-bit i/o port for which i/o se ttings can be controlled in 1-bit units. port dl includes the following alternate functions. table 4-18. alternate-function pins of port dl pin no. pin name alternate function i/o pull note remark block type 105 pdl0 ad0 i/o d2-ulz 106 pdl1 ad1 i/o d2-ulz 107 pdl2 ad2 i/o d2-ulz 108 pdl3 ad3 i/o d2-ulz 109 pdl4 ad4 i/o d2-ulz 110 pdl5 ad5 i/o d2-ulz 111 pdl6 ad6 i/o d2-ulz 112 pdl7 ad7 i/o d2-ulz 113 pdl8 ad8 i/o d2-ulz 114 pdl9 ad9 i/o d2-ulz 115 pdl10 ad10 i/o d2-ulz 116 pdl11 ad11 i/o d2-ulz 117 pdl12 ad12 i/o d2-ulz 118 pdl13 ad13 i/o d2-ulz 119 pdl14 ad14 i/o d2-ulz 120 pdl15 ad15 i/o yes ? d2-ulz note software pull-up function chapter 4 port functions preliminary user?s manual u17702ej1v0ud 136 (1) port dl register (pdl) pdl15 0 is output 1 is output pdln 0 1 control of output data (in output mode) (n = 0 to 15) pdl (pdlh note ) pdl14 pdl13 pdl12 pdl11 pdl10 pdl9 pdl8 after reset: 00h (output latch) r/w address: pdl fffff004h, pdll fffff004h, pdlh fffff005h pdl7 pdl6 pdl5 pdl4 pdl3 pdl2 pdl1 pdl0 8 9 10 11 12 13 14 15 (pdll) note when reading from or writing to bits 8 to 15 of the pdl register in 8-bit or 1-bit units, specify these bits as bits 0 to 7 of the pdlh register. remark the pdl register can be read or written in 16-bit units. however, when the higher 8 bits and the lowe r 8 bits of the pdl register are used as the pdlh register and as the pdll register, respectively, these registers can be read or written in 8-bit or 1-bit units. (2) port dl mode register (pmdl) pmdl7 output mode input mode pmdln 0 1 control of i/o mode (n = 0 to 15) pmdl6 pmdl5 pmdl4 pmdl3 pmdl2 pmdl1 pmdl0 after reset: ffffh r/w address: pmdl fffff024h, pmdll fffff024h, pmdlh fffff025h pmdl15 pmdl (pmdlh note ) pmdl14 pmdl13 pmdl12 pmdl11 pmdl10 pmdl9 pmdl8 8 9 10 11 12 13 14 15 (pmdll) note when reading from or writing to bits 8 to 15 of the pmdl register in 8-bit or 1-bit units, specify these bits as bits 0 to 7 of the pmdlh register. remark the pmdl register can be read or written in 16-bit units. however, when the higher 8 bits and the lowe r 8 bits of the pmdl register are used as the pmdlh register and as the pmdll r egister, respectively, these registers can be read or written in 8-bit or 1-bit units. chapter 4 port functions preliminary user?s manual u17702ej1v0ud 137 (3) port dl mode control register (pmcdl) i/o port adn i/o (address/data bus i/o) pmcdln 0 1 specification of pdln pin operation mode (n = 0 to 15) pmcdl7 pmcdl6 pmcdl5 pmcdl4 pmcdl3 pmcdl2 pmcdl1 pmcdl0 after reset: 0000h r/w address: pmcdl fffff044h, pmcdll fffff044h, pmcdlh fffff045h pmcdl15 pmcdl (pmcdlh note ) pmcdl14 pmcdl13 pmcdl12 pmcdl11pmcdl10 pmcdl9 pmcdl8 8 9 10 11 12 13 14 15 (pmcdll) note when reading from or writing to bits 8 to 15 of the pmcdl register in 8-bit or 1-bit units, specify these bits as bits 0 to 7 of the pmcdlh register. caution when specifying the por t/alternate function for each bi t, pay careful attention to the operation of the alternate functions. remark the pmcdl register can be read or written in 16-bit units. however, when the higher 8 bits and the lo wer 8 bits of the pmcdl register are used as the pmcdlh register and as the pmcdll register, respectively, these registers can be read or written in 8-bit or 1-bit units. (4) pull-up resistor option register dl (pudl) not connected connected pudln 0 1 control of on-chip pull-up resistor connection (n = 0 to 15) pudl7 pudl6 pudl5 pudl4 pudl3 pudl2 pudl1 pudl0 after reset: 0000h r/w address: pudl ffffff44h, pudll ffffff44h, pudlh ffffff45h pudl15 pudl (pudlh note ) pudl14 pudl13 pudl12 pudl11 pudl10 pudl9 pudl8 8 9 10 11 12 13 14 15 (pudll) note when reading from or writing to bits 8 to 15 of the pudl register in 8-bit or 1-bit units, specify these bits as bits 0 to 7 of the pudlh register. remark the pudl register can be read or written in 16-bit units. however, when the higher 8 bits and the lo wer 8 bits of the pudl register are used as the pudlh register and as the pudll r egister, respectively, these registers can be read or written in 8-bit or 1-bit units. chapter 4 port functions preliminary user?s manual u17702ej1v0ud 138 4.4 block diagrams figure 4-2. block diagram of type a-a internal bus rd a/d input signal pmn p-ch n-ch figure 4-3. block diagram of type c-n rd address pmn wr pm pmmn wr port ev dd p-ch medium-voltage input buffer ev ss n-ch output latch (pmn) internal bus selector selector chapter 4 port functions preliminary user?s manual u17702ej1v0ud 139 figure 4-4. block diagram of type c-u wr pm rd wr port pmn pmmn output latch (pmn) address wr pu bv dd pumn p-ch internal bus selector selector chapter 4 port functions preliminary user?s manual u17702ej1v0ud 140 figure 4-5. block diagram of type c-ua wr pm rd address wr port pmn pmmn p-ch n-ch d/a output signal output latch (pmn) wr pu av ref1 pumn p-ch internal bus selector selector dam.dacen bit chapter 4 port functions preliminary user?s manual u17702ej1v0ud 141 figure 4-6. block diagram of type d0-u wr pmc rd address output signal of alternate-function 1 wr port pmn pmcmn wr pu pumn wr pm pmmn ev dd note p-ch output latch (pmn) internal bus selector selector selector note bv dd in the case of pcm1 and pcm2 chapter 4 port functions preliminary user?s manual u17702ej1v0ud 142 figure 4-7. block diagram of type d0-uf wr pmc rd address wr port pmn pmcmn wr pu pumn wr pm pmmn wr pf pfmn ev dd p-ch ev dd ev ss p-ch n-ch output latch (pmn) output signal of alternate-function 1 internal bus selector selector selector chapter 4 port functions preliminary user?s manual u17702ej1v0ud 143 figure 4-8. block diagram of type d0-uz wr pmc rd wr port pmn pmcmn wr pu pumn wr pm address pmmn output latch (pmn) bv dd p-ch internal bus selector selector selector output signal of alternate-function 1 output buffer off signal remark output buffer off signal: signal that is asserted in the idle or stop mode, or when the bus is held. chapter 4 port functions preliminary user?s manual u17702ej1v0ud 144 figure 4-9. block diagram of type d1-suil wr pmc rd address input signal of alternate-function 1 wr port pmn note 2 pmcmn wr intf intfmn note 1 wr pu pumn wr pm pmmn noise elimination edge detection wr intr intrmn note 1 ev dd p-ch output latch (pmn) internal bus selector selector notes 1. refer to 21.4 external interrupt request input pins (nmi, intp0 to intp7 ). 2. there are no hysteresis characteristics in the port mode. chapter 4 port functions preliminary user?s manual u17702ej1v0ud 145 figure 4-10. block diag ram of type d1-sul wr pmc rd address note input signal of alternate-function 1 wr port pmn pmcmn wr pu pumn wr pm pmmn ev dd p-ch output latch (pmn) internal bus selector selector note there are no hysteresis characteristics in the port mode. chapter 4 port functions preliminary user?s manual u17702ej1v0ud 146 figure 4-11. block diagram of type d1-uh wr pmc rd wr port pmn pmcmn wr pu pumn wr pm pmmn bv dd p-ch address output latch (pmn) internal bus selector selector input signal of alternate-function 1 chapter 4 port functions preliminary user?s manual u17702ej1v0ud 147 figure 4-12. block diag ram of type d2-snfh wr pmc rd address output signal of alternate-function 1 input signal of alternate-function 1 wr port pmcmn wr pf pfmn wr pm pmmn pmn ev ss note n-ch output latch (pmn) internal bus selector selector selector note there are no hysteresis characteristics in the port mode. chapter 4 port functions preliminary user?s manual u17702ej1v0ud 148 figure 4-13. block diagram of type d2-sufl wr pmc rd note wr port pmn pmcmn wr pu pumn wr pm pmmn wr pf pfmn ev dd p-ch ev dd ev ss p-ch n-ch address output latch (pmn) internal bus selector selector selector input signal of alternate-function 1 output signal of alternate-function 1 output enable signal of alternate-function 1 note there are no hysteresis characteristics in the port mode. chapter 4 port functions preliminary user?s manual u17702ej1v0ud 149 figure 4-14. block diagram of type d2-ulz wr pmc rd wr port pmn pmcmn wr pm pmmn wr pu pumn bv dd p-ch address output latch (pmn) internal bus selector selector selector output enable signal of alternate-function 1 output signal of alternate-function 1 input enable signal of alternate-function 1 input signal of alternate-function 1 output buffer off signal remark output buffer off signal: signal that is asserted in the idle or stop mode, or when the bus is held. chapter 4 port functions preliminary user?s manual u17702ej1v0ud 150 figure 4-15. block diagram of type e00-suft wr pmc rd address alternate-function input signal in port mode output signal of alternate-function 2 wr port pmn pmcmn wr pfc pfcmn wr pu pumn wr pm pmmn wr pf pfmn ev dd p-ch ev dd ev ss p-ch n-ch output latch (pmn) internal bus selector selector selector selector output signal of alternate-function 1 chapter 4 port functions preliminary user?s manual u17702ej1v0ud 151 figure 4-16. block diagram of type e00-sut wr pmc rd address alternate-function input signal in port mode output signal of alternate-function 2 output signal of alternate-function 1 wr port pmn pmcmn wr pu pumn wr pm pmmn wr pfc pfcmn ev dd p-ch output latch (pmn) internal bus selector selector selector selector chapter 4 port functions preliminary user?s manual u17702ej1v0ud 152 figure 4-17. block diagram of type e00-sutz wr pmc rd address alternate-function input signal in port mode output signal of alternate-function 2 output signal of alternate-function 1 output buffer off signal wr port pmn pmcmn wr pu pumn wr pm pmmn wr pfc pfcmn ev dd p-ch output latch (pmn) internal bus selector selector selector selector remark output buffer off signal: signal that is asserted in the idle or stop mode, or when the bus is held. chapter 4 port functions preliminary user?s manual u17702ej1v0ud 153 figure 4-18. block diagram of type e00-u wr pmc rd wr port pmn pmcmn wr pu pumn wr pm pmmn wr pfc pfcmn ev dd p-ch address output latch (pmn) internal bus selector selector selector selector output signal of alternate-function 2 output signal of alternate-function 1 chapter 4 port functions preliminary user?s manual u17702ej1v0ud 154 figure 4-19. block diag ram of type e00-uf wr pmc rd wr port pmn pmcmn wr pfc pfcmn wr pu pumn wr pm pmmn wr pf pfmn ev dd p-ch ev dd ev ss p-ch n-ch address output latch (pmn) internal bus selector selector selector selector output signal of alternate-function 2 output signal of alternate-function 1 chapter 4 port functions preliminary user?s manual u17702ej1v0ud 155 figure 4-20. block diagram of type e00-ufz wr pmc rd address output signal of alternate-function 2 output signal of alternate-function 1 output buffer off signal wr port pmn pmcmn wr pfc pfcmn wr pu pumn wr pm pmmn wr pf pfmn ev dd p-ch ev dd ev ss p-ch n-ch output latch (pmn) internal bus selector selector selector selector remark output buffer off signal: signal that is asserted in the idle or stop mode, or when the bus is held. chapter 4 port functions preliminary user?s manual u17702ej1v0ud 156 figure 4-21. block diagram of type e01-suhtz wr pmc rd address alternate-function input signal in port mode output signal of alternate-function 1 input signal of alternate-function 2 output buffer off signal wr port pmn pmcmn wr pu pumn wr pm pmmn wr pfc pfcmn ev dd p-ch output latch (pmn) internal bus selector selector selector remark output buffer off signal: signal that is asserted in the idle or stop mode, or when the bus is held. chapter 4 port functions preliminary user?s manual u17702ej1v0ud 157 figure 4-22. block diagram of type e01-suilz wr pmc rd address output signal of alternate-function 1 wr port pmn pmcmn wr pfc pfcmn output buffer off signal wr pu pumn wr pm pmmn wr intf intfmn note 1 wr intr intrmn note 1 ev dd p-ch input signal of alternate-function 2 note 2 noise elimination edge detection output latch (pmn) internal bus selector selector selector notes 1. refer to 21.4 external interrupt request input pins (nmi, intp0 to intp7) . 2. there are no hysteresis characteristics in the port mode. remark output buffer off signal: signal that is asserted in the idle or stop mode, or when the bus is held. chapter 4 port functions preliminary user?s manual u17702ej1v0ud 158 figure 4-23. block diagram of type e01-sulz wr pmc rd address note output signal of alternate-function 1 input signal of alternate-function 2 output buffer off signal wr port pmn pmcmn wr pu pumn wr pm pmmn wr pfc pfcmn ev dd p-ch output latch (pmn) internal bus selector selector selector note there are no hysteresis characteristics in the port mode. remark output buffer off signal: signal that is asserted in the idle or stop mode, or when the bus is held. chapter 4 port functions preliminary user?s manual u17702ej1v0ud 159 figure 4-24. block diagram of type e02-sufh wr pmc rd address output signal of alternate-function 2 input signal of alternate-function 2 output signal of alternate-function 1 wr port pmn pmcmn wr pfc pfcmn wr pu pumn wr pm pmmn wr pf pfmn ev dd p-ch ev dd ev ss note p-ch n-ch output latch (pmn) internal bus selector selector selector selector note there are no hysteresis characteristics in the port mode. chapter 4 port functions preliminary user?s manual u17702ej1v0ud 160 figure 4-25. block diagram of type e02-suflz wr pmc rd address output signal of alternate-function 1 input signal of alternate-function 2 output signal of alternate-function 2 wr port pmn note pmcmn wr pfc pfcmn wr pu pumn wr pm pmmn wr pf pfmn ev dd p-ch ev dd ev ss p-ch n-ch output latch (pmn) output enable signal of alternate-function 2 output buffer off signal internal bus selector selector selector selector note there are no hysteresis characteristics in the port mode. remark output buffer off signal: signal that is asserted in the idle or stop mode, or when the bus is held. chapter 4 port functions preliminary user?s manual u17702ej1v0ud 161 figure 4-26. block diagram of type e10-suihl wr pmc rd wr port pmn note pmcmn wr pfc pfcmn wr pu pumn wr pm pmmn wr intf intfmn note wr intr intrmn note ev dd p-ch address output latch (pmn) internal bus selector selector selector output signal of alternate-function 2 input signal of alternate-function 1-2 input signal of alternate-function 1-1 noise elimination edge detection note there are no hysteresis characteristics in the port mode. remark alternate-function 1-1: rxd0 pin alternate-function 1-2: intp7 pin chapter 4 port functions preliminary user?s manual u17702ej1v0ud 162 figure 4-27. block diagram of type e10-sul wr pmc rd address input signal of alternate-function 1 output signal of alternate-function 2 wr port pmn pmcmn wr pu pumn wr pm pmmn wr pfc pfcmn ev dd p-ch output latch (pmn) internal bus selector selector selector note note there are no hysteresis characteristics in the port mode. chapter 4 port functions preliminary user?s manual u17702ej1v0ud 163 figure 4-28. block diagram of type e10-sult wr pmc rd address alternate-function input signal in port mode input signal of alternate-function 1 output signal of alternate-function 2 wr port pmn pmcmn wr pu pumn wr pm pmmn wr pfc pfcmn ev dd p-ch output latch (pmn) internal bus selector selector selector chapter 4 port functions preliminary user?s manual u17702ej1v0ud 164 figure 4-29. block diagram of type e11-sulh wr pmc rd wr port address pmn pmcmn wr pu pumn wr pm pmmn wr pfc pfcmn ev dd p-ch note output latch (pmn) internal bus selector selector input signal of alternate-function 1 input signal of alternate-function 2 note there are no hysteresis characteristics in the port mode. chapter 4 port functions preliminary user?s manual u17702ej1v0ud 165 figure 4-30. block diag ram of type e12-sufhh wr pmc wr port pmn pmcmn wr pfc pfcmn wr pu pumn wr pm pmmn wr pf pfmn ev dd p-ch ev dd ev ss p-ch n-ch rd address note output latch (pmn) internal bus selector selector selector output signal of alternate-function 2 input signal of alternate-function 1 input signal of alternate-function 2 alternate-function input signal of p40 pin (rxd2) note there are no hysteresis characteristics in the port mode. chapter 4 port functions preliminary user?s manual u17702ej1v0ud 166 figure 4-31. block diagram of type e20-suflt wr pmc rd wr port pmn pmcmn wr pfc pfcmn wr pu pumn wr pm pmmn wr pf pfmn ev dd p-ch ev dd ev ss p-ch n-ch address output latch (pmn) internal bus selector selector selector selector output signal of alternate-function 2 output enable signal of alternate-function 1 output signal of alternate-function 1 input signal of alternate-function 1 alternate-function input signal in port mode chapter 4 port functions preliminary user?s manual u17702ej1v0ud 167 figure 4-32. block diagram of type g1010-sul p-ch wr pmc rd address note input signal of alternate-function 1 input signal of alternate-function 3 output signal of alternate-function 2 output signal of alternate-function 4 wr port pmn pmcmn wr pfce pfcemn wr pm pmmn wr pfc pfcmn wr pu pumn ev dd output latch (pmn) internal bus selector selector selector selector note there are no hysteresis characteristics in the port mode. chapter 4 port functions preliminary user?s manual u17702ej1v0ud 168 figure 4-33. block diagram of type od11-suil wr pmc rd pocres wr port pmn pmcmn wr intf intfmn note 1 wr ocdm ocdm0 wr pm pmmn wr intr intrmn note 1 wr pu pumn ev dd p-ch ev ss n-ch internal bus output latch (pmn) selector selector address note 2 on-chip debug function input signal of alternate-function 1 edge detection noise elimination notes 1. refer to 21.4 external interrupt request pins (nmi, intp0 to intp7). 2. there are no hysteresis characteristics in the port mode. chapter 4 port functions preliminary user?s manual u17702ej1v0ud 169 figure 4-34. block diagram of type oe001-suft wr pmc rd wr port pmn pmcmn wr pfc pfcmn wr ocdm ocdm0 wr pm pmmn wr pf pfmn wr pu pumn ev dd p-ch ev dd ev ss p-ch n-ch alternate-function input signal in port mode output signal of alternate-function 2 output signal of alternate-function 1 drst signal internal bus selector selector selector selector output latch (pmn) address on-chip debug function chapter 4 port functions preliminary user?s manual u17702ej1v0ud 170 figure 4-35. block diagram of type oe001-sut wr pmc rd wr port pmn pmcmn wr ocdm ocdm0 wr pm pmmn wr pfc pfcmn wr pu pumn ev dd p-ch alternate-function input signal in port mode output signal of alternate-function 2 output signal of alternate-function 1 drst signal on-chip debug function address output latch (pmn) selector selector selector selector internal bus chapter 4 port functions preliminary user?s manual u17702ej1v0ud 171 figure 4-36. block diagram of type oe100-sult p-ch wr pmc rd wr port pmn pmcmn wr ocdm ocdm0 wr pm pmmn wr pfc pfcmn wr pu pumn ev dd input signal of alternate-function 1 alternate-function input signal in port mode on-chip debug function output signal of alternate-function 2 output latch (pmn) selector selector selector selector drst signal address internal bus chapter 4 port functions preliminary user?s manual u17702ej1v0ud 172 figure 4-37. block diagram of type oe201-suflt wr pmc rd wr port pmn pmcmn wr pfc pfcmn wr ocdm ocdm0 wr pm pmmn wr pf pfmn wr pu pumn ev dd p-ch ev dd ev ss p-ch n-ch output latch (pmn) selector selector selector selector address internal bus output enable signal of alternate-function 1 output signal of alternate-function 2 output signal of alternate-function 1 drst signal alternate-function input signal in port mode input signal of alternate-function 1 on-chip debug function chapter 4 port functions preliminary user?s manual u17702ej1v0ud 173 4.5 port register setting when alternate function is used table 4-19 shows the port register settings when each port is used for an alternate function. when using a port pin as an alternate-functi on pin, refer to description of each pin. chapter 4 port functions preliminary user?s manual u17702ej1v0ud 174 other bits (registers) ? ? ? ? ? ocdm0 (ocdm) = 0 note 1 ocdm0 (ocdm) = 1 note 1 ? ? ? ? ? ? ? ? ? ? ? pfcnx bit of pfcn register ? ? ? ? ? ? ? ? ? ? pfc30 = 0 pfc30 = 1 note 2 , pfc31 = 0 note 2 , pfc31 = 0 pfc31 = 1 note 3 , pfc32 = 0 note 3 , pfc32 = 0 pfc32 = 1 pfcenx bit of pfcen register ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? pmcnx bit of pmcn register pmc00 = 1 pmc01 = 1 pmc02 = 1 pmc03 = 1 pmc04 = 1 pmc05 = 1 pmc05 = setting not required pmc06 = 1 ? ? pmc30 = 1 pmc30 = 1 pmc31 = 1 pmc31 = 1 pmc31 = 1 pmc32 = 1 pmc32 = 1 pmc32 = 1 pmnx bit of pmn register pm00 = setting not required pm01 = setting not required pm02 = setting not required pm03 = setting not required pm04 = setting not required pm05 = setting not required pm05 = setting not required pm06 = setting not required pm1 register = ffh pm1 register = ffh pm30 = setting not required pm30 = setting not required pm31 = setting not required pm31 = setting not required pm31 = setting not required pm32 = setting not required pm32 = setting not required pm32 = setting not required pnx bit of pn register p00 = setting not required p01 = setting not required p02 = setting not required p03 = setting not required p04 = setting not required p05 = setting not required p05 = setting not required p06 = setting not required p10 = setting not required p11 = setting not required p30 = setting not required p30 = setting not required p31 = setting not required p31 = setting not required p31 = setting not required p32 = setting not required p32 = setting not required p32 = setting not required i/o output output input input input input input input output output output output input input output input input output alternate function function name toh0 toh1 nmi intp0 intp1 intp2 drst note 1 intp3 ano0 ano1 txd0 to02 rxd0 intp7 to03 asck0 adtrg to01 table 4-19. settings when port pins are used for alternate functions (1/8) pin name p00 p01 p02 p03 p04 p05 p06 p10 p11 p30 p31 p32 notes 1. only in the pd70f3734 2. the intp7 and rxd0 pins are alternate-function pins. when usi ng the pin as the rxd0 pin, di sable edge detection of the altern ate-function intp7 pin (clear the intf3.intf31 and intr3.intr31 bits to 0). when using the pin as the intp7 pin, stop the uart0 receive operation (cl ear the asim0.rxe0 bit to 0). 3. the asck0 and adtrg pins are alternate-function pins. when usi ng the pin as the asck0 pin, dis able the trigger input of the a lternate-function adtrg pin (clear the ads.trg bit to 0 or set the ads.adtmd bit to 1). when using the pin as t he adtrg pin, do not set the uart 0 operation cloc k to external input (set the cksr0.tps03 to cksr0.tps00 bits to other than 1011). caution when using the p10 and p11 pins as an alternate function (ano0 and ano1 pins), set the pm1 register to ffh. chapter 4 port functions preliminary user?s manual u17702ej1v0ud 175 other bits (registers) ? ? ? ? ? ? ? ? ? ? pf38 (pf3h) = 1 pf39 (pf3h) = 1 ? ? pf41 (pf4) = don?t care pf41 (pf4) = 0 pf42 (pf4) = don?t care pfcnx bit of pfcn register pfc33 = 0 pfc33 = 1 pfc33 = 0 pfc33 = 1 pfc34 = 0 pfc34 = 1 pfc34 = 0 pfc34 = 1 pfc35 = 0 pfc35 = 1 ? ? pfc40 = 0 pfc40 = 1 pfc41 = 0 pfc41 = 1 ? pfcenx bit of pfcen register pfce33 = 0 pfce33 = 0 pfce33 = 1 pfce33 = 1 pfce34 = 0 pfce34 = 0 pfce34 = 1 pfce34 = 1 ? ? ? ? ? ? ? ? ? pmcnx bit of pmcn register pmc33 = 1 pmc33 = 1 pmc33 = 1 pmc33 = 1 pmc34 = 1 pmc34 = 1 pmc34 = 1 pmc34 = 1 pmc35 = 1 pmc35 = 1 pmc38 = 1 pmc39 = 1 pmc40 = 1 pmc40 = 1 pmc41 = 1 pmc41 = 1 pmc42 = 1 pmnx bit of pmn register pm33 = setting not required pm33 = setting not required pm33 = setting not required pm33 = setting not required pm34 = setting not required pm34 = setting not required pm34 = setting not required pm34 = setting not required pm35 = setting not required pm35 = setting not required pm38 = setting not required pm39 = setting not required pm40 = setting not required pm40 = setting not required pm41 = setting not required pm41 = setting not required pm42 = setting not required pnx bit of pn register p33 = setting not required p33 = setting not required p33 = setting not required p33 = setting not required p34 = setting not required p34 = setting not required p34 = setting not required p34 = setting not required p35 = setting not required p35 = setting not required p38 = setting not required p39 = setting not required p40 = setting not required p40 = setting not required p41 = setting not required p41 = setting not required p42 = setting not required i/o input output input output input output input output input output i/o i/o input input output output i/o alternate function function name ti000 to00 tip00 top00 ti001 to00 tip10 top10 ti010 to01 sda0 scl0 si00 rxd2 note so00 txd2 table 4-19. settings when port pins are used for alternate functions (2/8) pin name p33 p34 p35 p38 p39 p40 p41 p42 note the v850es/kj2 also assigns the rxd2 pin f unction to the p80 pin. if the p40 and p80 pins are used as the rxd2 pin simultaneou sly, the uart2 receive operation may not be performed correctly. t herefore, do not use the p40 and p80 pi ns as the rxd2 pin simultaneously. sck00 chapter 4 port functions preliminary user?s manual u17702ej1v0ud 176 pin name function name i/o alternate function pnx bit of pn register pmnx bit of pmn register pmcnx bit of pmcn register p50 = setting not required p50 = setting not required p50 = setting not required p51 = setting not required p51 = setting not required p51 = setting not required p52 = setting not required p52 = setting not required p52 = setting not required p52 = setting not required p53 = setting not required p53 = setting not required p53 = setting not required p53 = setting not required p54 = setting not required p54 = setting not required p54 = setting not required p54 = setting not required p55 = setting not required p55 = setting not required p55 = setting not required p55 = setting not required pm50 = setting not required pm50 = setting not required pm50 = 1 pm51 = setting not required pm51 = setting not required pm51 = 1 pm52 = setting not required pm52 = setting not required pm52 =1 pm52 = setting not required pm53 = setting not required pm53 = setting not required pm53 = 1 pm53 = setting not required pm54 = setting not required pm54 = setting not required pm54 = 1 pm54 = setting not required pm55 = setting not required pm55 = setting not required pm55 = 1 pm55 = setting not required pmc50 = 1 pmc50 = 1 pmc50 = 1 pmc51 = 1 pmc51 = 1 pmc51 = 0 pmc52 = 1 pmc52 = 1 pmc52 = 0 pmc52 = setting not required pmc53 = 1 pmc53 = 1 pmc53 = 0 pmc53 = setting not required pmc54 = 1 pmc54 = 1 pmc54 = 0 pmc54 = setting not required pmc55 = 1 pmc55 = 1 pmc55 = 0 pmc55 = setting not required pfcnx bit of pfcn register pfc50 = 0 pfc50 = 1 pfc50 = setting not required pfc51 = 0 pfc51 = 1 pfc51 = setting not required pfc52 = 0 pfc52 = 1 pfc52 = setting not required pfc52 = setting not required pfc53 = 0 pfc53 = 1 pfc53 = setting not required pfc53 = setting not required pfc54 = 0 pfc54 = 1 pfc54 = setting not required pfc54 = setting not required pfc55 = 0 pfc55 = 1 pfc55 = setting not required pfc55 = setting not required ti011 rtp00 kr0 t150 rtp01 kr1 to50 rtp02 kr2 ddi note sia0 rtp03 kr3 ddo note soa0 rtp04 kr4 dck note scka0 rtp05 kr5 dms note input output input input output input output output input input input output input output output output input input i/o output input input p50 p51 p52 p53 p54 p55 other bits (registers) ? ? krm0 (krm) = 1 ? ? krm1 (krm) = 1 ocdm0 (ocdm) = 0 note ocdm0 (ocdm) = 0 note krm2 (krm) = 1, ocdm0 (ocdm) = 0 note ocdm0 (ocdm) = 1 note ocdm0 (ocdm) = 0 note ocdm0 (ocdm) = 0 note krm3 (krm) = 1, ocdm0 (ocdm) = 0 note ocdm0 (ocdm) = 1 note pf54 (pf5) = don't care, ocdm0 (ocdm) = 0 note pf54 (pf5) = 0, ocdm0 (ocdm) = 0 note pf54 (pf5) = 0, krm4 (krm) = 1, ocdm0 (ocdm) = 0 note pf54 (pf5) = 0, ocdm0 (ocdm) = 1 note pf55 (pf5) = don't care, ocdm0 (ocdm) = 0 note pf55 (pf5) = 0, ocdm0 (ocdm) = 0 note pf55 (pf5) = 0, krm4 (krm) = 1, ocdm0 (ocdm) = 0 note f55 (pf5) = 0, ocdm0 (ocdm) = 1 note table 4-19. settin g s when port pins are u sed for alternate functions ( 3/8 ) note only in the chapter 4 port functions preliminary user?s manual u17702ej1v0ud 177 other bits (registers) ? ? ? ? ? ? ? pf67 (pf6) = don?t care pf68 (pf6) = don?t care ? ? ? ? ? ? pfcnx bit of pfcn register ? ? ? ? ? ? ? ? ? ? ? ? ? pfc613 = 0 pfc613 = 1 pmcnx bit of pmcn register pmc60 = 1 pmc61 = 1 pmc62 = 1 pmc63 = 1 pmc64 = 1 pmc65 = 1 pmc66 = 1 pmc67 = 1 pmc68 = 1 pmc69 = 1 pmc610 = 1 pmc611 = 1 pmc612 = 1 pmc613 = 1 pmc613 = 1 pmnx bit of pmn register pm60 = setting not required pm61 = setting not required pm62 = setting not required pm63 = setting not required pm64 = setting not required pm65 = setting not required pm66 = setting not required pm67 = setting not required pm68 = setting not required pm69 = setting not required pm610 = setting not required pm611 = setting not required pm612 = setting not required pm613 = setting not required pm613 = setting not required pnx bit of pn register p60 = setting not required p61 = setting not required p62 = setting not required p63 = setting not required p64 = setting not required p65 = setting not required p66 = setting not required p67 = setting not required p68 = setting not required p69 = setting not required p610 = setting not required p611 = setting not required p612 = setting not required p613 = setting not required p613 = setting not required i/o output output output output output output input output i/o input input output input input output alternate function function name rtp10 rtp11 rtp12 rtp13 rtp14 rtp15 si02 so02 sck02 ti040 ti041 to04 ti050 ti051 to05 table 4-19. settings when port pins are used for alternate functions (4/8) pin name p60 p61 p62 p63 p64 p65 p66 p67 p68 p69 p610 p611 p612 p613 chapter 4 port functions preliminary user?s manual u17702ej1v0ud 178 other bits (registers) ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? pf80 (pf8) = 0 pf80 (pf8) = 1 pf81 (pf8) = 0 pf81 (pf8) = 1 pfcnx bit of pfcn register ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? pfc80 = 0 pfc80 = 1 pfc81 = 0 pfc81 = 1 pmcnx bit of pmcn register ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? pmc80 = 1 pmc80 = 1 pmc81 = 1 pmc81 = 1 pmnx bit of pmn register ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? pm80 = setting not required pm80 = setting not required pm81 = setting not required pm81 = setting not required pnx bit of pn register p70 = setting not required p71 = setting not required p72 = setting not required p73 = setting not required p74 = setting not required p75 = setting not required p76 = setting not required p77 = setting not required p78 = setting not required p79 = setting not required p710 = setting not required p711 = setting not required p712 = setting not required p713 = setting not required p714 = setting not required p715 = setting not required p80 = setting not required p80 = setting not required p81 = setting not required p81 = setting not required i/o input input input input input input input input input input input input input input input input input i/o output i/o alternate function function name ani0 ani1 ani2 ani3 ani4 ani5 ani6 ani7 ani8 ani9 ani10 ani11 ani12 ani13 ani14 ani15 rxd2 note sda1 txd2 scl1 table 4-19. settings when port pins are used for alternate functions (5/8) pin name p70 p71 p72 p73 p74 p75 p76 p77 p78 p79 p710 p711 p712 p713 p714 p715 p80 p81 note the v850es/kj2 also assigns the rxd2 pin f unction to the p40 pin. if the p40 and p80 pins are used as the rxd2 pin simultaneou sly, the uart2 receive operation may not be performed correctly. t herefore, do not use the p40 and p80 pi ns as the rxd2 pin simultaneously. chapter 4 port functions preliminary user?s manual u17702ej1v0ud 179 other bits (registers) note ? krm6 (krm) = 1 note ? krm7 (krm) = 1 note ? ? note ? note ? ? note ? note ? ? note ? note , pf98 (pf9) = 0 pf98 (pf9) = don?t care note , pf98 (pf9) = 0 pf98 (pf9) = don?t care pfcnx bit of pfcn register pfcn register pfc90 = 0 pfc90 = 1 pfc90 = setting not required pfc91 = 0 pfc91 = 1 pfc91 = setting not required pfc92 = 0 pfc92 = setting not required pfc92 = 1 pfc93 = 0 pfc93 = 1 pfc94 = 0 pfc94 = setting not required pfc94 = 1 pfc95 = 0 pfc95 = 1 pfc96 = 0 pfc96 = setting not required pfc96 = 1 pfc97 = 0 pfc97 = 1 pfc98 = 0 pfc98 = 1 pfc99 = 0 pfc99 = 1 pmcnx bit of pmcn register pmc90 = 1 pmc90 = 1 pmc90 = 0 pmc91 = 1 pmc91 = 1 pmc91 = 0 pmc92 = 1 pmc92 = 0 pmc92 = 1 pmc93 = 1 pmc93 = 1 pmc94 = 1 pmc94 = 0 pmc94 = 1 pmc95 = 1 pmc95 = 1 pmc96 = 1 pmc96 = 0 pmc96 = 1 pmc97 = 1 pmc97 = 1 pmc98 = 1 pmc98 = 1 pmc99 = 1 pmc99 = 1 pmnx bit of pmn register pm90 = setting not required pm90 = setting not required pm90 = 1 pm91 = setting not required pm91 = setting not required pm91 = 1 pm92 = setting not required pm92 = 1 pm92 = setting not required pm93 = setting not required pm93 = setting not required pm94 = setting not required pm94 = 1 pm94 = setting not required pm95 = setting not required pm95 = setting not required pm96 = setting not required pm96 = 1 pm96 = setting not required pm97 = setting not required pm97 = setting not required pm98 = setting not required pm98 = setting not required pm99 = setting not required pm99 = setting not required pnx bit of pn register p90 = setting not required p90 = setting not required p90 = setting not required p91 = setting not required p91 = setting not required p91 = setting not required p92 = setting not required p92 = setting not required p92 = setting not required p93 = setting not required p93 = setting not required p94 = setting not required p94 = setting not required p94 = setting not required p95 = setting not required p95 = setting not required p96 = setting not required p96 = setting not required p96 = setting not required p97 = setting not required p97 = setting not required p98 = setting not required p98 = setting not required p99 = setting not required p99 = setting not required i/o output output input output input input output input output output input output input output output input output input output output input output output output i/o alternate function function name a0 txd1 kr6 a1 rxd1 kr7 a2 ti020 to02 a3 ti021 a4 ti030 to03 a5 ti031 a6 ti51 to51 a7 si01 a8 so01 a9 sck01 table 4-19. settings when port pins are used for alternate functions (6/8) pin name p90 p91 p92 p93 p94 p95 p96 p97 p98 p99 note when setting the a0 to a15 pins, set the pfc9 register to 0000h and the pm c9 register to ffffh in 16-bit units. chapter 4 port functions preliminary user?s manual u17702ej1v0ud 180 other bits (registers) note ? note , pf911 (pf9) = 0 pf911 (pf9) = don?t care note , pf912 (pf9) = 0 pf912 (pf9) = don?t care note ? note ? note ? ? ? ? ? ? ? ? ? ? ? ? ? pfcnx bit of pfcn register pfc910 = 0 pfc910 = 1 pfc911 = 0 pfc911 = 1 pfc912 = 0 pfc912 = 1 pfc913 = 0 pfc913 = 1 pfc914 = 0 pfc914 = 1 pfc915 = 0 pfc915 = 1 ? ? ? ? ? ? ? ? ? ? ? ? pmcnx bit of pmcn register pmc910 = 1 pmc910 = 1 pmc911 = 1 pmc911 = 1 pmc912 = 1 pmc912 = 1 pmc913 = 1 pmc913 = 1 pmc914 = 1 pmc914 = 1 pmc915 = 1 pmc915 = 1 pmccm0 = 1 pmccm1 = 1 pmccm2 = 1 pmccm3 = 1 pmccs0 = 1 pmccs1 = 1 pmccs2 = 1 pmccs3 = 1 pmcct0 = 1 pmcct1 = 1 pmcct4 = 1 pmcct6 = 1 pmnx bit of pmn register pm910 = setting not required pm910 = setting not required pm911 = setting not required pm911 = setting not required pm912 = setting not required pm912 = setting not required pm913 = setting not required pm913 = setting not required pm914 = setting not required pm914 = setting not required pm915 = setting not required pm915 = setting not required pmcm0 = setting not required pmcm1 = setting not required pmcm2 = setting not required pmcm3 = setting not required pmcs0 = setting not required pmcs1 = setting not required pmcs2 = setting not required pmcs3 = setting not required pmct0 = setting not required pmct1 = setting not required pmct4 = setting not required pmct6 = setting not required pnx bit of pn register p910 = setting not required p910 = setting not required p911 = setting not required p911 = setting not required p912 = setting not required p912 = setting not required p913 = setting not required p913 = setting not required p914 = setting not required p914 = setting not required p915 = setting not required p915 = setting not required pcm0 = setting not required pcm1 = setting not required pcm2 = setting not required pcm3 = setting not required pcs0 = setting not required pcs1 = setting not required pcs2 = setting not required pcs3 = setting not required pct0 = setting not required pct1 = setting not required pct4 = setting not required pct6 = setting not required i/o output input output output output i/o output input output input output input input output output input output output output output output output output output alternate function function name a10 sia1 a11 soa1 a12 scka1 a13 intp4 a14 intp5 a15 intp6 wait clkout hldak hldrq cs0 cs1 cs2 cs3 wr0 wr1 rd astb table 4-19. settings when port pins are used for alternate functions (7/8) pin name p910 p911 p912 p913 p914 p915 pcm0 pcm1 pcm2 pcm3 pcs0 pcs1 pcs2 pcs3 pct0 pct1 pct4 pct6 note when setting the a0 to a15 pins, set the pfc9 register to 0000h and the pm c9 register to ffffh in 16-bit units. chapter 4 port functions preliminary user?s manual u17702ej1v0ud 181 other bits (registers) ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? pfcnx bit of pfcn register ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? pmcnx bit of pmcn register pmcdh0 = 1 pmcdh1 = 1 pmcdh2 = 1 pmcdh3 = 1 pmcdh4 = 1 pmcdh5 = 1 pmcdh6 = 1 pmcdh7 = 1 pmcdl0 = 1 pmcdl1 = 1 pmcdl2 = 1 pmcdl3 = 1 pmcdl4 = 1 pmcdl5 = 1 pmcdl6 = 1 pmcdl7 = 1 pmcdl8 = 1 pmcdl9 = 1 pmcdl10 = 1 pmcdl11 = 1 pmcdl12 = 1 pmcdl13 = 1 pmcdl14 = 1 pmcdl15 = 1 pmnx bit of pmn register pmdh0 = setting not required pmdh1 = setting not required pmdh2 = setting not required pmdh3 = setting not required pmdh4 = setting not required pmdh5 = setting not required pmdh6 = setting not required pmdh7 = setting not required pmdl0 = setting not required pmdl1 = setting not required pmdl2 = setting not required pmdl3 = setting not required pmdl4 = setting not required pmdl5 = setting not required pmdl6 = setting not required pmdl7 = setting not required pmdl8 = setting not required pmdl9 = setting not required pmdl10 = setting not required pmdl11 = setting not required pmdl12 = setting not required pmdl13 = setting not required pmdl14 = setting not required pmdl15 = setting not required pnx bit of pn register pdh0 = setting not required pdh1 = setting not required pdh2 = setting not required pdh3 = setting not required pdh4 = setting not required pdh5 = setting not required pdh6 = setting not required pdh7 = setting not required pdl0 = setting not required pdl1 = setting not required pdl2 = setting not required pdl3 = setting not required pdl4 = setting not required pdl5 = setting not required pdl6 = setting not required pdl7 = setting not required pdl8 = setting not required pdl9 = setting not required pdl10 = setting not required pdl11 = setting not required pdl12 = setting not required pdl13 = setting not required pdl14 = setting not required pdl15 = setting not required i/o output output output output output output output output i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o alternate function function name a16 a17 a18 a19 a20 a21 a22 a23 ad0 ad1 ad2 ad3 ad4 ad5 ad6 ad7 ad8 ad9 ad10 ad11 ad12 ad13 ad14 ad15 table 4-19. settings when port pins are used for alternate functions (8/8) pin name pdh0 pdh1 pdh2 pdh3 pdh4 pdh5 pdh6 pdh7 pdl0 pdl1 pdl2 pdl3 pdl4 pdl5 pdl6 pdl7 pdl8 pdl9 pdl10 pdl11 pdl12 pdl13 pdl14 pdl15 chapter 4 port functions preliminary user?s manual u17702ej1v0ud 182 4.6 cautions 4.6.1 cautions on bit manipulation instruction for port n register (pn) when a 1-bit manipulation instruction is executed on a port that provides both input and output functions, the value of the output latch of an input port that is not subject to manipulation may be written in addition to the targeted bit. therefore, it is recommended to rewr ite the output latch when switching a port from input mode to output mode. chapter 4 port functions preliminary user?s manual u17702ej1v0ud 183 4.6.2 hysteresis characteristics in port mode, the following ports do not have hysteresis characteristics. p02 to p06 p31 to p35, p38, p39 p40, p42 p66, p68 to p610, p612, p613 p80, p81 p93, p95, p97, p99, p910, p912 to p915 4.6.3 cautions on p05 pin the p05 pin has an internal pull-down resistor (30 k ? typ.). after a reset by the reset pin, a pull-down resistor is connected. the pull-down resistor is di sconnected when the ocdm0 bit is cleared (0). (a) pd70f3734 after reset by the reset pin, the p05/intp2/drst pi n is initialized to functi on as an on-chip debug pin (drst). if a high level is input to the drst pin at this time, the on-chip debug mode is set, and the dck, dms, ddi, and ddo pins can be used. the following action must be taken if on-chip debugging is not used. ? clear the ocdm0 bit of the ocdm register (special register) (0) at this time, fix the p05/intp2/drst pin to low level fr om when reset by the reset pin is released until the above action is taken. if a high level is input to the drst pin before the abov e action is taken, it may cause a malfunction (cpu deadlock). handle the p05 pin with the utmost care. caution after reset by the wdtres1 signal or wdtres2 signal, the p05/intp2/drst pin is not initialized to function as an on-chip debug pin (drst). the ocdm register holds the current value. (b) pd70f3733 after reset is released in the pd70f3733, the following operations are r equired before the operation starts. if these operations are omitted, the normal operation cannot be performed. <1> input low level to the p05/intp2 pin. <2> clear (0) the ocdm.ocdm0 bit. fix the p05/intp2 pin to low le vel until step <2> is complete. preliminary user?s manual u17702ej1v0ud 184 chapter 5 bus control function the v850es/kj2 is provided with an extern al bus interface function by which external memories such as rom and ram, and i/o can be connected. 5.1 features { 16-bit data bus { output is selectable from a multiplex bus with a mini mum of 3 bus cycles and a separate bus with a minimum of 2 bus cycles { chip select function for up to 4 spaces { 8-bit/16-bit data bus selectable (for each ar ea selected by chip select function) { wait function ? programmable wait function of up to 7 states (selecta ble for each area selected by chip select function) ? external wait function using wait pin { idle state function { bus hold function { the bus can be controlled using a different voltage from the operating voltage by setting bv dd v dd = ev dd (however, only in multiplex bus mode). { can be connected to the external device with port alternate-function pins. { misalign access possible chapter 5 bus control function preliminary user?s manual u17702ej1v0ud 185 5.2 bus control pins the pins used to connect an external device are listed in the table below. table 5-1. bus control pins (when multiplex bus selected) bus control pin alternate-function pin i/o function register to switch between port mode/ alternate-function mode ad0 to ad15 pdl0 to pdl15 i/o address/data bus pmcdl register a16 to a23 pdh0 to pdh7 output address bus pmcdh register wait pcm0 input external wait control pmccm register clkout pcm1 output internal system clock output pmccm register cs0 to cs3 pcs0 to pcs3 output chip select pmccs register wr0, wr1 pct0, pct1 output write strobe signal pmcct register rd pct4 output read strobe signal pmcct register astb pct6 output address st robe signal pmcct register hldrq pcm3 input hldak pcm2 output bus hold control pmccm register table 5-2. bus control pins (when separate bus selected) bus control pin alternate-function pin i/o function register to switch between port mode/ alternate-function mode ad0 to ad15 pdl0 to pdl15 i/o data bus pmcdl register a0 to a15 p90 to p915 output address bus pmc9 register a16 to a23 pdh0 to pdh7 output address bus pmcdh register wait pcm0 input external wait control pmccm register clkout pcm1 output internal system clock output pmccm register cs0 to cs3 pcs0 to pcs3 output chip select pmccs register wr0, wr1 pct0, pct1 output write strobe signal pmcct register rd pct4 output read strobe signal pmcct register hldrq pcm3 input hldak pcm2 output bus hold control pmccm register chapter 5 bus control function preliminary user?s manual u17702ej1v0ud 186 5.2.1 pin status when intern al rom, internal ram, or on -chip peripheral i/o is accessed when the internal rom, internal ram, or on-chip peripheral i/o are accessed, the status of each pin is as follows. table 5-3. pin statuses when in ternal rom, internal ram, or on -chip peripheral i/o is accessed separate bus mode multiplex bus mode address bus (a23 to a0) undefined a ddress bus (a23 to a16) undefined data bus (ad15 to ad0) hi-z address/data bus (ad15 to ad0) undefined control signal inactive control signal inactive caution when a write access is performed to the inte rnal rom area, address, data, and control signals are activated in the same way as ac cess to the external memory area. 5.2.2 pin status in each operation mode for the pin status of the v850es/kj 2 in each operation mode, refer to 2.2 pin status . chapter 5 bus control function preliminary user?s manual u17702ej1v0ud 187 5.3 memory block function the 64 mb memory space is divided into memory blocks of (lower) 2 mb, 2 mb, 4 mb, and 8 mb. the programmable wait function and bus cycle operation mode for each of these blo cks can be independently controlled in one-block units. figure 5-1. data memory map: physical address 3ffffffh 3fec000h 3febfffh 1000000h 0ffffffh 0800000h 07fffffh 0400000h 03fffffh 0200000h 01fffffh 0000000h 01fffffh 0100000h 00fffffh 3ffd800h note 1 3ffd7ffh 3fff000h 3ffefffh note 1 3ffffffh 0000000h 3fec000h (80 kb) access-prohibited area external memory area (8 mb) internal rom area note 2 (1 mb) external memory area (1 mb) internal ram area (6 kb note 1 ) on-chip peripheral i/o area (4 kb) access-prohibited area external memory area (4 mb) external memory area (2 mb) (2 mb) cs0 cs1 cs2 cs3 notes 1. pd70f3734: 16 kb (3ffb000h to 3ffefffh) 2. this area is an external memory area in the case of a data write access. chapter 5 bus control function preliminary user?s manual u17702ej1v0ud 188 5.3.1 chip select control function of the 64 mb (linear) address space, t he lower 16 mb (0000000h to 0ffffffh) include four chip select control functions, cs0 to cs3. the areas that c an be selected by cs0 to cs3 are fixed. by using these chip select control func tions, the memory space can be used effect ively. the allocation of the chip select areas is shown in the table below. cs0 0000000h to 01fffffh (2 mb) cs1 0200000h to 03fffffh (2 mb) cs2 0400000h to 07fffffh (4 mb) cs3 0800000h to 0ffffffh (8 mb) 5.4 external bus interface mode control function the v850es/kj2 includes the following two external bus interface modes. ? multiplex bus mode ? separate bus mode these two modes can be selected by using the eximc register. (1) external bus interface mode control register (eximc) this register can be read or written in 8-bit or 1-bit units. reset sets this register to 00h. 0 multiplex bus mode separate bus mode smsel 0 1 mode selection eximc 0 0 0 0 0 0 smsel after reset: 00h r/w address: ffffffbeh caution set the eximc register from the internal rom or internal ram area before external access. after setting the eximc register, be sure to set a nop instruction. chapter 5 bus control function preliminary user?s manual u17702ej1v0ud 189 5.5 bus access 5.5.1 number of clocks for access the following table shows the num ber of basic clocks required for accessing each resource. area (bus width) bus cycle type internal rom (32 bits) internal ram (32 bits) external memory (16 bits) on-chip peripheral i/o (16 bits) instruction fetch (normal access) 1 1 note 1 3 + n note 2 ? instruction fetch (branch) 2 2 note 1 3+ n note 2 ? operand data access 3 1 3 +n note 2 3 note 3 notes 1. if the access conflicts with a data access, the number of clock is increased by 1. 2. value when the multiplexed bus is selected. 2 + n clocks (n: number of wait states) when the separate bus mode is selected. 3. this value varies depending on the setting of the vswc register. remark unit: clocks/access 5.5.2 bus size setting function the bus size of each external memory area selected by csn can be set (to 8 bits or 16 bits) by using the bsc register. the external memory area of the v850es/kj2 is selected by cs0 to cs3. (1) bus size configuration register (bsc) this register can be read or written in 16-bit units. reset sets this register to 5555h. caution write to the bsc register after reset, an d then do not change the set values. also, do not access an external memory area until the initial settings of the bsc register are complete. after reset: 5555h r/w address: fffff066h 0 0 bsn0 0 1 8 bits 16 bits bsc 1 bs30 0 0 1 bs20 0 0 1 bs10 0 0 1 bs00 8 9 10 11 12 13 data bus width of csn space (n = 0 to 3) 14 15 1 2 3 4 5 6 7 0 cs0 cs3 csn signal cs2 cs1 caution be sure to set bi ts 14, 12, 10, and 8 to 1, and clear bits 15, 13, 11, 9, 7, 5, 3, and 1 to 0. chapter 5 bus control function preliminary user?s manual u17702ej1v0ud 190 5.5.3 access by bus size the v850es/kj2 accesses the on-chip per ipheral i/o and external memory in 8-bit, 16-bit, or 32-bit units. the bus size is as follows. ? the bus size of the on-chip peripheral i/o is fixed to 16 bits. ? the bus size of the external memory is selectable from 8 bits or 16 bits (by using the bsc register). the operation when each of the above is accessed is described below. all data is accessed starting from the lower side. the v850es/kj2 supports only the little endian format. figure 5-2. little endian address in word 000bh 000ah 0009h 0008h 0007h 0006h 0005h 0004h 0003h 0002h 0001h 0000h 31 24 23 16 15 8 7 0 (1) data space the v850es/kj2 has an address misalign function. with this function, data can be placed at all addresse s, regardless of the format of the data (word data or halfword data). however, if the word data or halfwor d data is not aligned at the boundary, a bus cycle is generated at least twice, causi ng the bus efficiency to drop. (a) halfword-length data access a byte-length bus cycle is generated twice if t he least significant bit of the address is 1. (b) word-length data access (i) a byte-length bus cycle, halfword-length bus cycle, and byte-length bus cycle are generated in that order if the least significant bit of the address is 1. (ii) a halfword-length bus cycle is generated twice if the lower 2 bits of the address are 10. chapter 5 bus control function preliminary user?s manual u17702ej1v0ud 191 (2) byte access (8 bits) (a) 16-bit data bus width <1> access to even address (2n) <2> access to odd address (2n + 1) 7 0 7 0 byte data 15 8 external data bus 2n address 7 0 7 0 15 8 2n + 1 address byte data external data bus (b) 8-bit data bus width <1> access to even address (2n) <2> access to odd address (2n + 1) 7 0 7 0 2n address byte data external data bus 7 0 7 0 2n + 1 address byte data external data bus chapter 5 bus control function preliminary user?s manual u17702ej1v0ud 192 (3) halfword access (16 bits) (a) with 16-bit data bus width <1> access to even address (2n) <2> access to odd address (2n + 1) first access second access 7 0 7 0 15 8 2n address 15 8 2n + 1 halfword data external data bus 7 0 7 0 15 8 15 8 7 0 7 0 15 8 15 8 2n + 2 2n address address 2n + 1 halfword data external data bus halfword data external data bus (b) 8-bit data bus width <1> access to even address (2n) <2> access to odd address (2n + 1) first access second access first access second access 7 0 7 0 15 8 address 7 0 7 0 15 8 2n + 1 address 2n halfword data external data bus halfword data external data bus 7 0 7 0 15 8 7 0 7 0 15 8 2n + 2 2n + 1 address address halfword data external data bus halfword data external data bus chapter 5 bus control function preliminary user?s manual u17702ej1v0ud 193 (4) word access (32 bits) (a) 16-bit data bus width (1/2) <1> access to address (4n) first access second access 7 0 7 0 15 8 4n 15 8 4n + 1 23 16 31 24 7 0 7 0 15 8 4n + 2 15 8 4n + 3 23 16 31 24 word data external data bus address word data external data bus address <2> access to address (4n + 1) first access second access third access 7 0 7 0 15 8 15 8 4n + 1 23 16 31 24 7 0 7 0 15 8 4n + 2 15 8 4n + 3 23 16 31 24 7 0 7 0 15 8 4n + 4 15 8 23 16 31 24 address address address word data external data bus word data external data bus word data external data bus chapter 5 bus control function preliminary user?s manual u17702ej1v0ud 194 (a) 16-bit data bus width (2/2) <3> access to address (4n + 2) first access second access 7 0 7 0 15 8 4n + 2 15 8 4n + 3 23 16 31 24 7 0 7 0 15 8 4n + 4 15 8 4n + 5 23 16 31 24 address address word data external data bus word data external data bus <4> access to address (4n + 3) first access second access third access 7 0 7 0 15 8 15 8 4n + 3 23 16 31 24 7 0 7 0 15 8 4n + 4 15 8 4n + 5 23 16 31 24 7 0 7 0 15 8 4n + 6 15 8 23 16 31 24 address address address word data external data bus word data external data bus word data external data bus chapter 5 bus control function preliminary user?s manual u17702ej1v0ud 195 (b) 8-bit data bus width (1/2) <1> access to address (4n) first access second access third access fourth access 7 0 7 0 15 8 4n 23 16 31 24 7 0 7 0 4n + 1 15 8 23 16 31 24 7 0 7 0 4n + 2 15 8 23 16 31 24 7 0 7 0 4n + 3 15 8 23 16 31 24 word data external data bus address address address address word data external data bus word data external data bus word data external data bus <2> access to address (4n + 1) first access second access third access fourth access 7 0 7 0 15 8 4n + 1 23 16 31 24 7 0 7 0 4n + 2 15 8 23 16 31 24 7 0 7 0 4n + 3 15 8 23 16 31 24 7 0 7 0 4n + 4 15 8 23 16 31 24 address address address address word data external data bus word data external data bus word data external data bus word data external data bus chapter 5 bus control function preliminary user?s manual u17702ej1v0ud 196 (b) 8-bit data bus width (2/2) <3> access to address (4n + 2) first access second access third access fourth access address address address address 7 0 7 0 15 8 4n + 2 23 16 31 24 7 0 7 0 4n + 3 15 8 23 16 31 24 7 0 7 0 4n + 4 15 8 23 16 31 24 7 0 7 0 4n + 5 15 8 23 16 31 24 word data external data bus word data external data bus word data external data bus word data external data bus <4> access to address (4n + 3) first access second access third access fourth access 7 0 7 0 15 8 4n + 3 23 16 31 24 7 0 7 0 4n + 4 15 8 23 16 31 24 7 0 7 0 4n + 5 15 8 23 16 31 24 7 0 7 0 4n + 6 15 8 23 16 31 24 address address address address word data external data bus word data external data bus word data external data bus word data external data bus chapter 5 bus control function preliminary user?s manual u17702ej1v0ud 197 5.6 wait function 5.6.1 programmable wait function (1) data wait control register 0 (dwc0) to realize interfacing with a low-s peed memory or i/o, up to seven data wait states can be inserted in the bus cycle that is executed for each cs space. the number of wait states can be pr ogrammed by using the dw c0 register. immediately after system reset, 7 data wait states are inserted fo r all the chip select areas. the dwc0 register can be read or written in 16-bit units. reset sets this register to 7777h. cautions 1. the internal rom and internal ram ar eas are not subject to programmable wait, and are always accessed without a wait state. the on-chip peripheral i/o area is also not subject to programmable wait, and only wait control from each peripheral function is performed. 2. write to the dwc0 register after reset, an d then do not change the set values. also, do not access an external memory area until the initial settings of the dwc0 register are complete. after reset: 7777h r/w address: fffff484h 0 0 dwn2 0 0 0 0 1 1 1 1 dwn1 0 0 1 1 0 0 1 1 dwn0 0 1 0 1 0 1 0 1 none 1 2 3 4 5 6 7 dwc0 dw32 dw12 dw31 dw11 dw30 dw10 0 0 dw22 dw02 dw21 dw01 dw20 dw00 8 9 10 11 12 13 number of wait states inserted in csn space (n = 0 to 3) 14 15 1 2 3 4 5 6 7 0 cs0 cs3 csn signal csn signal cs2 cs1 caution be sure to clear bi ts 15, 11, 7, and 3 to 0. chapter 5 bus control function preliminary user?s manual u17702ej1v0ud 198 5.6.2 external wait function to synchronize an extremely slow memory, i/o, or a synchronous system, any number of wait states can be inserted in the bus cycle by using the external wait pin (wait). access to each area of the internal rom, internal ram, a nd on-chip peripheral i/o is not subject to control by the external wait function, in the same ma nner as the programmable wait function. the wait signal can be input asynchronously to clkout, and is sampled at the falling edge of the clock in the t2 and tw states of the bus cycle in the multiplex bus mode. in the separate bus mode, it is sampled at the rising edge of the clock immediately after the t1 and tw states of the bus cycle. if the setu p/hold time of the sampling timing is not satisfied, a wait state is inserted in the next state, or not inserted at all. chapter 5 bus control function preliminary user?s manual u17702ej1v0ud 199 5.6.3 relationship between progr ammable wait and external wait wait cycles are inserted as the result of an or operation between the wait cycles specified by the set value of the programmable wait and t he wait cycles controlled by the wait pin. wait control programmable wait wait via wait pin for example, if the timing of the pr ogrammable wait and the wait pin signal is as illustrated below, three wait states will be inserted in the bus cycle. figure 5-3. example of inserting wait states (a) in separate bus mode t1 tw tw tw t2 clkout wait pin wait via wait pin programmable wait wait control remark the circles indicate the sampling timing. (b) in multiplex bus mode clkout t1 t2 tw tw tw t3 wait pin wait via wait pin programmable wait wait control remark the circles indicate the sampling timing. chapter 5 bus control function preliminary user?s manual u17702ej1v0ud 200 5.6.4 programmable address wait function address-setup or address-hold waits to be inserted in each bus cycle can be set by using the awc register. address wait insertion is set for each chip select area (cs0 to cs3). if an address setup wait is inserted, it seems that the high-clock period of t1 state is extended by 1 clock. if an address hold wait is inserted, it s eems that the low-clock period of t1 state is extended by 1 clock. (1) address wait cont rol register (awc) this register can be read or written in 16-bit units. reset sets this register to ffffh. cautions 1. the internal rom, internal ram, and on-chip peripher al i/o areas are not subject to address setup wait or ad dress hold wait insertion. 2. write the awc register after reset, and th en do not change the set values. also, do not access an external memory area until the in itial settings of the awc register are complete. after reset: ffffh r/w address: fffff488h 1 ahw3 ahwn 0 1 not inserted inserted awc 1 asw3 1 ahw2 1 asw2 1 ahw1 1 asw1 1 ahw0 1 asw0 8 9 10 11 12 13 specifies insertion of address hold wait (n = 0 to 3) 14 15 1 2 3 4 5 6 7 0 aswn 0 1 not inserted inserted specifies insertion of address setup wait (n = 0 to 3) cs0 cs3 csn signal cs2 cs1 caution be sure to set bits 15 to 8 to 1. chapter 5 bus control function preliminary user?s manual u17702ej1v0ud 201 5.7 idle state insertion function to facilitate interfacing with low-speed memories, one idle st ate (ti) can be inserted afte r the t3 state in the bus cycle that is executed for each space sele cted by csn in the multiplex address/data bus mode. in the separate bus mode, one idle state (ti) can be inserted a fter the t2 state. by inserting idle st ates, the data output float delay time of the memory can be secured during read access (an id le state cannot be inserted during write access). whether the idle state is to be inserted c an be programmed by using the bcc register. an idle state is inserted for all t he areas immediately after system reset. (1) bus cycle control register (bcc) this register can be read or written in 16-bit units. reset sets this register to aaaah. cautions 1. the internal rom, in ternal ram, and on-chip peripheral i/o areas are not subject to idle state insertion. 2. write to the bcc register after reset, and th en do not change the set values. also, do not access an external memory area until the initial settings of the bcc register are complete. after reset: aaaah r/w address: fffff48ah 1 bc31 bcn1 0 1 not inserted inserted bcc 0 0 1 bc21 0 0 1 bc11 0 0 1 bc01 0 0 8 9 10 11 12 13 specifies insertion of idle state (n = 0 to 3) 14 15 1 2 3 4 5 6 7 0 cs0 cs3 csn signal cs2 cs1 caution be sure to set bits 15, 13, 11 , and 9 to 1, and clear bits 14, 12, 10, 8, 6, 4, 2, and 0 to 0. chapter 5 bus control function preliminary user?s manual u17702ej1v0ud 202 5.8 bus hold function 5.8.1 functional outline the hldrq and hldak functions are valid if the pc m2 and pcm3 pins are set in the control mode. when the hldrq pin is asserted (low level), indicating th at another bus master has re quested bus mastership, the external address/data bus goes into a hi gh-impedance state and is released (bus ho ld status). if the request for the bus mastership is cleared and the hldrq pin is deasserted (high level), driving these pins is started again. during the bus hold period, execution of the program in the internal rom and internal ram is continued until a peripheral i/o register or the ex ternal memory is accessed. the bus hold status is indica ted by assertion (low level) of the hld ak pin. the bus hold function enables the configuration of mult i-processor type systems in which two or more bus masters exist. note that the bus hold request is not acknowledged during a multiple-access cycle initiated by the bus sizing function or a bit manipulation instruction. status data bus width access type timing in which bus hold request not acknowledged word access to even address between first and second access between first and second access word access to odd address between second and third access 16 bits halfword access to odd address between first and second access between first and second access between second and third access word access between third and fourth access cpu bus lock 8 bits halfword access between first and second access read-modify-write access of bit manipulation instruction ? ? between read access and write access chapter 5 bus control function preliminary user?s manual u17702ej1v0ud 203 5.8.2 bus hold procedure the bus hold status transiti on procedure is shown below. <1> low-level input to hldrq pin acknowledged <2> all bus cycle start requests inhibited <3> end of current bus cycle <4> shift to bus idle status. <5> output low level from hldak pin <6> high-level input to hldrq pin acknowledged <7> output high level from hldak pin <8> bus cycle start request inhibition released <9> bus cycle starts normal status bus hold status normal status hldak (output) hldrq (input) <1> <2> <5> <3><4> <7><8><9> <6> 5.8.3 operation in power save mode because the internal system clock is stopped in the st op and idle modes, the bus hold status is not entered even if the hldrq pin is asserted. in the halt mode, the hldak pin is asserted as soon as the hldrq pin has been asserted, and the bus hold status is entered. when the hldrq pin is later deasserted, the hldak pi n is also deasserted, and the bus hold status is cleared. chapter 5 bus control function preliminary user?s manual u17702ej1v0ud 204 5.9 bus priority bus hold, instruction fetch (branch), instruction fetc h (successive), operand data accesses, and dma transfer are executed in the external bus cycle. bus hold has the highest priority, followed by dma trans fer, operand data access, instruction fetch (branch), and instruction fetch (successive). an instruction fetch may be inserted between the read access and write access in a read-modify-write access. if an instruction is executed for two or more accesses, an instruction fetch and bus hold are not inserted between accesses due to bus size limitations. table 5-4. bus priority priority external bus cycle bus master high bus hold external device dma transfer dmac operand data access cpu instruction fetch (branch) cpu low instruction fetch (successive) cpu chapter 5 bus control function preliminary user?s manual u17702ej1v0ud 205 5.10 bus timing figure 5-4. multiplex bus read timi ng (bus size: 16 bits, 16-bit access) a1 a2 a3 d1 d2 a3 a2 a1 t1 t2 t3 t1 t2 tw tw t3 ti t1 programmable wait external wait idle state clkout a23 to a16 astb cs3 to cs0 wait ad15 to ad0 rd 8-bit access ad15 to ad8 ad7 to ad0 odd address active hi-z even address hi-z active remark the broken lines indicate high impedance. figure 5-5. multiplex bus read timing (bus size: 8 bits) a1 a2 a3 d1 d2 a3 a2 a1 t1 t2 t3 t1 t2 tw tw t3 ti t1 programmable wait external wait idle state clkout a23 to a16, ad15 to ad8 astb cs3 to cs0 wait ad7 to ad0 rd remark the broken lines indicate high impedance. chapter 5 bus control function preliminary user?s manual u17702ej1v0ud 206 figure 5-6. multiplex bus write timi ng (bus size: 16 bits, 16-bit access) a1 11 00 11 11 00 11 a2 a3 d1 d2 a3 a2 a1 t2 t3 t1 t1 t2 tw tw t3 t1 programmable wait external wait clkout a23 to a16 astb cs3 to cs0 wait ad15 to ad0 wr1, wr0 wr1, wr0 01 10 8-bit access ad15 to ad8 ad7 to ad0 odd address active undefined even address undefined active figure 5-7. multiplex bus writ e timing (bus size: 8 bits) a1 11 10 11 11 10 11 a2 a3 d1 d2 a3 a2 a1 t2 t3 t1 t1 t2 tw tw t3 t1 programmable wait external wait clkout a23 to a16, ad15 to ad8 astb cs3 to cs0 wait ad7 to ad0 wr1, wr0 chapter 5 bus control function preliminary user?s manual u17702ej1v0ud 207 figure 5-8. multiplex bu s hold timing (bus size : 16 bits, 16-bit access) t1 a1 undefined a1 a2 t2 t3 ti note th th th th ti note t1 t2 t3 d1 clkout hldrq hldak a23 to a16 astb cs3 to cs0 ad15 to ad0 rd undefined undefined undefined a2 d2 1111 1111 note this idle state (ti) does not de pend on the bcc register settings. remarks 1. refer to table 2-2 for the pin statuses in the bus hold mode. 2. the broken lines indicate high impedance. chapter 5 bus control function preliminary user?s manual u17702ej1v0ud 208 figure 5-9. separate bus read timi ng (bus size: 16 bits, 16-bit access) t1 a1 a2 a3 t2 t1 tw tw t2 t2 ti t1 d3 d2 programmable wait external wait idle state d1 clkout a23 to a0 cs3 to cs0 wait ad15 to ad0 rd 8-bit access ad15 to ad8 ad7 to ad0 odd address active hi-z even address hi-z active remark the broken lines indicate high impedance. figure 5-10. separate bus r ead timing (bus size: 8 bits) t1 a1 a2 a3 t2 t1 tw tw t2 t2 ti t1 d3 d2 programmable wait external wait idle state d1 clkout a23 to a0 cs3 to cs0 wait ad7 to ad0 rd remark the broken lines indicate high impedance. chapter 5 bus control function preliminary user?s manual u17702ej1v0ud 209 figure 5-11. separate bus write timi ng (bus size: 16 bits, 16-bit access) t1 a1 11 00 00 00 11 11 11 11 a2 a3 t2 t1 tw tw t2 t1 t2 d3 d2 programmable wait external wait d1 clkout a23 to a0 cs3 to cs0 wait ad15 to ad0 wr1, wr0 wr1, wr0 01 10 8-bit access ad15 to ad8 ad7 to ad0 odd address active undefined even address undefined active remark the broken lines indicate high impedance. figure 5-12. separate bus writ e timing (bus size: 8 bits) t1 a1 a2 a3 t2 t1 tw tw t2 t1 t2 d3 d2 programmable wait external wait d1 clkout a23 to a0 cs3 to cs0 wait ad7 to ad0 wr1, wr0 11 10 10 10 11 11 11 11 remark the broken lines indicate high impedance. chapter 5 bus control function preliminary user?s manual u17702ej1v0ud 210 figure 5-13. separate bus hold ti ming (bus size: 8 bits, write) clkout t1 t2 a1 d1 d2 undefined a2 undefined 11 11 10 d3 a3 t1 t2 th ti note ti note th th th t1 t2 hldrq hldak a23 to a0 ad7 to ad0 wr1, wr0 cs3 to cs0 11 10 11 10 1111 1111 11 note this idle state (ti) does not de pend on the bcc register settings. remark the broken lines indicate high impedance. figure 5-14. address wait timing (separate bus read, bus size: 16 bits, 16-bit access) tasw t1 tahw t2 clkout astb a23 to a0 cs3 to cs0 wait ad15 to ad0 rd d1 a1 t1 t2 clkout astb a23 to a0 cs3 to cs0 wait ad15 to ad0 rd d1 a1 remarks 1. tasw (address setup wait): image of hi gh-level width of t1 state expanded. 2. tahw (address hold wait): image of lo w-level width of t1 state expanded. 3. the broken lines indicate high impedance. chapter 5 bus control function preliminary user?s manual u17702ej1v0ud 211 5.11 cautions with the external bus function, signals may not be outpu t at the correct timing under the following conditions. preliminary user?s manual u17702ej1v0ud 212 chapter 6 clock generation function 6.1 overview the following clock generation functions are available. { main clock oscillator chapter 6 clock generation function preliminary user?s manual u17702ej1v0ud 213 6.2 configuration figure 6-1. clock generator frc bit mck bit ck2 to ck0 bits selpll bit pllon bit cls bit, ck3 bit stop mode subclock oscillator port cm prescaler 1 prescaler 2 idle control halt control halt mode cpu clock watch timer clock watch timer clock, watchdog timer clock peripheral clock, watchdog timer 2 clock watchdog timer 1 clock internal system clock interval timer brg main clock oscillator main clock oscillator stop control xt1 xt2 clkout x1 x2 idle mode idle control idle mode selector pll f xx /32 f xx /16 f xx /8 f xx /4 f xx /2 f xx f cpu f clk f xx to f xx /1024 f brg = f x /2 to f x /2 12 f xt f xt f xx f x f xw idle control idle mode selector selector mfrc bit remark f x : main clock oscillation frequency f xx : main clock frequency f clk : internal system clock frequency f xt : subclock frequency f cpu : cpu clock frequency f brg : watch timer clock frequency f xw : watchdog timer 1 clock frequency chapter 6 clock generation function preliminary user?s manual u17702ej1v0ud 214 (1) main clock oscillator the main clock oscillator oscillates the following frequencies (f x ): ? f x = 2 to 5 mhz (regc = v dd = 4.5 to 5.5 v, in pll mode) ? f x = 2 to 4 mhz (regc = v dd = 4.0 to 5.5 v, in pll mode) ? f x = 2 to 4 mhz (regc = 10 f, v dd = 4.0 to 5.5 v, in pll mode) ? f x = 2 to 2.5 mhz (regc = v dd = 2.7 to 5.5 v, in pll mode) ? f x = 2 to 10 mhz (regc = v dd = 2.7 to 5.5 v, in clock through mode) ? f x = 2 to 10 mhz (regc = 10 f, v dd = 4.0 to 5.5 v, in clock through mode) (2) subclock oscillator the subclock oscillator oscillat es a frequency of 32.768 khz (f xt ). (3) main clock oscillator stop control this circuit generates a control signal that stops oscillation of the main clock oscillator. oscillation of the main clock oscill ator is stopped in the st op mode or when the pcc.mck bit = 1 (valid only when the pcc.cls bit = 1). (4) prescaler 1 this prescaler generates the clock (f xx to f xx /1024) to be supplied to the following on-chip peripheral functions: tmp0, tm00 to tm05, tm50, tm51, tmh0, tmh1, csi00 to csi02, csia0, csia1, uart0 to uart2, i 2 c0, i 2 c1, adc, dac, and wdt2 (5) prescaler 2 this circuit divides the main clock (f xx ). the clock generated by prescaler 2 (f xx to f xx /32) is supplied to the selector that generates the cpu clock (f cpu ) and internal system clock (f clk ). f clk is the clock supplied to the intc, dma controller , rom, and ram blocks, and can be output from the clkout pin. (6) interval timer brg this circuit divides the clock (f x ) generated by the main clock oscillator to a specific frequency (32.768 khz) and supplies that clock to the watch timer block. for details, refer to chapter 11 interval timer, watch timer . (7) pll this circuit multiplies the clock (f x ) generated by the main clock oscillator. it operates in two modes: clock-through mode in which f x is output as is, and pll mode in which a multiplied clock is output. these modes can be sele cted by using the pllctl.selpll bit. operation of the pll c an be started or stopped by the pllctl.pllon bit. chapter 6 clock generation function preliminary user?s manual u17702ej1v0ud 215 6.3 registers (1) processor clock control register (pcc) the pcc register is a special register. data can be wr itten to this register only in combination of specific sequences (refer to 3.4.7 special registers ). this register can be read or written in 8-bit or 1-bit units. reset sets this register to 03h. (1/2) frc used not used frc 0 1 use of subclock on-chip feedback resistor pcc mck mfrc cls note ck3 ck2 ck1 ck0 oscillation enabled oscillation stopped mck 0 1 control of main clock oscillator used not used mfrc 0 1 use of main clock on-chip feedback resistor after reset: 03h r/w after reset: fffff828h main clock operation subclock operation cls note 0 1 status of cpu clock (f cpu ) even if the mck bit is set to 1 while the system is operating with the main clock as the cpu clock, the operation of the main clock does not stop. it stops after the cpu clock has been changed to the subclock. when the main clock is stopped and the device is operating on the subclock, clear the mck bit to 0 and wait until the oscillation stabilization time has been secured by the program before switching back to the main clock. < > < > < > note the cls bit is a read-only bit. chapter 6 clock generation function preliminary user?s manual u17702ej1v0ud 216 (2/2) f xx f xx /2 f xx /4 f xx /8 (default value) f xx /16 f xx /32 setting prohibited f xt ck2 0 0 0 0 1 1 1 clock selection (f clk /f cpu ) ck1 0 0 1 1 0 0 1 ck0 0 1 0 1 0 1 ck3 0 0 0 0 0 0 0 1 cautions 1. do not change the cpu clock (by using the ck3 to ck0 bits) while clkout is being output. 2. use a bit manipulation instruction to ma nipulate the ck3 bit. when using an 8-bit manipulation instruction, do not change the set values of the ck2 to ck0 bits. 3. when the cpu operates on the subclock and no clock is input to the x1 pin, do not access a register in which a wait occurs (refer to 3.4.8 (1) (b) a ccess to special on-chip peripheral i/o register for details of the access methods). if a wait occurs, it can only be released by a reset. remark : don?t care chapter 6 clock generation function preliminary user?s manual u17702ej1v0ud 217 (a) example of setting main clock operation subclock operation <1> ck3 bit 1: use of a bit manipulation instructi on is recommended. do not change the ck2 to ck0 bits. <2> subclock operation: read the cls bit to check if subclock operation has started. it takes the following time after the ck3 bit is se t until subclock operation is started. max.: 1/f xt (1/subclock frequency) <3> mck bit 1: set the mck bit to 1 only when stopping the main clock. cautions 1. when stopping th e main clock, stop the pll. 2. if the following conditions are not satisfi ed, change the ck2 to ck0 bits so that the conditions are satisfied, then change to the subclock operation mode. internal system clock (f clk ) > subclock (f xt : 32.768 khz) 4 remark internal system clock (f clk ): clock generated from the main clock (f xx ) by setting bits ck2 to ck0 [description example] <1> _set_sub_run : st.b r0, prcmd[r0] set1 3, pcc[r0] -- ck3 bit 1 <2> _check_cls : tst1 4, pcc[r0] -- wait until subclock operation starts. bz _check_cls <3> _stop_main_clock : st.b r0, prcmd[r0] set1 6, pcc[r0] -- mck bit 1, main clock is stopped remark the above description is an exampl e. note with caution that t he cls bit is read in a closed loop in <2>. chapter 6 clock generation function preliminary user?s manual u17702ej1v0ud 218 (b) example of setting subclock operation main clock operation <1> mck bit 0: main clock starts oscillating <2> insert waits by the program and wait until the oscillation stabilizat ion time of the main clock elapses. <3> ck3 bit 0: use of a bit manipulation instruct ion is recommended. do not change the ck2 to ck0 bits. <4> main clock operation: it takes the following time after the ck3 bit is set until main clock operation is started. max.: 1/f xt (1/subclock frequency) therefore, insert one nop instructi on immediately after setting the ck3 bit to 0 or read the cls bit to check if main clock operation has started. [description example] <1> _start_main_osc : st.b r0, prcmd[r0] -- release of protection of special registers clr1 6, pcc[r0] -- main clock starts oscillating <2> movea 0x55, r0, r11 -- wait for oscillation stabilization time _wait_ost : nop nop nop addi -1, r11, r11 mp r0, r11 bne _program_wait <3> st.b r0, prcmd[r0] clr1 3, pcc[r0] -- ck3 0 <4> _check_cls : tst1 4, pcc[r0] -- wait until main clock operation starts bnz _check_cls remark the above description is an exampl e. note with caution that t he cls bit is read in a closed loop in <4>. chapter 6 clock generation function preliminary user?s manual u17702ej1v0ud 219 6.4 operation 6.4.1 operation of each clock the following table shows the oper ation status of each clock. table 6-1. operation status of each clock pcc register cls bit = 0, mck bit = 0 cls bit = 1, mck bit = 0 cls bit = 1, mck bit = 1 register setting and operation status target clock during reset during oscillation stabilization time count halt mode idle mode stop mode subclock mode sub-idle mode subclock mode sub-idle mode main clock oscillator (f x ) { { { { { subclock oscillator (f xt ) { { { { { { { { { cpu clock (f cpu ) { { internal system clock (f clk ) { { { peripheral clock (f xx to f xx /1024) { { wt clock (main) { { { { { wt clock (sub) { { { { { { { { { wdt1 clock (f xw ) { { { { { wdt2 clock (main) { { wdt2 clock (sub) { { { { { { { { { remark o: operable : stopped 6.4.2 clock output function the clock output function is used to output the internal system clock (f clk ) from the clkout pin. the internal system clock (f clk ) is selected by using the pcc.ck3 to pcc.ck0 bits. the clkout pin functions alte rnately as the pcm1 pin and functions as a clock output pin if so specified by the control register of port cm. the status of the clko ut pin is the same as the in ternal system clock in table 6-1 and the pin can output the clock when it is in the operable status. it outputs a low level in the stopped status. however, the port mode (pcm1: input mode) is selected until the clkout pin output is set after reset. cons equently, the clkout pin goes into a high-impedance state. 6.4.3 external clock input function an external clock can be direct ly input to the oscillator. input the clock to the x1 pin and its inverse signal to the x2 pin. set the pcc.mfrc bit to 1 (on-chip feedback resistor not used). note, however, that oscillation stabilization time is inserted even in the external clock mode. connect v dd directly to the regc pin. chapter 6 clock generation function preliminary user?s manual u17702ej1v0ud 220 6.5 pll function 6.5.1 overview the pll function is used to output t he operating clock of the cpu and on-chip peripheral function at a frequency 4 times higher than the oscillation frequen cy, and select the clock-through mode. when pll function is used: input clock = 2 to 5 mhz (f xx : 8 to 20 mhz) clock-through mode: input clock = 2 to 10 mhz (f xx : 2 to 10 mhz) 6.5.2 register (1) pll control register (pllctl) the pllctl register is an 8-bit register that controls the security function of pll and rto. this register can be read or written in 8-bit or 1-bit units. reset sets this register to 01h. 0 pllctl 0 0 0 rtost1 note rtost0 note selpll pllon pll stopped pll operating pllon 0 1 pll operation control clock-through operation pll operation selpll 0 1 pll clock selection after reset: 01h r/w address: fffff806h < > < > < > < > note for the rtost1 and rtost0 bits, refer to chapter 13 real-time output function (rto) . caution be sure to clea r bits 4 to 7 to 0. chapter 6 clock generation function preliminary user?s manual u17702ej1v0ud 221 6.5.3 usage (1) when pll is used ? after reset has been released, the pll operates (pll ctl.pllon bit = 1), but because the default mode is the clock-through mode (pllctl.selpll bit = 0), select the pll mode (selpll bit = 1). ? to set the stop mode in which the main clock is stoppe d, or to set the idle mode, first select the clock- through mode and then stop the pll. to return from the idle or stop mode, first enable pll operation (pllon bit = 1), and then select the pll mode (selpll bit = 1). ? to enable the pll operation, first se t the pllon bit to 1, wait for 200 s, and then set the selpll bit to 1. to stop the pll, first select the clock-through mode (selpll bit = 0), wait for 8 clocks or more, and then stop the pll (pllon bit = 0). (2) when pll is not used ? the clock-through mode (selpll bit = 0) is select ed after reset has been released, but the pll is operating (pllon bit = 1) and must t herefore be stopped (pllon bit = 0). remark the pll is operable in the idle mode. to realiz e low power consumption, stop the pll. be sure to stop the pll when shifting to the stop mode. preliminary user?s manual u17702ej1v0ud 222 chapter 7 16-bit timer/event counter p (tmp) timer p (tmp) is a 16-bit timer/event counter. 7.1 overview an outline of tmp0 is shown below. ? clock selection: 8 ways ? capture trigger input pins: 2 ? external event count input pins: 1 ? external trigger input pins: 1 ? timer/counters: 1 ? capture/compare registers: 2 ? capture/compare match interrupt request signals: 2 ? timer output pins: 2 7.2 functions tmp0 has the following functions. ? interval timer ? external event counter ? external trigger pulse output ? one-shot pulse output ? pwm output ? free-running timer ? pulse width measurement chapter 7 16-bit timer/event counter p (tmp) preliminary user?s manual u17702ej1v0ud 223 7.3 configuration tmp0 includes the following hardware. table 7-1. configuration of tmp0 item configuration timer register 16-bit counter registers tmp0 capture/compare registers 0, 1 (tp0ccr0, tp0ccr1) tmp0 counter read buffer register (tp0cnt) ccr0, ccr1 buffer registers timer inputs 2 (tip00 note , tip01 pins) timer outputs 2 (top00, top01 pins) control registers tmp0 control registers 0, 1 (tp0ctl0, tp0ctl1) tmp0 i/o control registers 0 to 2 (tp0ioc0 to tp0ioc2) tmp0 option register 0 (tp0opt0) note the tip00 pin functions alternat ely as a capture trigger input signal, external event count input signal, and external trigger input signal. figure 7-1. block diagram of tmp0 f xx f xx /2 f xx /4 f xx /8 f xx /16 f xx /32 f xx /64 f xx /128 selector internal bus internal bus top00 top01 tip00 tip01 selector ccr0 buffer register ccr1 buffer register tp0ccr0 tp0ccr1 16-bit counter tp0cnt inttp0ov inttp0cc0 inttp0cc1 output controller clear edge detector edge detector digital noise eliminator remark f xx : main clock frequency chapter 7 16-bit timer/event counter p (tmp) preliminary user?s manual u17702ej1v0ud 224 (1) 16-bit counter this 16-bit counter can count inte rnal clocks or external events. the count value of this counter can be read by using the tp0cnt register. when the tp0ctl0.tp0ce bit = 0, the va lue of the 16-bit counter is ffffh. if the tp0cnt register is read at this time, 0000h is read. reset sets the tp0ce bit to 0. therefor e, the 16-bit counter is set to ffffh. (2) ccr0 buffer register this is a 16-bit compare register that com pares the count value of the 16-bit counter. when the tp0ccr0 register is used as a compare regist er, the value written to the tp0ccr0 register is transferred to the ccr0 buffer register. when the count value of the 16-bit counter matches the value of the ccr0 buffer register, a compare match interrupt request signal (inttp0cc0) is generated. the ccr0 buffer register cannot be read or written directly. the ccr0 buffer register is cleared to 0000h after reset, as the tp0ccr0 register is cleared to 0000h. (3) ccr1 buffer register this is a 16-bit compare register that com pares the count value of the 16-bit counter. when the tp0ccr1 register is used as a compare regist er, the value written to the tp0ccr1 register is transferred to the ccr1 buffer register. when the count value of the 16-bit counter matches the value of the ccr1 buffer register, a compare match interrupt request signal (inttp0cc1) is generated. the ccr1 buffer register cannot be read or written directly. the ccr1 buffer register is cleared to 0000h after reset, as the tp0ccr1 register is cleared to 0000h. (4) edge detector this circuit detects the valid edges input to the tip00 and tip01 pins. no edge, rising edge, falling edge, or both the rising and falling edges can be selected as the valid edge by using the tp0ioc1 and tp0ioc2 registers. (5) output controller this circuit controls the output of the top00 and top0 1 pins. the output contro ller is controlled by the tp0ioc0 register. (6) selector this selector selects the count clock for the 16-bit counter . eight types of internal clocks or an external event can be selected as the count clock. (7) digital noise eliminator this circuit is valid only when the tip0a pi n is used as a capture trigger input pin. this circuit is controlled by the tip0a noise elimination register (panfc). remark a = 0, 1 chapter 7 16-bit timer/event counter p (tmp) preliminary user?s manual u17702ej1v0ud 225 7.4 registers (1) tmp0 control re gister 0 (tp0ctl0) the tp0ctl0 register is an 8-bit register that controls the operation of tmp0. this register can be read or written in 8-bit or 1-bit units. reset sets this register to 00h. the same value can always be written to the tp0ctl0 register by software. tp0ce tmp0 operation disabled (tmp0 reset asynchronously note ). tmp0 operation enabled. tmp0 operation started. tp0ce 0 1 tmp0 operation control tp0ctl0 0 0 0 0 tp0cks2 tp0cks1 tp0cks0 654321 after reset: 00h r/w address: fffff5a0h <7> 0 f xx f xx /2 f xx /4 f xx /8 f xx /16 f xx /32 f xx /64 f xx /128 tp0cks2 0 0 0 0 1 1 1 1 internal count clock selection tp0cks1 0 0 1 1 0 0 1 1 tp0cks0 0 1 0 1 0 1 0 1 note tp0opt0.tp0ovf bit, 16-bit counter , timer output (top00, top01 pins) cautions 1. set the tp0cks2 to tp0 cks0 bits when the tp0ce bit = 0. when the value of the tp0ce bi t is changed from 0 to 1, the tp0cks2 to tp0cks0 bits can be set simultaneously. 2. be sure to clear bits 3 to 6 to 0. remark f xx : main clock frequency chapter 7 16-bit timer/event counter p (tmp) preliminary user?s manual u17702ej1v0ud 226 (2) tmp0 control re gister 1 (tp0ctl1) the tp0ctl1 register is an 8-bit register that controls the operation of tmp0. this register can be read or written in 8-bit or 1-bit units. reset sets this register to 00h. 0 tp0est 0 1 software trigger control tp0ctl1 tp0est tp0eee 0 0 tp0md2 tp0md1 tp0md0 <6> <5> 4 3 2 1 after reset: 00h r/w address: fffff5a1h generate a valid signal for external trigger input. ? in one-shot pulse output mode: a one-shot pulse is output with writing 1 to the tp0est bit as the trigger. ? in external trigger pulse output mode: a pwm waveform is output with writing 1 to the tp0est bit as the trigger. disable operation with external event count input. (perform counting with the count clock selected by the tp0ctl0.tp0ck0 to tp0ctl0.tp0ck2 bits.) tp0eee 0 1 count clock selection the tp0eee bit selects whether counting is performed with the internal count clock or the valid edge of the external event count input. 7 0 interval timer mode external event count mode external trigger pulse output mode one-shot pulse output mode pwm output mode free-running timer mode pulse width measurement mode setting prohibited tp0md2 0 0 0 0 1 1 1 1 timer mode selection tp0md1 0 0 1 1 0 0 1 1 tp0md0 0 1 0 1 0 1 0 1 enable operation with external event count input. (perform counting at the valid edge of the external event count input signal.) ? cautions 1. the tp0est bit is valid only in the external trigger pulse output mode or one-shot pulse output mode . in any other mode, writing 1 to this bit is ignored. 2. external event count input is selected in the external event count mode regardless of the value of the tp0eee bit. 3. set the tp0eee and tp0md2 to tp0md0 bits when the tp0ctl0.tp0ce bit = 0. (the sam e value can be written when the tp0ce bit = 1.) the operation is not guaranteed when rewriting is performed with the tp0ce bit = 1. if rewriting was mistakenly performed, clear the tp0ce bit to 0 and then set the bits again. 4. be sure to clear bits 3, 4, and 7 to 0. chapter 7 16-bit timer/event counter p (tmp) preliminary user?s manual u17702ej1v0ud 227 (3) tmp0 i/o control register 0 (tp0ioc0) the tp0ioc0 register is an 8-bit register that controls the timer output (top00, top01 pins). this register can be read or written in 8-bit or 1-bit units. reset sets this register to 00h. 0 tp0ol1 0 1 top01 pin output level setting top01 pin output inversion disabled top01 pin output inversion enabled tp0ioc0 0 0 0 tp0ol1 tp0oe1 tp0ol0 tp0oe0 6543<2>1 after reset: 00h r/w address: fffff5a2h tp0oe1 0 1 top01 pin output setting timer output disabled ? when tp0ol1 bit = 0: low level is output from the top01 pin ? when tp0ol1 bit = 1: high level is output from the top01 pin tp0ol0 0 1 top00 pin output level setting top00 pin output inversion disabled top00 pin output inversion enabled tp0oe0 0 1 top00 pin output setting timer output disabled ? when tp0ol0 bit = 0: low level is output from the top00 pin ? when tp0ol0 bit = 1: high level is output from the top00 pin 7 <0> timer output enabled (a square wave is output from the top01 pin). timer output enabled (a square wave is output from the top00 pin). cautions 1. rewrite the tp0ol1, tp0oe1, tp0ol0, and tp0oe0 bits when the tp0ctl0.tp0ce bit = 0. (the same value can be written when the tp0ce bit = 1.) if rewriting was mistakenly performed, clear the tp0ce bit to 0 and then set the bits again. 2. even if the tp0ola bit is manipulated when the tp0ce and tp0oea bits are 0, the top0a pin output level varies (a = 0, 1). chapter 7 16-bit timer/event counter p (tmp) preliminary user?s manual u17702ej1v0ud 228 (4) tmp0 i/o control register 1 (tp0ioc1) the tp0ioc1 register is an 8-bit regist er that controls the valid edge of the capture trig ger input signals (tip00, tip01 pins). this register can be read or written in 8-bit units. reset sets this register to 00h. 0 tp0is3 0 0 1 1 tp0is2 0 1 0 1 capture trigger input signal (tip01 pin) valid edge setting no edge detection (capture operation invalid) detection of rising edge detection of falling edge detection of both edges tp0ioc1 0 0 0 tp0is3 tp0is2 tp0is1 tp0is0 654321 after reset: 00h r/w address: fffff5a3h tp0is1 0 0 1 1 tp0is0 0 1 0 1 capture trigger input signal (tip00 pin) valid edge setting no edge detection (capture operation invalid) detection of rising edge detection of falling edge detection of both edges 7 0 cautions 1. rewrite the tp0is3 to tp0is0 bits when the tp0ctl0.tp0ce bit = 0. (the same value can be written when the tp0ce bit = 1.) if rewriting was mistakenly performed, clear the tp0ce bit to 0 and then set the bits again. 2. the tp0is3 to tp0is0 bi ts are valid only in the free- running timer mode and the pulse width measurement mode. in all other modes, a capture operation is not possible. chapter 7 16-bit timer/event counter p (tmp) preliminary user?s manual u17702ej1v0ud 229 (5) tmp0 i/o control register 2 (tp0ioc2) the tp0ioc2 register is an 8-bit register that controls the valid edge of the external event count input signal (tip00 pin) and external trigger input signal (tip00 pin). this register can be read or written in 8-bit or 1-bit units. reset sets this register to 00h. 0 tp0ees1 0 0 1 1 tp0ees0 0 1 0 1 external event count input signal (tip00 pin) valid edge setting no edge detection (external event count invalid) detection of rising edge detection of falling edge detection of both edges tp0ioc2 0 0 0 tp0ees1 tp0ees0 tp0ets1 tp0ets0 654321 after reset: 00h r/w address: fffff5a4h tp0ets1 0 0 1 1 tp0ets0 0 1 0 1 external trigger input signal (tip00 pin) valid edge setting no edge detection (external trigger invalid) detection of rising edge detection of falling edge detection of both edges 7 0 cautions 1. rewrite the tp0ees1, tp0ees0, tp0ets1, and tp0ets0 bits when the tp0ctl0.tp0ce bit = 0. (the same value can be written when the tp0ce bit = 1.) if rewriting was mistakenly performed, clear the tp0ce bit to 0 and then set the bits again. 2. the tp0ees1 and tp0ees0 bi ts are valid only when the tp0ctl1.tp0eee bit = 1 or when the external event count mode (tp0ctl1.tp0md2 to tp0ctl1.tp0md0 bits = 001) has been set. 3. the tp0ets1 and tp0ets0 bi ts are valid only when the external trigger pulse output mode (tp0md2 to tp0md0 bits = 010) or the one-shot pu lse output mode (tp0md2 to tp0md0 bits = 011) is set. chapter 7 16-bit timer/event counter p (tmp) preliminary user?s manual u17702ej1v0ud 230 (6) tmp0 option register 0 (tp0opt0) the tp0opt0 register is an 8-bit register used to set the capture/compare operation and detect an overflow. this register can be read or written in 8-bit or 1-bit units. reset sets this register to 00h. 0 tp0ccs1 0 1 tp0ccr1 register capture/compare selection the tp0ccs1 bit setting is valid only in the free-running timer mode. compare register selected capture register selected tp0opt0 0 tp0ccs1 tp0ccs0 0 0 0 tp0ovf 654321 after reset: 00h r/w address: fffff5a5h tp0ccs0 0 1 tp0ccr0 register capture/compare selection the tp0ccs0 bit setting is valid only in the free-running timer mode. compare register selected capture register selected tp0ovf set (1) reset (0) tmp0 overflow detection flag the tp0ovf bit is reset when the 16-bit counter count value overflows from ffffh to 0000h in the free-running timer mode or the pulse width measurement mode. an interrupt request signal (inttp0ov) is generated at the same time that the tp0ovf bit is set to 1. the inttp0ov signal is not generated in modes other than the free-running timer mode and the pulse width measurement mode. the tp0ovf bit is not cleared even when the tp0ovf bit or the tp0opt0 register are read when the tp0ovf bit = 1. the tp0ovf bit can be both read and written, but the tp0ovf bit cannot be set to 1 by software. writing 1 has no influence on the operation of tmp0. overflow occurred tp0ovf bit 0 written or tp0ctl0.tp0ce bit = 0 7 <0> cautions 1. rewrite the tp0ccs1 and tp0ccs0 bits when the tp0ce bit = 0. (the same value can be written when the tp0ce bit = 1.) if rewriting was mi stakenly performed, clear the tp0ce bit to 0 and then set the bits again. 2. be sure to clear bits 1 to 3, 6, and 7 to 0. chapter 7 16-bit timer/event counter p (tmp) preliminary user?s manual u17702ej1v0ud 231 (7) tmp0 capture/compare register 0 (tp0ccr0) the tp0ccr0 register can be used as a capture register or a com pare register depending on the mode. this register can be used as a capture register or a compare register only in the free-running timer mode, depending on the setting of the tp0opt0.tp0ccs0 bit. in the pulse width measurement mode, the tp0ccr0 register can be used only as a capt ure register. in any other mode, this register can be used only as a compare register. the tp0ccr0 register can be r ead or written during operation. this register can be read or written in 16-bit units. reset sets this register to 0000h. caution accessing the tp0ccr0 register is disable d during subclock operation with the main clock stopped. for details, refer to 3.4.8 (1) (b). tp0ccr0 12 10 8 6 4 2 after reset: 0000h r/w address: fffff5a6h 14 0 13 11 9 7 5 3 15 1 chapter 7 16-bit timer/event counter p (tmp) preliminary user?s manual u17702ej1v0ud 232 (a) function as compare register the tp0ccr0 register can be rewritten even when the tp0ctl0.tp0ce bit = 1. the set value of the tp0ccr0 register is transferred to the ccr0 buffer register. when the value of the 16-bit counter matches the value of the ccr0 buffer register, a compare match interrupt request signal (inttp0cc0) is generated. if top00 pin output is ena bled at this time, the output of the top00 pin is inverted. when the tp0ccr0 register is used as a cycle register in the interval timer mode, external event count mode, external trigger pulse output mode, one-shot pulse output mode, or pwm output mode, the value of the 16-bit counter is cleared (0000h) if its count va lue matches the value of the ccr0 buffer register. (b) function as capture register when the tp0ccr0 register is used as a capture regi ster in the free-running timer mode, the count value of the 16-bit counter is stored in the tp0ccr0 register if the valid ed ge of the capture trigger input pin (tip00 pin) is detected. in the pulse width measur ement mode, the count value of the 16-bit counter is stored in the tp0ccr0 register and the 16-bit counter is cleared (0000h) if the valid edge of the capture trigger input pin (tip00 pin) is detected. even if the capture operation and reading the tp0 ccr0 register conflict, the correct value of the tp0ccr0 register can be read. the following table shows the functions of the capture/compare re gister in each mode, and how to write data to the compare register. table 7-2. function of capture/co mpare register in each mode a nd how to write compare register operation mode capture/compare register how to write compare register interval timer compare register anytime write external event counter compare register anytime write external trigger pulse output compare register batch write one-shot pulse output compare register anytime write pwm output compare register batch write free-running timer capture/compare register anytime write pulse width measurement capture register ? chapter 7 16-bit timer/event counter p (tmp) preliminary user?s manual u17702ej1v0ud 233 (8) tmp0 capture/compare register 1 (tp0ccr1) the tp0ccr1 register can be used as a capture register or a com pare register depending on the mode. this register can be used as a capture register or a compare register only in the free-running timer mode, depending on the setting of the tp0opt0.tp0ccs1 bit. in the pulse width measurement mode, the tp0ccr1 register can be used only as a capt ure register. in any other mode, this register can be used only as a compare register. the tp0ccr1 register can be r ead or written during operation. this register can be read or written in 16-bit units. reset sets this register to 0000h. caution accessing the tp0ccr1 register is disable d during subclock operation with the main clock stopped. for details, refer to 3.4.8 (1) (b). tp0ccr1 12 10 8 6 4 2 after reset: 0000h r/w address: fffff5a8h 14 0 13 11 9 7 5 3 15 1 chapter 7 16-bit timer/event counter p (tmp) preliminary user?s manual u17702ej1v0ud 234 (a) function as compare register the tp0ccr1 register can be rewritten even when the tp0ctl0.tp0ce bit = 1. the set value of the tp0ccr1 register is transferred to the ccr1 buffer register. when the value of the 16-bit counter matches the value of the ccr1 buffer register, a compare match interrupt request signal (inttp0cc1) is generated. if top01 pin output is ena bled at this time, the output of the top01 pin is inverted. (b) function as capture register when the tp0ccr1 register is used as a capture regi ster in the free-running timer mode, the count value of the 16-bit counter is stored in the tp0ccr1 register if the valid ed ge of the capture trigger input pin (tip01 pin) is detected. in the pulse width measur ement mode, the count value of the 16-bit counter is stored in the tp0ccr1 register and the 16-bit counter is cleared (0000h) if the valid edge of the capture trigger input pin (tip01 pin) is detected. even if the capture operation and reading the tp0 ccr1 register conflict, the correct value of the tp0ccr1 register can be read. the following table shows the functions of the capture/compare re gister in each mode, and how to write data to the compare register. table 7-3. function of capture/co mpare register in each mode a nd how to write compare register operation mode capture/compare register how to write compare register interval timer compare register anytime write external event counter compare register anytime write external trigger pulse output compare register batch write one-shot pulse output compare register anytime write pwm output compare register batch write free-running timer capture/compare register anytime write pulse width measurement capture register ? chapter 7 16-bit timer/event counter p (tmp) preliminary user?s manual u17702ej1v0ud 235 (9) tmp0 counter read buffer register (tp0cnt) the tp0cnt register is a read buffer register that can read the count va lue of the 16-bit counter. if this register is read when the tp0ctl0.tp0ce bit = 1, the count value of the 16-bit timer can be read. this register is read-only, in 16-bit units. the value of the tp0cnt register is cleared to 0000h wh en the tp0ce bit = 0. if t he tp0cnt register is read at this time, the value of the 16-bit count er (ffffh) is not read, but 0000h is read. the value of the tp0cnt register is cleared to 000 0h after reset, as the tp0ce bit is cleared to 0. caution accessing the tp0cnt register is disabl ed during subclock operation with the main clock stopped. for details, refer to 3.4.8 (1) (b). tp0cnt 12 10 8 6 4 2 after reset: 0000h r address: fffff5aah 14 0 13 11 9 7 5 3 15 1 chapter 7 16-bit timer/event counter p (tmp) preliminary user?s manual u17702ej1v0ud 236 7.5 operation tmp0 can perform the following operations. operation tp0ctl1.tp0est bit (software trigger bit) tip00 pin (external trigger input) capture/compare register setting compare register write interval timer mode invalid invalid compare only anytime write external event count mode note 1 invalid invalid compare only anytime write external trigger pulse output mode note 2 valid valid compare only batch write one-shot pulse output mode note 2 valid valid compare only anytime write pwm output mode invalid invalid compare only batch write free-running timer mode invalid invalid switching enabled anytime write pulse width measurement mode note 2 invalid invalid capture only not applicable notes 1. to use the external event count mode, specify that t he valid edge of the tip00 pin capture trigger input is not detected (by clearing the tp0ioc1.tp0i s1 and tp0ioc1.tp0is0 bits to ?00?). 2. when using the external trigger pulse output m ode, one-shot pulse output mode, and pulse width measurement mode, select the internal clock as the count clock (by clearing the tp0ctl1.tp0eee bit to 0). chapter 7 16-bit timer/event counter p (tmp) preliminary user?s manual u17702ej1v0ud 237 7.5.1 interval timer mode (t p0md2 to tp0md0 bits = 000) in the interval timer mode, an interrupt request signal (inttp0cc0) is generated at t he specified interval if the tp0ctl0.tp0ce bit is set to 1. a square wave whose hal f cycle is equal to the interval can be output from the top00 pin. usually, the tp0ccr1 register is not used in the interval timer mode. figure 7-2. configuration of interval timer 16-bit counter output controller ccr0 buffer register tp0ce bit tp0ccr0 register count clock selection clear match signal top00 pin inttp0cc0 signal figure 7-3. basic timing of operation in interval timer mode ffffh 16-bit counter 0000h tp0ce bit tp0ccr0 register top00 pin output inttp0cc0 signal d 0 d 0 d 0 d 0 d 0 interval (d 0 + 1) interval (d 0 + 1) interval (d 0 + 1) interval (d 0 + 1) chapter 7 16-bit timer/event counter p (tmp) preliminary user?s manual u17702ej1v0ud 238 when the tp0ce bit is set to 1, the va lue of the 16-bit counter is cleared fr om ffffh to 0000h in synchronization with the count clock, and t he counter starts counting. at this time, the out put of the top00 pin is inverted. additionally, the set value of the tp0ccr0 register is transferred to the ccr0 buffer register. when the count value of the 16-bit counter matches the valu e of the ccr0 buffer register, the 16-bit counter is cleared to 0000h, the output of the top00 pin is in verted, and a compare match interrupt request signal (inttp0cc0) is generated. the interval can be calculated by the following expression. interval = (set value of tp0ccr0 register + 1) count clock cycle figure 7-4. register setting for in terval timer mode operation (1/2) (a) tmp0 control re gister 0 (tp0ctl0) 0/1 0 0 0 0 tp0ctl0 select count clock 0: stop counting 1: enable counting 0/1 0/1 0/1 tp0cks2 tp0cks1 tp0cks0 tp0ce (b) tmp0 control register 1 (tp0ctl1) 0 0 0/1 note 00 tp0ctl1 0, 0, 0: interval timer mode 0: operate on count clock selected by tp0cks0 to tp0cks2 bits 1: count with external event count input signal 000 tp0md2 tp0md1 tp0md0 tp0eee tp0est (c) tmp0 i/o control register 0 (tp0ioc0) 0 0 0 0 0/1 tp0ioc0 0: disable top00 pin output 1: enable top00 pin output setting of output level with operation of top00 pin disabled 0: low level 1: high level 0: disable top01 pin output 1: enable top01 pin output setting of output level with operation of top01 pin disabled 0: low level 1: high level 0/1 0/1 0/1 tp0oe1 tp0ol0 tp0oe0 tp0ol1 note this bit can be set to 1 only when the interrupt request signals (inttp0cc0 and inttp0cc1) are masked by the interrupt mask flags (tp0ccmk0 and tp0ccmk1) and timer output (top01) is performed at the same time. however, set the tp0ccr0 and tp0ccr1 registers to the same value (refer to 7.5.1 (2) (d) operation of tp0ccr1 register ). chapter 7 16-bit timer/event counter p (tmp) preliminary user?s manual u17702ej1v0ud 239 figure 7-4. register setting for in terval timer mode operation (2/2) (d) tmp0 counter read buffer register (tp0cnt) by reading the tp0cnt register, the count va lue of the 16-bit counter can be read. (e) tmp0 capture/compare register 0 (tp0ccr0) if the tp0ccr0 register is set to d 0 , the interval is as follows. interval = (d 0 + 1) count clock cycle (f) tmp0 capture/compare register 1 (tp0ccr1) usually, the tp0ccr1 register is not used in the inte rval timer mode. however, the set value of the tp0ccr1 register is transferred to the ccr1 buffer register. a compare match interrupt request signal (inttp0cc1) is generated when the count value of th e 16-bit counter matches the value of the ccr1 buffer register. therefore, mask the interrupt request by using the corresponding interrupt mask flag (tp0ccmk1). remark tmp0 i/o control register 1 (tp0ioc1), tm p0 i/o control register 2 (tp0ioc2), and tmp0 option register 0 (tp0opt0) are usually not used in the interval timer mode. however, set the tp0ioc2 register to use the external event count input. chapter 7 16-bit timer/event counter p (tmp) preliminary user?s manual u17702ej1v0ud 240 (1) interval timer mode operation flow figure 7-5. software processing flow in interval timer mode ffffh 16-bit counter 0000h tp0ce bit tp0ccr0 register top00 pin output inttp0cc0 signal d 0 d 0 d 0 d 0 <1> <2> tp0ce bit = 1 tp0ce bit = 0 register initial setting tp0ctl0 register (tp0cks0 to tp0cks2 bits) tp0ctl1 register, tp0ioc0 register, tp0ccr0 register initial setting of these registers is performed before setting the tp0ce bit to 1. the tp0cks0 to tp0cks2 bits can be set at the same time when counting has been started (tp0ce bit = 1). the counter is initialized and counting is stopped by clearing the tp0ce bit to 0. start stop <1> count operation start flow <2> count operation stop flow chapter 7 16-bit timer/event counter p (tmp) preliminary user?s manual u17702ej1v0ud 241 (2) interval timer mode operation timing (a) operation if tp0ccr0 register is cleared to 0000h if the tp0ccr0 register is cleared to 0000h, the inttp 0cc0 signal is generated at each count clock, and the output of the top00 pin is inverted. the value of the 16-bit counter is always 0000h. count clock 16-bit counter tp0ce bit tp0ccr0 register top00 pin output inttp0cc0 signal 0000h interval time count clock cycle interval time count clock cycle interval time count clock cycle ffffh 0000h 0000h 0000h 0000h chapter 7 16-bit timer/event counter p (tmp) preliminary user?s manual u17702ej1v0ud 242 (b) operation if tp0ccr0 register is set to ffffh if the tp0ccr0 register is set to ffffh, the 16-bit co unter counts up to ffffh. t he counter is cleared to 0000h in synchronization with the next count-up timing. the inttp0cc0 signal is generated and the output of the top00 pin is inverted. at this time, an overflow interrupt request signal (inttp0ov) is not generated, nor is the overflow flag (tp0opt0.tp0ovf bit) set to 1. ffffh 16-bit counter 0000h tp0ce bit tp0ccr0 register top00 pin output inttp0cc0 signal ffffh interval time 10000h count clock cycle interval time 10000h count clock cycle interval time 10000h count clock cycle chapter 7 16-bit timer/event counter p (tmp) preliminary user?s manual u17702ej1v0ud 243 (c) notes on rewriting tp0ccr0 register to change the value of the tp0ccr0 register to a smaller value, stop counting once and then change the set value. if the value of the tp0ccr0 register is rewritten to a smaller value during counting, the 16-bit counter may overflow. ffffh 16-bit counter 0000h tp0ce bit tp0ccr0 register tp0ol0 bit top00 pin output inttp0cc0 signal d 1 d 2 d 1 d 1 d 2 d 2 d 2 l interval time (1) interval time (ng) interval time (2) remark interval time (1): (d 1 + 1) count clock cycle interval time (ng): (10000h + d 2 + 1) count clock cycle interval time (2): (d 2 + 1) count clock cycle if the value of the tp0ccr0 register is changed from d 1 to d 2 while the count value is greater than d 2 but less than d 1 , the count value is transferred to the ccr0 buffer register as soon as the tp0ccr0 register has been rewritten. consequently, the value of the 16-bit counter that is compared is d 2 . because the count value has already exceeded d 2 , however, the 16-bit c ounter counts up to ffffh, overflows, and then counts up again from 0000h. when the count value matches d 2 , the inttp0cc0 signal is generated and the output of the top00 pin is inverted. therefore, the inttp0cc0 signal may not be generated at the interval time ?(d 1 + 1) count clock cycle? or ?(d 2 + 1) count clock cycle? originally expected, but may be generated at an interval of ?(10000h + d 2 + 1) count clock period?. chapter 7 16-bit timer/event counter p (tmp) preliminary user?s manual u17702ej1v0ud 244 (d) operation of tp0ccr1 register figure 7-6. configuration of tp0ccr1 register ccr0 buffer register tp0ccr0 register tp0ccr1 register ccr1 buffer register top00 pin inttp0cc0 signal top01 pin inttp0cc1 signal 16-bit counter output controller tp0ce bit count clock selection clear match signal output controller match signal chapter 7 16-bit timer/event counter p (tmp) preliminary user?s manual u17702ej1v0ud 245 if the set value of the tp0ccr1 register is less than the set value of the tp0ccr0 register, the inttp0cc1 signal is generated once per cycle. at the same time, the output of t he top01 pin is inverted. the top01 pin outputs a square wave with the sa me cycle as that output by the top00 pin. figure 7-7. timing chart when d 01 d 11 ffffh 16-bit counter 0000h tp0ce bit tp0ccr0 register top00 pin output inttp0cc0 signal tp0ccr1 register top01 pin output inttp0cc1 signal d 01 d 11 d 01 d 11 d 11 d 11 d 11 d 01 d 01 d 01 chapter 7 16-bit timer/event counter p (tmp) preliminary user?s manual u17702ej1v0ud 246 if the set value of the tp0ccr1 register is greater than the set value of the tp0ccr0 register, the count value of the 16-bit counter does not match the va lue of the tp0ccr1 register. consequently, the inttp0cc1 signal is not generated, nor is the output of the top01 pin changed. figure 7-8. timing chart when d 01 < d 11 ffffh 16-bit counter 0000h tp0ce bit tp0ccr0 register top00 pin output inttp0cc0 signal tp0ccr1 register top01 pin output inttp0cc1 signal d 01 d 11 d 01 d 01 d 01 d 01 l chapter 7 16-bit timer/event counter p (tmp) preliminary user?s manual u17702ej1v0ud 247 7.5.2 external event count mode (tp0md2 to tp0md0 bits = 001) in the external event count mode, the valid edge of the external event count input is counted when the tp0ctl0.tp0ce bit is set to 1, and an interrupt request si gnal (inttp0cc0) is generated each time the specified number of edges have been counted. the time r output (top00, top01 pins) cannot be used. usually, the tp0ccr1 register is not us ed in the external event count mode. figure 7-9. configuration in external event count mode 16-bit counter ccr0 buffer register tp0ce bit tp0ccr0 register edge detector clear match signal inttp0cc0 signal tip00 pin (external event count input) figure 7-10. basic timing in external event count mode ffffh 16-bit counter 0000h tp0ce bit tp0ccr0 register inttp0cc0 signal d 0 d 0 d 0 d 0 16-bit counter tp0ccr0 register inttp0cc0 signal external event count input (tip00 pin input) d 0 external event count interval (d 0 + 1) d 0 ? 1d 0 0000 0001 external event count interval (d 0 + 1) external event count interval (d 0 + 1) remark this figure shows the basic timing when the rising edge is specified as the valid edge of the external event count input. chapter 7 16-bit timer/event counter p (tmp) preliminary user?s manual u17702ej1v0ud 248 when the tp0ce bit is set to 1, the value of the 16-bit counter is clea red from ffffh to 0000h. the counter counts each time the valid edge of external event count input is detected. additionally, the set value of the tp0ccr0 register is transferred to the ccr0 buffer register. when the count value of the 16-bit counter matches the valu e of the ccr0 buffer register, the 16-bit counter is cleared to 0000h, and a compare match interrupt request signal (inttp0cc0) is generated. the inttp0cc0 signal is generated each time the valid e dge of the external event count input has been detected (set value of tp0ccr0 register + 1) times. figure 7-11. register setting for operati on in external event count mode (1/2) (a) tmp0 control re gister 0 (tp0ctl0) 0/1 0 0 0 0 tp0ctl0 0: stop counting 1: enable counting 000 tp0cks2 tp0cks1 tp0cks0 tp0ce (b) tmp0 control register 1 (tp0ctl1) 00000 tp0ctl1 0, 0, 1: external event count mode 001 tp0md2 tp0md1 tp0md0 tp0eee tp0est (c) tmp0 i/o control register 0 (tp0ioc0) 00000 tp0ioc0 0: disable top00 pin output 0: disable top01 pin output 000 tp0oe1 tp0ol0 tp0oe0 tp0ol1 (d) tmp0 i/o control register 2 (tp0ioc2) 0 0 0 0 0/1 tp0ioc2 select valid edge of external event count input 0/1 0 0 tp0ees0 tp0ets1 tp0ets0 tp0ees1 chapter 7 16-bit timer/event counter p (tmp) preliminary user?s manual u17702ej1v0ud 249 figure 7-11. register setting for operati on in external event count mode (2/2) (e) tmp0 counter read buffer register (tp0cnt) the count value of the 16-bit counter can be read by reading the tp0cnt register. (f) tmp0 capture/compare register 0 (tp0ccr0) if d 0 is set to the tp0ccr0 register, the counter is cleared and a compare match interrupt request signal (inttp0cc0) is generated when the nu mber of external event counts reaches (d 0 + 1). (g) tmp0 capture/compare register 1 (tp0ccr1) usually, the tp0ccr1 register is not used in the exte rnal event count mode. however, the set value of the tp0ccr1 register is transferred to the ccr1 buff er register. when the count value of the 16-bit counter matches the value of the ccr1 buffer re gister, a compare match interrupt request signal (inttp0cc1) is generated. therefore, mask the interrupt signal by using the interrupt mask flag (tp0ccmk1). remark tmp0 i/o control register 1 (tp0ioc1) and tmp0 option register 0 (tp0opt0) are not used in the external event count mode. chapter 7 16-bit timer/event counter p (tmp) preliminary user?s manual u17702ej1v0ud 250 (1) external event count mode operation flow figure 7-12. flow of software processing in external event count mode ffffh 16-bit counter 0000h tp0ce bit tp0ccr0 register inttp0cc0 signal d 0 d 0 d 0 d 0 <1> <2> tp0ce bit = 1 tp0ce bit = 0 register initial setting tp0ctl0 register (tp0cks0 to tp0cks2 bits) tp0ctl1 register, tp0ioc0 register, tp0ioc2 register, tp0ccr0 register initial setting of these registers is performed before setting the tp0ce bit to 1. the tp0cks0 to tp0cks2 bits can be set at the same time when counting has been started (tp0ce bit = 1). the counter is initialized and counting is stopped by clearing the tp0ce bit to 0. start stop <1> count operation start flow <2> count operation stop flow chapter 7 16-bit timer/event counter p (tmp) preliminary user?s manual u17702ej1v0ud 251 (2) operation timing in external event count mode cautions 1. in the external even t count mode, do not set the tp0 ccr0 and tp0ccr1 registers to 0000h. 2. in the external event count mode, use of the timer output is disabled. if performing timer output using external event co unt input, set the interval timer mode, and select the operation enabled by the external even t count input for the count clock (tp0ctl1.tp0md2 to tp0ctl1.tp0md0 bits = 000, tp0ctl1.tp0eee bit = 1). (a) operation if tp0ccr0 register is set to ffffh if the tp0ccr0 register is set to ffffh, the 16-bit co unter counts to ffffh each time the valid edge of the external event count signal has been detected. the 16-bit counter is cleared to 0000h in synchronization with the next count-up timing, and the inttp0cc0 signal is generated. at this time, the tp0opt0.tp0ovf bit is not set. ffffh 16-bit counter 0000h tp0ce bit tp0ccr0 register inttp0cc0 signal ffffh external event count signal interval external event count signal interval external event count signal interval chapter 7 16-bit timer/event counter p (tmp) preliminary user?s manual u17702ej1v0ud 252 (b) notes on rewriting the tp0ccr0 register to change the value of the tp0ccr0 register to a smaller value, stop counting once and then change the set value. if the value of the tp0ccr0 register is rewritten to a smaller value during counting, the 16-bit counter may overflow. ffffh 16-bit counter 0000h tp0ce bit tp0ccr0 register inttp0cc0 signal d 1 d 2 d 1 d 1 d 2 d 2 d 2 external event count signal interval (1) (d 1 + 1) external event count signal interval (ng) (10000h + d 2 + 1) external event count signal interval (2) (d 2 + 1) if the value of the tp0ccr0 register is changed from d 1 to d 2 while the count value is greater than d 2 but less than d 1 , the count value is transferred to the ccr0 buffer register as soon as the tp0ccr0 register has been rewritten. consequently, the value t hat is compared with the 16-bit counter is d 2 . because the count value has already exceeded d 2 , however, the 16-bit c ounter counts up to ffffh, overflows, and then counts up again from 0000h. when the count value matches d 2 , the inttp0cc0 signal is generated. therefore, the inttp0cc0 signal may not be generated at the va lid edge count of ?(d 1 + 1) times? or ?(d 2 + 1) times? originally expected, but may be generated at the valid edge count of ?(10000h + d 2 + 1) times?. chapter 7 16-bit timer/event counter p (tmp) preliminary user?s manual u17702ej1v0ud 253 (c) operation of tp0ccr1 register figure 7-13. configuration of tp0ccr1 register ccr0 buffer register tp0ce bit tp0ccr0 register 16-bit counter tp0ccr1 register ccr1 buffer register clear match signal match signal inttp0cc0 signal inttp0cc1 signal edge detector tip00 pin if the set value of the tp0ccr1 register is smalle r than the set value of the tp0ccr0 register, the inttp0cc1 signal is generated once per cycle. figure 7-14. timing chart when d 01 d 11 ffffh 16-bit counter 0000h tp0ce bit tp0ccr0 register inttp0cc0 signal tp0ccr1 register inttp0cc1 signal d 01 d 11 d 01 d 11 d 11 d 11 d 11 d 01 d 01 d 01 chapter 7 16-bit timer/event counter p (tmp) preliminary user?s manual u17702ej1v0ud 254 if the set value of the tp0ccr1 register is greater than the set value of the tp0ccr0 register, the inttp0cc1 signal is not generated because the count va lue of the 16-bit counte r and the value of the tp0ccr1 register do not match. figure 7-15. timing chart when d 01 < d 11 ffffh 16-bit counter 0000h tp0ce bit tp0ccr0 register inttp0cc0 signal tp0ccr1 register inttp0cc1 signal d 01 d 11 d 01 d 01 d 01 d 01 l chapter 7 16-bit timer/event counter p (tmp) preliminary user?s manual u17702ej1v0ud 255 7.5.3 external trigger pulse output mode (tp0md2 to tp0md0 bits = 010) in the external trigger pulse output mode, 16-bit timer/event counter p waits for a trigger when the tp0ctl0.tp0ce bit is set to 1. when the valid edge of an ex ternal trigger input signal is detected, 16-bit timer/event counter p starts counting, and outputs a pwm waveform from the top01 pin. pulses can also be output by generating a software trigger instead of using the external trigger. when using a software trigger, a square wave that has one cycle of the pwm waveform as half its cycle can also be output from the top00 pin. figure 7-16. configuration in external trigger pulse output mode ccr0 buffer register tp0ce bit tp0ccr0 register 16-bit counter tp0ccr1 register ccr1 buffer register clear match signal match signal inttp0cc0 signal output controller (rs-ff) output controller top01 pin inttp0cc1 signal top00 pin count clock selection count start control edge detector software trigger generation tip00 pin transfer transfer s r chapter 7 16-bit timer/event counter p (tmp) preliminary user?s manual u17702ej1v0ud 256 figure 7-17. basic timing in exte rnal trigger pulse output mode external trigger input (tip00 pin input) top00 pin output (software trigger) d 1 d 0 d 0 d 1 d 1 d 1 d 1 d 0 d 0 d 0 wait for trigger active level width (d 1 ) cycle (d 0 + 1) cycle (d 0 + 1) cycle (d 0 + 1) active level width (d 1 ) active level width (d 1 ) ffffh 16-bit counter 0000h tp0ce bit tp0ccr0 register inttp0cc0 signal tp0ccr1 register inttp0cc1 signal top01 pin output 16-bit timer/event counter p waits for a trigger when the tp0c e bit is set to 1. when the trigger is generated, the 16-bit counter is cleared from ffffh to 0000h, starts count ing at the same time, and out puts a pwm waveform from the top01 pin. if the trigger is generated again while the counter is operating, the counter is cleared to 0000h and restarted. (the output of th e top00 pin is inverted. the top01 pin outputs a high leve l regardless of the status (high/low) when a trigger occurs.) the active level width, cycle, and duty factor of the pwm waveform can be calculated as follows. active level width = (set value of tp0ccr1 register) count clock cycle cycle = (set value of tp0ccr0 register + 1) count clock cycle duty factor = (set value of tp0ccr1 regist er)/(set value of tp0ccr0 register + 1) the compare match interrupt request signal inttp0cc0 is generated when the 16-bit counter counts next time after its count value matches the value of the ccr0 buffer register, and the 16-bit counter is cleared to 0000h. the compare match interrupt request signal inttp0cc1 is gener ated when the count value of the 16-bit counter matches the value of the ccr1 buffer register. the value set to the tp0ccra register is transferred to t he ccra buffer register when the count value of the 16-bit counter matches the value of the ccra buffer regi ster and the 16-bit counter is cleared to 0000h. the valid edge of an external trigger input signal, or setti ng the software trigger (tp0ctl1.tp0est bit) to 1 is used as the trigger. remark a = 0, 1 chapter 7 16-bit timer/event counter p (tmp) preliminary user?s manual u17702ej1v0ud 257 figure 7-18. setting of registers in exte rnal trigger pulse output mode (1/2) (a) tmp0 control re gister 0 (tp0ctl0) 0/1 0 0 0 0 tp0ctl0 select count clock note 0: stop counting 1: enable counting 0/1 0/1 0/1 tp0cks2 tp0cks1 tp0cks0 tp0ce note the setting is invalid when the tp0ctl1.tp0eee bit = 1. (b) tmp0 control register 1 (tp0ctl1) 0 0/1 0/1 0 0 tp0ctl1 0: operate on count clock selected by tp0cks0 to tp0cks2 bits 1: count with external event input signal generate software trigger when 1 is written 010 tp0md2 tp0md1 tp0md0 tp0eee tp0est 0, 1, 0: external trigger pulse output mode (c) tmp0 i/o control register 0 (tp0ioc0) 0 0 0 0 0/1 tp0ioc0 0: disable top00 pin output 1: enable top00 pin output settings of output level while operation of top00 pin is disabled 0: low level 1: high level 0: disable top01 pin output 1: enable top01 pin output specifies active level of top01 pin output 0: active-high 1: active-low 0/1 0/1 0/1 tp0oe1 tp0ol0 tp0oe0 tp0ol1 top01 pin output 16-bit counter ? when tp0ol1 bit = 0 top01 pin output 16-bit counter ? when tp0ol1 bit = 1 chapter 7 16-bit timer/event counter p (tmp) preliminary user?s manual u17702ej1v0ud 258 figure 7-18. setting of registers in exte rnal trigger pulse output mode (2/2) (d) tmp0 i/o control register 2 (tp0ioc2) 0 0 0 0 0/1 tp0ioc2 select valid edge of external trigger input select valid edge of external event count input 0/1 0/1 0/1 tp0ees0 tp0ets1 tp0ets0 tp0ees1 (e) tmp0 counter read buffer register (tp0cnt) the value of the 16-bit counter can be read by reading the tp0cnt register. (f) tmp0 capture/compare register s 0 and 1 (tp0ccr0 and tp0ccr1) if d 0 is set to the tp0ccr0 register and d 1 to the tp0ccr1 register, the cycle and active level of the pwm waveform are as follows. cycle = (d 0 + 1) count clock cycle active level width = d 1 count clock cycle remark tmp0 i/o control register 1 (tp0ioc1) and tm p0 option register 0 (tp0opt0) are not used in the external trigger pulse output mode. chapter 7 16-bit timer/event counter p (tmp) preliminary user?s manual u17702ej1v0ud 259 (1) operation flow in extern al trigger pulse output mode figure 7-19. software processing flow in ex ternal trigger pulse output mode (1/2) ffffh 16-bit counter 0000h tp0ce bit tp0ccr0 register ccr0 buffer register inttp0cc0 signal tp0ccr1 register ccr1 buffer register inttp0cc1 signal top01 pin output external trigger input (tip00 pin input) top00 pin output (software trigger) d 10 d 00 d 00 d 01 d 00 d 00 d 10 d 10 d 11 d 10 d 10 d 10 d 11 d 10 d 01 d 00 d 10 d 10 d 00 d 10 d 00 d 11 d 11 d 01 d 01 d 01 <1> <2> <3> <4> <5> chapter 7 16-bit timer/event counter p (tmp) preliminary user?s manual u17702ej1v0ud 260 figure 7-19. software processing flow in ex ternal trigger pulse output mode (2/2) tp0ce bit = 1 setting of tp0ccr0 register register initial setting tp0ctl0 register (tp0cks0 to tp0cks2 bits) tp0ctl1 register, tp0ioc0 register, tp0ioc2 register, tp0ccr0 register, tp0ccr1 register initial setting of these registers is performed before setting the tp0ce bit to 1. the tp0cks0 to tp0cks2 bits can be set at the same time when counting is enabled (tp0ce bit = 1). trigger wait status tp0ccr1 register write processing is necessary only when the set cycle is changed. when the counter is cleared after setting, the value of the tp0ccra register is transferred to the ccra buffer register. start setting of tp0ccr1 register <1> count operation start flow <2> tp0ccr0 and tp0ccr1 register setting change flow setting of tp0ccr0 register when the counter is cleared after setting, the value of the tp0ccra register is transferred to the ccra buffer register. setting of tp0ccr1 register <4> tp0ccr0, tp0ccr1 register setting change flow only writing of the tp0ccr1 register must be performed when the set duty factor is changed. when the counter is cleared after setting, the value of the tp0ccra register is transferred to the ccra buffer register. setting of tp0ccr1 register <3> tp0ccr0, tp0ccr1 register setting change flow tp0ce bit = 0 counting is stopped. stop <5> count operation stop flow remark a = 0, 1 chapter 7 16-bit timer/event counter p (tmp) preliminary user?s manual u17702ej1v0ud 261 (2) external trigger pulse output mode operation timing (a) note on changing pulse width during operation to change the pwm waveform while the counter is operating, write the tp0ccr1 register last. rewrite the tp0ccra register after writing the tp0ccr1 register after the inttp0cc0 signal is detected. ffffh 16-bit counter 0000h tp0ce bit tp0ccr0 register ccr0 buffer register inttp0cc0 signal tp0ccr1 register ccr1 buffer register inttp0cc1 signal top01 pin output external trigger input (tip00 pin input) top00 pin output (software trigger) d 10 d 00 d 00 d 01 d 00 d 10 d 11 d 10 d 11 d 01 d 10 d 10 d 00 d 00 d 11 d 11 d 01 d 01 chapter 7 16-bit timer/event counter p (tmp) preliminary user?s manual u17702ej1v0ud 262 in order to transfer data from the tp0ccra register to the ccra buffer register, the tp0ccr1 register must be written. to change both the cycle and active level width of the pwm waveform at this time, first set the cycle to the tp0ccr0 register and then set the active level width to the tp0ccr1 register. to change only the cycle of the pwm waveform, first set the cycle to the tp0ccr0 register, and then write the same value to the tp0ccr1 register. to change only the active level width (duty factor) of the pwm waveform, only the tp0ccr1 register has to be set. after data is written to the tp0ccr1 register, the val ue written to the tp0ccra register is transferred to the ccra buffer register in synchr onization with clearing of the 16-bi t counter, and is used as the value compared with the 16-bit counter. to write the tp0ccr0 or tp0ccr1 register again after writing the tp0ccr1 register once, do so after the inttp0cc0 signal is generated. otherwise, the value of the ccra buffer register may become undefined because the timing of transferring data from the tp0ccra register to the ccra buffer register conflicts with writing the tp0ccra register. remark a = 0, 1 chapter 7 16-bit timer/event counter p (tmp) preliminary user?s manual u17702ej1v0ud 263 (b) 0%/100% output of pwm waveform to output a 0% waveform, clear the tp0ccr1 register to 0000h. if the set value of the tp0ccr0 register is ffffh, the inttp0cc1 signal is generated periodically. count clock 16-bit counter tp0ce bit tp0ccr0 register tp0ccr1 register inttp0cc0 signal inttp0cc1 signal top01 pin output d 0 0000h d 0 0000h d 0 0000h d 0 ? 1d 0 0000 ffff 0000 d 0 ? 1d 0 0000 0001 to output a 100% waveform, set a value of (set value of tp0ccr0 register + 1) to the tp0ccr1 register. if the set value of the tp0ccr0 register is ffffh, 100% output cannot be produced. count clock 16-bit counter tp0ce bit tp0ccr0 register tp0ccr1 register inttp0cc0 signal inttp0cc1 signal top01 pin output d 0 d 0 + 1 d 0 d 0 + 1 d 0 d 0 + 1 d 0 ? 1d 0 0000 ffff 0000 d 0 ? 1d 0 0000 0001 chapter 7 16-bit timer/event counter p (tmp) preliminary user?s manual u17702ej1v0ud 264 (c) conflict between trigger detecti on and match with tp0ccr1 register if the trigger is detected immediately after the inttp 0cc1 signal is generated, the 16-bit counter is immediately cleared to 0000h, the output signal of the top01 pin is asserted, and the counter continues counting. consequently, the inactive peri od of the pwm waveform is shortened. 16-bit counter tp0ccr1 register inttp0cc1 signal top01 pin output external trigger input (tip00 pin input) d 1 d 1 ? 1 0000 ffff 0000 shortened if the trigger is detected immediately before the inttp 0cc1 signal is generated, the inttp0cc1 signal is not generated, and the 16-bit counter is cleared to 0000h and continues counting. t he output signal of the top01 pin remains active. consequently, the active period of the pwm waveform is extended. 16-bit counter tp0ccr1 register inttp0cc1 signal top01 pin output external trigger input (tip00 pin input) d 1 d 1 ? 2d 1 ? 1d 1 0000 ffff 0000 0001 extended chapter 7 16-bit timer/event counter p (tmp) preliminary user?s manual u17702ej1v0ud 265 (d) conflict between trigger detecti on and match with tp0ccr0 register if the trigger is detected immediately after the inttp 0cc0 signal is generated, the 16-bit counter is cleared to 0000h and continues counting up. therefore, the active period of the top01 pin is extended by time from generation of the inttp0cc0 signal to trigger detection. 16-bit counter tp0ccr0 register inttp0cc0 signal top01 pin output external trigger input (tip00 pin input) d 0 d 0 ? 1d 0 0000 ffff 0000 0000 extended if the trigger is detected immediately before the inttp 0cc0 signal is generated, the inttp0cc0 signal is not generated. the 16-bit counter is cleared to 0000h, the top01 pin is asserted, and the counter continues counting. consequently, the inactive period of the pwm waveform is shortened. 16-bit counter tp0ccr0 register inttp0cc0 signal top01 pin output external trigger input (tip00 pin input) d 0 d 0 ? 1d 0 0000 ffff 0000 0001 shortened chapter 7 16-bit timer/event counter p (tmp) preliminary user?s manual u17702ej1v0ud 266 (e) generation timing of compare match interrupt request signal (inttp0cc1) the timing of generation of the inttp0cc1 signal in the external trigger pulse output mode differs from the timing of other inttp0cc1 signals; the inttp0cc1 signal is generated when the count value of the 16-bit counter matches the value of the tp0ccr1 register. count clock 16-bit counter tp0ccr1 register top01 pin output inttp0cc1 signal d 1 d 1 ? 1d 1 ? 1d 1 d 1 + 1 d 1 + 2 usually, the inttp0cc1 signal is generated in synch ronization with the next count up, after the count value of the 16-bit counter matches the value of the tp0ccr1 register. in the external trigger pulse output mode, however, it is generated one clock earlier. this is because the timing is changed to match the timing of cha nging the output signal of the top01 pin. chapter 7 16-bit timer/event counter p (tmp) preliminary user?s manual u17702ej1v0ud 267 7.5.4 one-shot pulse output mode (tp0md2 to tp0md0 bits = 011) in the one-shot pulse output mode, 16-bit timer/event coun ter p waits for a trigger when the tp0ctl0.tp0ce bit is set to 1. when the valid edge of an external trigger input is detected, 16-bit timer/event counter p starts counting, and outputs a one-shot pulse from the top01 pin. instead of the external trigger, a software trigger can also be generated to output the pulse. when the software trigger is used, the top00 pin outputs the active level while the 16-bit counter is counting, and the inactive level when the counter is stopped (waiting for a trigger). figure 7-20. configuration in one-shot pulse output mode ccr0 buffer register tp0ce bit tp0ccr0 register tp0ccr1 register ccr1 buffer register clear match signal match signal inttp0cc0 signal output controller (rs-ff) top01 pin inttp0cc1 signal top00 pin count clock selection count start control edge detector software trigger generation tip00 pin transfer transfer s r output controller (rs-ff) s r 16-bit counter chapter 7 16-bit timer/event counter p (tmp) preliminary user?s manual u17702ej1v0ud 268 figure 7-21. basic timing in one-shot pulse output mode ffffh 16-bit counter 0000h tp0ce bit tp0ccr0 register inttp0cc0 signal tp0ccr1 register inttp0cc1 signal top01 pin output external trigger input (tip00 pin input) d 1 d 0 d 0 d 1 d 1 d 1 d 0 d 0 delay (d 1 ) active level width (d 0 ? d 1 + 1) delay (d 1 ) active level width (d 0 ? d 1 + 1) delay (d 1 ) active level width (d 0 ? d 1 + 1) top00 pin output (software trigger) when the tp0ce bit is set to 1, 16-bit timer/event counter p waits for a trigger. when the trigger is generated, the 16-bit counter is cleared from ffffh to 0000h, starts counti ng, and outputs a one-shot pul se from the top01 pin. after the one-shot pulse is output, the 16-bit counter is set to ffffh, stops counting, and waits for a trigger. if a trigger is generated again while the one-s hot pulse is being output, it is ignored. the output delay period and active level width of the one-shot pulse can be calculated as follows. output delay period = (set value of tp0ccr1 register) count clock cycle active level width = (set value of tp0ccr0 register ? set value of tp0ccr1 register + 1) count clock cycle the compare match interrupt request signal inttp0cc0 is generated when the 16-bit counter counts after its count value matches the value of the c cr0 buffer register. the compare match interrupt request signal inttp0cc1 is generated when the count value of the 16-bit counter matches the va lue of the ccr1 buffer register. the valid edge of an external trigger input or setting the so ftware trigger (tp0ctl1.tp0est bit) to 1 is used as the trigger. chapter 7 16-bit timer/event counter p (tmp) preliminary user?s manual u17702ej1v0ud 269 figure 7-22. setting of registers in one-shot pulse output mode (1/2) (a) tmp0 control re gister 0 (tp0ctl0) 0/1 0 0 0 0 tp0ctl0 select count clock note 0: stop counting 1: enable counting 0/1 0/1 0/1 tp0cks2 tp0cks1 tp0cks0 tp0ce note the setting is invalid when the tp0ctl1.tp0eee bit = 1. (b) tmp0 control register 1 (tp0ctl1) 0 0/1 0/1 0 0 tp0ctl1 0: operate on count clock selected by tp0cks0 to tp0cks2 bits 1: count external event input signal generate software trigger when 1 is written 011 tp0md2 tp0md1 tp0md0 tp0eee tp0est 0, 1, 1: one-shot pulse output mode (c) tmp0 i/o control register 0 (tp0ioc0) 0 0 0 0 0/1 tp0ioc0 0: disable top00 pin output 1: enable top00 pin output setting of output level while operation of top00 pin is disabled 0: low level 1: high level 0: disable top01 pin output 1: enable top01 pin output specifies active level of top01 pin output 0: active-high 1: active-low 0/1 0/1 0/1 tp0oe1 tp0ol0 tp0oe0 tp0ol1 top01 pin output 16-bit counter ? when tp0ol1 bit = 0 top01 pin output 16-bit counter ? when tp0ol1 bit = 1 chapter 7 16-bit timer/event counter p (tmp) preliminary user?s manual u17702ej1v0ud 270 figure 7-22. setting of registers in one-shot pulse output mode (2/2) (d) tmp0 i/o control register 2 (tp0ioc2) 0 0 0 0 0/1 tp0ioc2 select valid edge of external trigger input select valid edge of external event count input 0/1 0/1 0/1 tp0ees0 tp0ets1 tp0ets0 tp0ees1 (e) tmp0 counter read buffer register (tp0cnt) the value of the 16-bit counter can be read by reading the tp0cnt register. (f) tmp0 capture/compare register s 0 and 1 (tp0ccr0 and tp0ccr1) if d 0 is set to the tp0ccr0 register and d 1 to the tp0ccr1 register, the active level width and output delay period of the one-shot pulse are as follows. active level width = (d 1 ? d 0 + 1) count clock cycle output delay period = d 1 count clock cycle remark tmp0 i/o control register 1 (tp0ioc1) and tm p0 option register 0 (tp0opt0) are not used in the one-shot pulse output mode. chapter 7 16-bit timer/event counter p (tmp) preliminary user?s manual u17702ej1v0ud 271 (1) operation flow in one-shot pulse output mode figure 7-23. software processing flow in one-shot pulse output mode ffffh 16-bit counter 0000h tp0ce bit tp0ccr0 register inttp0cc0 signal tp0ccr1 register inttp0cc1 signal top01 pin output external trigger input (tip00 pin input) <1> <3> tp0ce bit = 1 register initial setting tp0ctl0 register (tp0cks0 to tp0cks2 bits) tp0ctl1 register, tp0ioc0 register, tp0ioc2 register, tp0ccr0 register, tp0ccr1 register initial setting of these registers is performed before setting the tp0ce bit to 1. the tp0cks0 to tp0cks2 bits can be set at the same time when counting has been started (tp0ce bit = 1). trigger wait status start <1> count operation start flow tp0ce bit = 0 count operation is stopped stop <3> count operation stop flow d 10 d 00 d 11 d 01 d 00 d 10 d 11 <2> d 01 setting of tp0ccr0, tp0ccr1 registers as rewriting the tp0ccrm register immediately forwards to the ccrm buffer register, rewriting immediately after the generation of the inttp0ccr0 signal is recommended. <2> tp0ccr0, tp0ccr1 register setting change flow remark m = 0, 1 chapter 7 16-bit timer/event counter p (tmp) preliminary user?s manual u17702ej1v0ud 272 (2) operation timing in one-shot pulse output mode (a) note on rewriti ng tp0ccra register to change the set value of the tp0ccra register to a smaller value, stop counting once, and then change the set value. if the value of the tp0ccra register is rewritten to a smaller value during counting, the 16-bit counter may overflow. ffffh 16-bit counter 0000h tp0ce bit tp0ccr0 register inttp0cc0 signal tp0ccr1 register inttp0cc1 signal top01 pin output external trigger input (tip00 pin input) d 10 d 11 d 00 d 01 d 00 d 10 d 10 d 10 d 01 d 11 d 00 d 00 delay (d 10 ) active level width (d 00 ? d 10 + 1) delay (d 10 ) active level width (d 00 ? d 10 + 1) delay (10000h + d 11 ) active level width (d 01 ? d 11 + 1) top00 pin output (software trigger) when the tp0ccr0 register is rewritten from d 00 to d 01 and the tp0ccr1 register from d 10 to d 11 where d 00 > d 01 and d 10 > d 11 , if the tp0ccr1 register is rewritten when the count value of the 16-bit counter is greater than d 11 and less than d 10 and if the tp0ccr0 register is rewritten when the count value is greater than d 01 and less than d 00 , each set value is reflected as soon as the register has been rewritten and compared with the count value. the counter count s up to ffffh and then counts up again from 0000h. when the count value matches d 11 , the counter generates the inttp0cc1 signal and asserts the top01 pin. when the count value matches d 01 , the counter generates the in ttp0cc0 signal, deasserts the top01 pin, and stops counting. therefore, the counter may output a pulse with a delay period or ac tive period different from that of the one-shot pulse that is originally expected. remark a = 0, 1 chapter 7 16-bit timer/event counter p (tmp) preliminary user?s manual u17702ej1v0ud 273 (b) generation timing of compare match interrupt request signal (inttp0cc1) the generation timing of the inttp0cc1 signal in the one-shot pulse output mode is different from other inttp0cc1 signals; the inttp0cc1 signal is genera ted when the count value of the 16-bit counter matches the value of the tp0ccr1 register. count clock 16-bit counter tp0ccr1 register top01 pin output inttp0cc1 signal d 1 d 1 ? 2d 1 ? 1d 1 d 1 + 1 d 1 + 2 usually, the inttp0cc1 signal is generated when the 16- bit counter counts up next time after its count value matches the value of the tp0ccr1 register. in the one-shot pulse output mode, howe ver, it is generated one clock earlier. this is because the timing is changed to match the change timing of the top01 pin. chapter 7 16-bit timer/event counter p (tmp) preliminary user?s manual u17702ej1v0ud 274 7.5.5 pwm output mode (tp0md2 to tp0md0 bits = 100) in the pwm output mode, a pwm waveform is output from the top01 pin when the tp0ctl0.tp0ce bit is set to 1. in addition, a pulse with one cycle of the pwm waveform as half its cycle is output from the top00 pin. figure 7-24. configuration in pwm output mode ccr0 buffer register tp0ce bit tp0ccr0 register 16-bit counter tp0ccr1 register ccr1 buffer register clear match signal match signal inttp0cc0 signal output controller (rs-ff) output controller top01 pin inttp0cc1 signal top00 pin count clock selection count start control transfer transfer s r chapter 7 16-bit timer/event counter p (tmp) preliminary user?s manual u17702ej1v0ud 275 figure 7-25. basic timing in pwm output mode ffffh 16-bit counter 0000h tp0ce bit tp0ccr0 register ccr0 buffer register inttp0cc0 signal top00 pin output tp0ccr1 register ccr1 buffer register inttp0cc1 signal top01 pin output d 10 d 00 d 00 d 01 d 00 d 10 d 11 d 10 d 11 d 01 d 10 d 10 d 00 d 00 d 11 d 11 d 01 d 01 active period (d 10 ) cycle (d 00 + 1) inactive period (d 00 ? d 10 + 1) when the tp0ce bit is set to 1, the 16-bit counter is cleared from ffffh to 0000h, starts count ing, and outputs a pwm waveform from the top01 pin. the active level width, cycle, and duty factor of the pwm waveform can be calculated as follows. active level width = (set value of tp0ccr1 register ) count clock cycle cycle = (set value of tp0ccr0 register + 1) count clock cycle duty factor = (set value of tp0ccr1 regist er)/(set value of tp0ccr0 register + 1) the pwm waveform can be changed by rewriting the tp0ccra register while the counter is operating. the newly written value is reflected when the count value of the 16-bit counter matches the value of the ccr0 buffer register and the 16-bit counter is cleared to 0000h. the compare match interrupt request signal inttp0cc0 is generated when the 16-bit counter counts next time after its count value matches the value of the ccr0 buffer register, and the 16-bit counter is cleared to 0000h. the compare match interrupt request signal inttp0cc1 is gener ated when the count value of the 16-bit counter matches the value of the ccr1 buffer register. the value set to the tp0ccra register is transferred to t he ccra buffer register when the count value of the 16-bit counter matches the value of the ccra buffer regi ster and the 16-bit counter is cleared to 0000h. remark a = 0, 1 chapter 7 16-bit timer/event counter p (tmp) preliminary user?s manual u17702ej1v0ud 276 figure 7-26. register setting in pwm output mode (1/2) (a) tmp0 control re gister 0 (tp0ctl0) 0/1 0 0 0 0 tp0ctl0 select count clock note 0: stop counting 1: enable counting 0/1 0/1 0/1 tp0cks2 tp0cks1 tp0cks0 tp0ce note the setting is invalid when the tp0ctl1.tp0eee bit = 1. (b) tmp0 control register 1 (tp0ctl1) 0 0 0/1 0 0 tp0ctl1 100 tp0md2 tp0md1 tp0md0 tp0eee tp0est 1, 0, 0: pwm output mode 0: operate on count clock selected by tp0cks0 to tp0cks2 bits 1: count with external event count input signal (c) tmp0 i/o control register 0 (tp0ioc0) 0 0 0 0 0/1 tp0ioc0 0: disable top00 pin output 1: enable top00 pin output setting of output level while operation of top00 pin is disabled 0: low level 1: high level 0: disable top01 pin output 1: enable top01 pin output specifies active level of top01 pin output 0: active-high 1: active-low 0/1 0/1 0/1 tp0oe1 tp0ol0 tp0oe0 tp0ol1 top01 pin output 16-bit counter ? when tp0ol1 bit = 0 top01 pin output 16-bit counter ? when tp0ol1 bit = 1 chapter 7 16-bit timer/event counter p (tmp) preliminary user?s manual u17702ej1v0ud 277 figure 7-26. register setting in pwm output mode (2/2) (d) tmp0 i/o control register 2 (tp0ioc2) 0 0 0 0 0/1 tp0ioc2 select valid edge of external event count input. 0/1 0 0 tp0ees0 tp0ets1 tp0ets0 tp0ees1 (e) tmp0 counter read buffer register (tp0cnt) the value of the 16-bit counter can be read by reading the tp0cnt register. (f) tmp0 capture/compare register s 0 and 1 (tp0ccr0 and tp0ccr1) if d 0 is set to the tp0ccr0 register and d 1 to the tp0ccr1 register, the cycle and active level of the pwm waveform are as follows. cycle = (d 0 + 1) count clock cycle active level width = d 1 count clock cycle remark tmp0 i/o control register 1 (tp0ioc1) and tm p0 option register 0 (tp0opt0) are not used in the pwm output mode. chapter 7 16-bit timer/event counter p (tmp) preliminary user?s manual u17702ej1v0ud 278 (1) operation flow in pwm output mode figure 7-27. software processing flow in pwm output mode (1/2) ffffh 16-bit counter 0000h tp0ce bit tp0ccr0 register ccr0 buffer register inttp0cc0 signal top00 pin output tp0ccr1 register ccr1 buffer register inttp0cc1 signal top01 pin output d 10 d 00 d 00 d 01 d 00 d 00 d 10 d 10 d 11 d 10 d 10 d 10 d 11 d 10 d 01 d 00 d 10 d 10 d 00 d 10 d 00 d 11 d 11 d 01 d 01 d 01 <2> <3> <4> <5> <1> chapter 7 16-bit timer/event counter p (tmp) preliminary user?s manual u17702ej1v0ud 279 figure 7-27. software processing flow in pwm output mode (2/2) tp0ce bit = 1 setting of tp0ccr0 register register initial setting tp0ctl0 register (tp0cks0 to tp0cks2 bits) tp0ctl1 register, tp0ioc0 register, tp0ioc2 register, tp0ccr0 register, tp0ccr1 register initial setting of these registers is performed before setting the tp0ce bit to 1. the tp0cks0 to tp0cks2 bits can be set at the same time when counting is enabled (tp0ce bit = 1). tp0ccr1 write processing is necessary only when the set cycle is changed. when the counter is cleared after setting, the value of the tp0ccra register is transferred to the ccra buffer register. start setting of tp0ccr1 register <1> count operation start flow <2> tp0ccr0, tp0ccr1 register setting change flow setting of tp0ccr0 register when the counter is cleared after setting, the value of compare register a is transferred to the ccra buffer register. setting of tp0ccr1 register <4> tp0ccr0, tp0ccr1 register setting change flow only writing of the tp0ccr1 register must be performed when the set duty factor is changed. when the counter is cleared after setting, the value of compare register a is transferred to the ccra buffer register. setting of tp0ccr1 register <3> tp0ccr0, tp0ccr1 register setting change flow tp0ce bit = 0 counting is stopped. stop <5> count operation stop flow remark a = 0, 1 chapter 7 16-bit timer/event counter p (tmp) preliminary user?s manual u17702ej1v0ud 280 (2) pwm output mode operation timing (a) changing pulse width during operation to change the pwm waveform while the counter is operating, write the tp0ccr1 register last. rewrite the tp0ccra register after writing the tp0ccr1 register after the inttp0cc1 signal is detected. ffffh 16-bit counter 0000h tp0ce bit tp0ccr0 register ccr0 buffer register tp0ccr1 register ccr1 buffer register top01 pin output inttp0cc0 signal d 10 d 00 d 00 d 01 d 00 d 10 d 11 d 10 d 11 d 01 d 10 d 10 d 00 d 00 d 11 d 11 d 01 d 01 to transfer data from the tp0ccra register to the ccr a buffer register, the tp0ccr1 register must be written. to change both the cycle and active level of the pwm waveform at this time, first set the cycle to the tp0ccr0 register and then set the active level to the tp0ccr1 register. to change only the cycle of the pwm waveform, first set the cycle to the tp0ccr0 register, and then write the same value to the tp0ccr1 register. to change only the active level width (duty factor) of the pwm waveform, only the tp0ccr1 register has to be set. after data is written to the tp0ccr1 register, the val ue written to the tp0ccra register is transferred to the ccra buffer register in synchr onization with clearing of the 16-bi t counter, and is used as the value compared with the 16-bit counter. to write the tp0ccr0 or tp0ccr1 register again after writing the tp0ccr1 register once, do so after the inttp0cc0 signal is generated. otherwise, the value of the ccra buffer register may become undefined because the timing of transferring data from the tp0ccr a register to the ccra bu ffer register conflicts with writing the tp0ccra register. remark a = 0, 1 chapter 7 16-bit timer/event counter p (tmp) preliminary user?s manual u17702ej1v0ud 281 (b) 0%/100% output of pwm waveform to output a 0% waveform, set the tp0ccr1 register to 0000h. if the set value of the tp0ccr0 register is ffffh, the inttp0cc1 signal is generated periodically. count clock 16-bit counter tp0ce bit tp0ccr0 register tp0ccr1 register inttp0cc0 signal inttp0cc1 signal top01 pin output d 00 0000h d 00 0000h d 00 0000h d 00 ? 1d 00 0000 ffff 0000 d 00 ? 1d 00 0000 0001 to output a 100% waveform, set a value of (set value of tp0ccr0 register + 1) to the tp0ccr1 register. if the set value of the tp0ccr0 register is ffffh, 100% output cannot be produced. count clock 16-bit counter tp0ce bit tp0ccr0 register tp0ccr1 register inttp0cc0 signal inttp0cc1 signal top01 pin output d 00 d 00 + 1 d 00 d 00 + 1 d 00 d 00 + 1 d 00 ? 1d 00 0000 ffff 0000 d 00 ? 1d 00 0000 0001 chapter 7 16-bit timer/event counter p (tmp) preliminary user?s manual u17702ej1v0ud 282 (c) generation timing of compare match interrupt request signal (inttp0cc1) the timing of generation of the inttp0cc1 signal in the pwm output mode differs from the timing of other inttp0cc1 signals; the inttp0cc1 signal is genera ted when the count value of the 16-bit counter matches the value of the tp0ccr1 register. count clock 16-bit counter tp0ccr1 register top01 pin output inttp0cc1 signal d 1 d 1 ? 2d 1 ? 1d 1 d 1 + 1 d 1 + 2 usually, the inttp0cc1 signal is generated in synch ronization with the next counting up after the count value of the 16-bit counter matches the value of the tp0ccr1 register. in the pwm output mode, however, it is generated one clock earlier. this is because the timing is changed to match the change timing of the output signal of the top01 pin. chapter 7 16-bit timer/event counter p (tmp) preliminary user?s manual u17702ej1v0ud 283 7.5.6 free-running timer mode (tp0md2 to tp0md0 bits = 101) in the free-running timer mode, 16-bit timer/event counter p starts counting when the tp0ctl0.tp0ce bit is set to 1. at this time, the tp0ccra register can be used as a compare register or a c apture register, depending on the setting of the tp0opt0.tp0ccs 0 and tp0opt0.tp0ccs1 bits. figure 7-28. configuration in free-running timer mode tp0ccr0 register (capture) tp0ce bit tp0ccr1 register (capture) 16-bit counter tp0ccr1 register (compare) tp0ccr0 register (compare) output controller tp0ccs0, tp0ccs1 bits (capture/compare selection) top00 pin output output controller top01 pin output edge detector count clock selection digital noise eliminator digital noise eliminator tip00 pin (external event count input/ capture trigger input) tip01 pin (capture trigger input) internal count clock 0 1 0 1 inttp0ov signal inttp0cc1 signal inttp0cc0 signal edge detector edge detector remark a = 0, 1 chapter 7 16-bit timer/event counter p (tmp) preliminary user?s manual u17702ej1v0ud 284 when the tp0ce bit is set to 1, 16-bit timer/event counter p starts counting, and the output signals of the top00 and top01 pins are inverted. when the count value of the 16-bit counter later matches the set value of the tp0ccra register, a compare match interrupt request signal (inttp0 cca) is generated, and the out put signal of the top0a pin is inverted. the 16-bit counter continues counting in synchronization with t he count clock. when it counts up to ffffh, it generates an overflow interrupt request signal (inttp0ov) at the next clock, is cl eared to 0000h, and continues counting. at this time, the overflow flag (tp0opt0.tp0ovf bit) is also set to 1. clear the overflow flag to 0 by executing the clr instruction by software. the tp0ccra register can be rewritten whil e the counter is operating. if it is re written, the new value is reflected at that time, and compared with the count value. figure 7-29. basic timing in free-r unning timer mode (compare function) ffffh 16-bit counter 0000h tp0ce bit tp0ccr0 register inttp0cc0 signal top00 pin output tp0ccr1 register inttp0cc1 signal top01 pin output inttp0ov signal tp0ovf bit d 00 d 01 d 10 d 11 d 00 d 10 d 10 d 11 d 11 d 11 d 00 d 01 d 01 cleared to 0 by clr instruction cleared to 0 by clr instruction cleared to 0 by clr instruction cleared to 0 by clr instruction remark a = 0, 1 chapter 7 16-bit timer/event counter p (tmp) preliminary user?s manual u17702ej1v0ud 285 when the tp0ce bit is set to 1, the 16-bit counter starts counting. when the valid edge input to the tip0a pin is detected, the count value of the 16-bit counter is stored in the tp0ccra register, and a capture interrupt request signal (inttp0cca) is generated. the 16-bit counter continues counting in synchronization with t he count clock. when it counts up to ffffh, it generates an overflow interrupt request signal (inttp0ov) at the next clock, is cl eared to 0000h, and continues counting. at this time, the overflow flag (tp0opt0.tp0ovf bit) is also set to 1. clear the overflow flag to 0 by executing the clr instruction by software. figure 7-30. basic timing in free-r unning timer mode (capture function) ffffh 16-bit counter 0000h tp0ce bit tip00 pin input tp0ccr0 register inttp0cc0 signal tip01 pin input tp0ccr1 register inttp0cc1 signal inttp0ov signal tp0ovf bit d 00 d 01 d 02 d 03 d 10 d 00 d 01 d 02 d 03 d 11 d 12 d 13 d 10 d 11 d 12 d 13 cleared to 0 by clr instruction cleared to 0 by clr instruction cleared to 0 by clr instruction chapter 7 16-bit timer/event counter p (tmp) preliminary user?s manual u17702ej1v0ud 286 figure 7-31. register setting in free-running timer mode (1/2) (a) tmp0 control re gister 0 (tp0ctl0) 0/1 0 0 0 0 tp0ctl0 select count clock note 0: stop counting 1: enable counting 0/1 0/1 0/1 tp0cks2 tp0cks1 tp0cks0 tp0ce note the setting is invalid when the tp0ctl1.tp0eee bit = 1 (b) tmp0 control register 1 (tp0ctl1) 0 0 0/1 0 0 tp0ctl1 101 tp0md2 tp0md1 tp0md0 tp0eee tp0est 1, 0, 1: free-running mode 0: operate with count clock selected by tp0cks0 to tp0cks2 bits 1: count on external event count input signal (c) tmp0 i/o control register 0 (tp0ioc0) 0 0 0 0 0/1 tp0ioc0 0: disable top00 pin output 1: enable top00 pin output setting of output level with operation of top00 pin disabled 0: low level 1: high level 0: disable top01 pin output 1: enable top01 pin output setting of output level with operation of top01 pin disabled 0: low level 1: high level 0/1 0/1 0/1 tp0oe1 tp0ol0 tp0oe0 tp0ol1 chapter 7 16-bit timer/event counter p (tmp) preliminary user?s manual u17702ej1v0ud 287 figure 7-31. register setting in free-running timer mode (2/2) (d) tmp0 i/o control register 1 (tp0ioc1) 0 0 0 0 0/1 tp0ioc1 select valid edge of tip00 pin input select valid edge of tip01 pin input 0/1 0/1 0/1 tp0is2 tp0is1 tp0is0 tp0is3 (e) tmp0 i/o control register 2 (tp0ioc2) 0 0 0 0 0/1 tp0ioc2 select valid edge of external event count input 0/1 0 0 tp0ees0 tp0ets1 tp0ets0 tp0ees1 (f) tmp0 option register 0 (tp0opt0) 0 0 0/1 0/1 0 tp0opt0 overflow flag specifies if tp0ccr0 register functions as capture or compare register specifies if tp0ccr1 register functions as capture or compare register 0 0 0/1 tp0ccs0 tp0ovf tp0ccs1 (g) tmp0 counter read buffer register (tp0cnt) the value of the 16-bit counter can be read by reading the tp0cnt register. (h) tmp0 capture/compare regist ers 0 and 1 (tp0ccr0 and tp0ccr1) these registers function as captur e registers or compare registers depending on the setting of the tp0opt0.tp0ccsa bit. when the registers function as captur e registers, they store the count value of the 16-bit counter when the valid edge input to t he tip0a pin is detected. when the registers function as compare registers and when d a is set to the tp0ccra register, the inttp0cca signal is generated when the counter reaches (d a + 1), and the output signal of the top0a pin is inverted. remark a = 0, 1 chapter 7 16-bit timer/event counter p (tmp) preliminary user?s manual u17702ej1v0ud 288 (1) operation flow in free-running timer mode (a) when using capture/compare register as compare register figure 7-32. software processing flow in fr ee-running timer mode (c ompare function) (1/2) ffffh 16-bit counter 0000h tp0ce bit tp0ccr0 register inttp0cc0 signal top00 pin output tp0ccr1 register inttp0cc1 signal top01 pin output inttp0ov signal tp0ovf bit d 00 d 01 d 10 d 11 d 00 d 10 d 10 d 11 d 11 d 11 d 00 d 01 d 01 cleared to 0 by clr instruction cleared to 0 by clr instruction cleared to 0 by clr instruction <1> <2> <2> <2> <3> chapter 7 16-bit timer/event counter p (tmp) preliminary user?s manual u17702ej1v0ud 289 figure 7-32. software processing flow in fr ee-running timer mode (c ompare function) (2/2) tp0ce bit = 1 read tp0opt0 register (check overflow flag). register initial setting tp0ctl0 register (tp0cks0 to tp0cks2 bits) tp0ctl1 register, tp0ioc0 register, tp0ioc2 register, tp0opt0 register, tp0ccr0 register, tp0ccr1 register initial setting of these registers is performed before setting the tp0ce bit to 1. the tp0cks0 to tp0cks2 bits can be set at the same time when counting has been started (tp0ce bit = 1). start execute instruction to clear tp0ovf bit (clr tp0ovf). <1> count operation start flow <2> overflow flag clear flow tp0ce bit = 0 counter is initialized and counting is stopped by clearing tp0ce bit to 0. stop <3> count operation stop flow tp0ovf bit = 1 no yes chapter 7 16-bit timer/event counter p (tmp) preliminary user?s manual u17702ej1v0ud 290 (b) when using capture/compare register as capture register figure 7-33. software processing flow in fr ee-running timer mode (c apture function) (1/2) ffffh 16-bit counter 0000h tp0ce bit tip00 pin input tp0ccr0 register inttp0cc0 signal tip01 pin input tp0ccr1 register inttp0cc1 signal inttp0ov signal tp0ovf bit d 00 0000 0000 d 01 d 02 d 03 d 10 d 00 d 01 d 02 d 03 d 11 d 12 d 10 0000 d 11 d 12 0000 cleared to 0 by clr instruction cleared to 0 by clr instruction <3> <1> <2> <2> chapter 7 16-bit timer/event counter p (tmp) preliminary user?s manual u17702ej1v0ud 291 figure 7-33. software processing flow in fr ee-running timer mode (c apture function) (2/2) tp0ce bit = 1 read tp0opt0 register (check overflow flag). register initial setting tp0ctl0 register (tp0cks0 to tp0cks2 bits) tp0ctl1 register, tp0ioc1 register, tp0opt0 register initial setting of these registers is performed before setting the tp0ce bit to 1. the tp0cks0 to tp0cks2 bits can be set at the same time when counting has been started (tp0ce bit = 1). start execute instruction to clear tp0ovf bit (clr tp0ovf). <1> count operation start flow <2> overflow flag clear flow tp0ce bit = 0 counter is initialized and counting is stopped by clearing tp0ce bit to 0. stop <3> count operation stop flow tp0ovf bit = 1 no yes chapter 7 16-bit timer/event counter p (tmp) preliminary user?s manual u17702ej1v0ud 292 (2) operation timing in free-running timer mode (a) interval operation with compare register when 16-bit timer/event counter p is used as an interval timer with the tp0ccra register used as a compare register, software processing is necessary for setting a comparison value to generate the next interrupt request signal each time the inttp0cca signal has been detected. ffffh 16-bit counter 0000h tp0ce bit tp0ccr0 register inttp0cc0 signal top00 pin output tp0ccr1 register inttp0cc1 signal top01 pin output d 00 d 01 d 02 d 03 d 04 d 05 d 10 d 00 d 11 d 01 d 12 d 04 d 13 d 02 d 03 d 11 d 10 d 12 d 13 d 14 interval period (d 10 + 1) interval period (10000h + d 11 ? d 10 ) interval period (10000h + d 12 ? d 11 ) interval period (10000h + d 13 ? d 12 ) interval period (d 00 + 1) interval period (10000h + d 01 ? d 00 ) interval period (d 02 ? d 01 ) interval period (10000h + d 03 ? d 02 ) interval period (10000h + d 04 ? d 03 ) when performing an interval operation in the free-running timer mode, two intervals can be set with one channel. to perform the interval operation, the value of the corresponding tp0ccra register must be re-set in the interrupt servicing that is executed when the inttp0cca signal is detected. the set value for re-setting the tp0ccra register can be calculated by the following expression, where ?d a ? is the interval period. compare register default value: d a ? 1 value set to compare register second and subsequent time: previous set value + d a (if the calculation result is greate r than ffffh, subtract 10000h from the result and set this value to the register.) remark a = 0, 1 chapter 7 16-bit timer/event counter p (tmp) preliminary user?s manual u17702ej1v0ud 293 (b) pulse width measurement with capture register when pulse width measurement is performed with the tp0ccra register used as a capture register, software processing is necessary for reading the capt ure register each time the inttp0cca signal has been detected and for calculating an interval. ffffh 16-bit counter 0000h tp0ce bit tip00 pin input tp0ccr0 register inttp0cc0 signal tip01 pin input tp0ccr1 register inttp0cc1 signal inttp0ov signal tp0ovf bit 0000h d 00 d 01 d 02 d 03 d 04 d 10 d 00 d 11 d 01 d 12 d 04 d 13 d 02 d 03 d 10 0000h d 11 d 12 d 13 pulse interval (d 00 ) pulse interval (10000h + d 01 ? d 00 ) pulse interval (d 02 ? d 01 ) pulse interval (10000h + d 03 ? d 02 ) pulse interval (10000h + d 04 ? d 03 ) pulse interval (d 10 ) pulse interval (10000h + d 11 ? d 10 ) pulse interval (10000h + d 12 ? d 11 ) pulse interval (10000h + d 13 ? d 12 ) cleared to 0 by clr instruction cleared to 0 by clr instruction cleared to 0 by clr instruction when executing pulse width measurement in the fr ee-running timer mode, two pulse widths can be measured with one channel. to measure a pulse width, the pulse width can be calcul ated by reading the value of the tp0ccra register in synchronization with the inttp0cca signal, and calc ulating the difference between the read value and the previously read value. remark a = 0, 1 chapter 7 16-bit timer/event counter p (tmp) preliminary user?s manual u17702ej1v0ud 294 (c) processing of overflow when two capture registers are used care must be exercised in processing the overflow flag when two capture registers are used. first, an example of incorrect processing is shown below. example of incorrect processing when two capture regi sters are used ffffh 16-bit counter 0000h tp0ce bit tip00 pin input tp0ccr0 register tip01 pin input tp0ccr1 register inttp0ov signal tp0ovf bit d 00 d 01 d 10 d 11 d 10 <1> <2> <3> <4> d 00 d 11 d 01 the following problem may occur when two pulse widt hs are measured in the free-running timer mode. <1> read the tp0ccr0 register (setting of t he default value of the tip00 pin input). <2> read the tp0ccr1 register (setting of t he default value of the tip01 pin input). <3> read the tp0ccr0 register. read the overflow flag. if the overflow flag is 1, clear it to 0. because the overflow flag is 1, the pulse width can be calculated by (10000h + d 01 ? d 00 ). <4> read the tp0ccr1 register. read the overflow flag. because the flag is cleared in <3>, 0 is read. because the overflow flag is 0, the pulse width can be calculated by (d 11 ? d 10 ) (incorrect). when two capture registers are used, and if the overflow flag is cleared to 0 by one capture register, the other capture register may not obtain the correct pulse width. use software when using two capture registers. an example of how to use software is shown below. chapter 7 16-bit timer/event counter p (tmp) preliminary user?s manual u17702ej1v0ud 295 (1/2) example when two capture registers are used (usi ng overflow interrupt) ffffh 16-bit counter 0000h tp0ce bit inttp0ov signal tp0ovf bit tp0ovf0 flag note tip00 pin input tp0ccr0 register tp0ovf1 flag note tip01 pin input tp0ccr1 register d 10 d 11 d 00 d 01 d 10 <1> <2> <5> <6> <3> <4> d 00 d 11 d 01 note the tp0ovf0 and tp0ovf1 flags are set on the internal ram by software. <1> read the tp0ccr0 register (setting of t he default value of the tip00 pin input). <2> read the tp0ccr1 register (setting of t he default value of the tip01 pin input). <3> an overflow occurs. set the tp0ovf0 and tp0ovf 1 flags to 1 in the overflow interrupt servicing, and clear the overflow flag to 0. <4> read the tp0ccr0 register. read the tp0ovf0 flag. if the tp0ovf0 flag is 1, clear it to 0. because the tp0ovf0 flag is 1, the pulse width can be calculated by (10000h + d 01 ? d 00 ). <5> read the tp0ccr1 register. read the tp0ovf1 flag. if the tp0ovf1 flag is 1, clear it to 0 (the tp0ovf0 flag is cleared in <4>, and the tp0ovf1 flag remains 1). because the tp0ovf1 flag is 1, the puls e width can be calculated by (10000h + d 11 ? d 10 ) (correct). <6> same as <3> chapter 7 16-bit timer/event counter p (tmp) preliminary user?s manual u17702ej1v0ud 296 (2/2) example when two capture re gisters are used (without using overflow interrupt) ffffh 16-bit counter 0000h tp0ce bit inttp0ov signal tp0ovf bit tp0ovf0 flag note tip00 pin input tp0ccr0 register tp0ovf1 flag note tip01 pin input tp0ccr1 register d 10 d 11 d 00 d 01 d 10 <1> <2> <5> <6> <3> <4> d 00 d 11 d 01 note the tp0ovf0 and tp0ovf1 flags are set on the internal ram by software. <1> read the tp0ccr0 register (setting of t he default value of the tip00 pin input). <2> read the tp0ccr1 register (setting of t he default value of the tip01 pin input). <3> an overflow occurs. nothing is done by software. <4> read the tp0ccr0 register. read the overflow flag. if the overflow flag is 1, set only the tp0ovf1 flag to 1, and clear the overflow flag to 0. because the overflow flag is 1, the pulse width can be calculated by (10000h + d 01 ? d 00 ). <5> read the tp0ccr1 register. read the overflow flag. because the overflow flag is cleared in <4>, 0 is read. read the tp0ovf1 flag. if the tp0ovf1 flag is 1, clear it to 0. because the tp0ovf1 flag is 1, the pulse width can be calculated by (10000h + d 11 ? d 10 ) (correct). <6> same as <3> chapter 7 16-bit timer/event counter p (tmp) preliminary user?s manual u17702ej1v0ud 297 (d) processing of overflow if capture trigger interval is long if the pulse width is greater than one cycle of the 16- bit counter, care must be exercised because an overflow may occur more than once from the first captur e trigger to the next. first, an example of incorrect processing is shown below. example of incorrect processing when capture trigger interval is long ffffh 16-bit counter 0000h tp0ce bit tip0a pin input tp0ccra register inttp0ov signal tp0ovf bit d a0 d a1 d a0 d a1 <1> <2> <3> <4> 1 cycle of 16-bit counter pulse width the following problem may occur when long pulse width is measured in the free-running timer mode. <1> read the tp0ccra register (setting of t he default value of the tip0a pin input). <2> an overflow occurs. nothing is done by software. <3> an overflow occurs a second time. nothing is done by software. <4> read the tp0ccra register. read the overflow flag. if the overflow flag is 1, clear it to 0. because the overflow flag is 1, the pul se width can be calculated by (10000h + d a1 ? d a0 ) (incorrect). actually, the pulse width must be (20000h + d a1 ? d a0 ) because an overflow occurs twice. if an overflow occurs twice or more when the capture tr igger interval is long, the correct pulse width may not be obtained. if the capture trigger interval is long, slow the count clock to lengthen one cycle of the 16-bit counter, or use software. an example of how to use software is shown next. chapter 7 16-bit timer/event counter p (tmp) preliminary user?s manual u17702ej1v0ud 298 example when capture trigger interval is long ffffh 16-bit counter 0000h tp0ce bit tip0a pin input tp0ccra register inttp0ov signal tp0ovf bit overflow counter note d a0 d a1 1h 0h 2h 0h d a0 d a1 <1> <2> <3> <4> 1 cycle of 16-bit counter pulse width note the overflow counter is set arbitrarily by software on the internal ram. <1> read the tp0ccra register (setting of t he default value of the tip0a pin input). <2> an overflow occurs. increment the overflow count er and clear the overflow flag to 0 in the overflow interrupt servicing. <3> an overflow occurs a second time. increment (+1) the overflow counter and clear the overflow flag to 0 in the overflow interrupt servicing. <4> read the tp0ccra register. read the overflow counter. when the overflow counter is ?n?, t he pulse width can be calculated by (n 10000h + d a1 ? d a0 ). in this example, the pulse width is (20000h + d a1 ? d a0 ) because an overflow occurs twice. clear the overflow counter (0h). chapter 7 16-bit timer/event counter p (tmp) preliminary user?s manual u17702ej1v0ud 299 (e) clearing overflow flag the overflow flag can be cleared to 0 by clearing th e tp0ovf bit to 0 with the clr instruction and by writing 8-bit data (bit 0 is 0) to the tp0opt0 regist er. to accurately detect an overflow, read the tp0ovf bit when it is 1, and then clear the overflow flag by using a bit manipulation instruction. (i) operation to write 0 (without conflict with setting) (iii) operation to clear to 0 (without conflict with setting) (ii) operation to write 0 (conflict with setting) (iv) operation to clear to 0 (conflict with setting) 0 write signal overflow set signal register access signal overflow flag (tp0ovf bit) read write 0 write signal overflow set signal register access signal overflow flag (tp0ovf bit) read write 0 write signal overflow set signal 0 write signal overflow set signal overflow flag (tp0ovf bit) overflow flag (tp0ovf bit) l h l to clear the overflow flag to 0, read the overflow flag to check if it is set to 1, and clear it with the clr instruction. if 0 is written to the overflow flag wit hout checking if the flag is 1, the set information of overflow may be erased by writing 0 ((ii) in the above chart). therefore, software may judge that no overflow has occurred even when an overflow actually has occurred. if execution of the clr instruction conflicts with occurrence of an over flow when the overflow flag is cleared to 0 with the clr instruction, the overflow flag remains set even after execution of the clear instruction. chapter 7 16-bit timer/event counter p (tmp) preliminary user?s manual u17702ej1v0ud 300 7.5.7 pulse width measurement mode (tp0md2 to tp0md0 bits = 110) in the pulse width measurement mode, 16-bit timer/event counter p starts counting when the tp0ctl0.tp0ce bit is set to 1. each time the valid edge input to the tip0a pi n has been detected, the count va lue of the 16-bit counter is stored in the tp0ccra register, and the 16-bit counter is cleared to 0000h. the interval of the valid edge can be measured by readin g the tp0ccra register after a capture interrupt request signal (inttp0cca) occurs. select either the tip00 or tip01 pin as the capture trigger input pin. specify ?no edge detected? by using the tp0ioc1 register for the unused pins. when an external clock is used as the count clock, measur e the pulse width of the tip01 pin because the external clock is fixed to the tip00 pin. at this time, clear the tp0ioc1.tp0is1 and tp0ioc1.tp0is0 bits to 00 (capture trigger input (tip00 pin): no edge detected). figure 7-34. configuration in pulse width measurement mode tp0ccr0 register (capture) tp0ce bit tp0ccr1 register (capture) edge detector count clock selection edge detector edge detector tip00 pin (external event count input/capture trigger input) tip01 pin (capture trigger input) internal count clock clear inttp0ov signal inttp0cc0 signal inttp0cc1 signal 16-bit counter digital noise eliminator digital noise eliminator remark a = 0, 1 chapter 7 16-bit timer/event counter p (tmp) preliminary user?s manual u17702ej1v0ud 301 figure 7-35. basic timing in pulse width measurement mode ffffh 16-bit counter 0000h tp0ce bit tip0a pin input tp0ccra register inttp0cca signal inttp0ov signal tp0ovf bit d 0 0000h d 1 d 2 d 3 cleared to 0 by clr instruction remark a = 0, 1 when the tp0ce bit is set to 1, the 16-bit counter starts counting. when the valid edge input to the tip0a pin is later detected, the count value of the 16-bit counter is stored in the tp0ccra register, the 16-bit counter is cleared to 0000h, and a capture interrupt request signal (inttp0cca) is generated. the pulse width is calculated as follows. pulse width = captured value count clock cycle if the valid edge is not input to the tip0a pin even wh en the 16-bit counter counted up to ffffh, an overflow interrupt request signal (inttp0ov) is generated at the next count clock, and the counter is cleared to 0000h and continues counting. at this time, the overflow flag (tp0opt0.t p0ovf bit) is also set to 1. clear the overflow flag to 0 by executing the clr instruction via software. if the overflow flag is set to 1, the pu lse width can be calculated as follows. pulse width = (10000h tp0ovf bit set (1) count + captured value) count clock cycle remark a = 0, 1 chapter 7 16-bit timer/event counter p (tmp) preliminary user?s manual u17702ej1v0ud 302 figure 7-36. register setting in pu lse width measurement mode (1/2) (a) tmp0 control re gister 0 (tp0ctl0) 0/1 0 0 0 0 tp0ctl0 select count clock note 0: stop counting 1: enable counting 0/1 0/1 0/1 tp0cks2 tp0cks1 tp0cks0 tp0ce note setting is invalid when the tp0eee bit = 1. (b) tmp0 control register 1 (tp0ctl1) 0 0 0/1 0 0 tp0ctl1 110 tp0md2 tp0md1 tp0md0 tp0eee tp0est 1, 1, 0: pulse width measurement mode 0: operate with count clock selected by tp0cks0 to tp0cks2 bits 1: count external event count input signal (c) tmp0 i/o control register 1 (tp0ioc1) 0 0 0 0 0/1 tp0ioc1 select valid edge of tip00 pin input select valid edge of tip01 pin input 0/1 0/1 0/1 tp0is2 tp0is1 tp0is0 tp0is3 (d) tmp0 i/o control register 2 (tp0ioc2) 0 0 0 0 0/1 tp0ioc2 select valid edge of external event count input 0/1 0 0 tp0ees0 tp0ets1 tp0ets0 tp0ees1 chapter 7 16-bit timer/event counter p (tmp) preliminary user?s manual u17702ej1v0ud 303 figure 7-36. register setting in pu lse width measurement mode (2/2) (e) tmp0 option register 0 (tp0opt0) 00000 tp0opt0 overflow flag 0 0 0/1 tp0ccs0 tp0ovf tp0ccs1 (f) tmp0 counter read buffer register (tp0cnt) the value of the 16-bit counter can be read by reading the tp0cnt register. (g) tmp0 capture/compare regist ers 0 and 1 (tp0ccr0 and tp0ccr1) these registers store the count valu e of the 16-bit counter when the valid edge input to the tip0a pin is detected. remarks 1. tmp0 i/o control register 0 (tp0ioc0) is not used in the pulse wid th measurement mode. 2. a = 0, 1 chapter 7 16-bit timer/event counter p (tmp) preliminary user?s manual u17702ej1v0ud 304 (1) operation flow in pul se width measurement mode figure 7-37. software processing flow in pulse width measurement mode <1> <2> set tp0ctl0 register (tp0ce bit = 1) tp0ce bit = 0 register initial setting tp0ctl0 register (tp0cks0 to tp0cks2 bits), tp0ctl1 register, tp0ioc1 register, tp0ioc2 register, tp0opt0 register initial setting of these registers is performed before setting the tp0ce bit to 1. the tp0cks0 to tp0cks2 bits can be set at the same time when counting has been started (tp0ce bit = 1). the counter is initialized and counting is stopped by clearing the tp0ce bit to 0. start stop <1> count operation start flow <2> count operation stop flow ffffh 16-bit counter 0000h tp0ce bit tip00 pin input tp0ccr0 register inttp0cc0 signal d 0 0000h 0000h d 1 d 2 chapter 7 16-bit timer/event counter p (tmp) preliminary user?s manual u17702ej1v0ud 305 (2) operation timing in pul se width measurement mode (a) clearing overflow flag the overflow flag can be cleared to 0 by clearing th e tp0ovf bit to 0 with the clr instruction and by writing 8-bit data (bit 0 is 0) to the tp0opt0 regist er. to accurately detect an overflow, read the tp0ovf bit when it is 1, and then clear the overflow flag by using a bit manipulation instruction. (i) operation to write 0 (without conflict with setting) (iii) operation to clear to 0 (without conflict with setting) (ii) operation to write 0 (conflict with setting) (iv) operation to clear to 0 (conflict with setting) 0 write signal overflow set signal register access signal overflow flag (tp0ovf bit) read write 0 write signal overflow set signal register access signal overflow flag (tp0ovf bit) read write 0 write signal overflow set signal 0 write signal overflow set signal overflow flag (tp0ovf bit) overflow flag (tp0ovf bit) l h l to clear the overflow flag to 0, read the overflow flag to check if it is set to 1, and clear it with the clr instruction. if 0 is written to the overflow flag wit hout checking if the flag is 1, the set information of overflow may be erased by writing 0 ((ii) in the above chart). therefore, software may judge that no overflow has occurred even when an overflow actually has occurred. if execution of the clr instruction conflicts with occurrence of an over flow when the overflow flag is cleared to 0 with the clr instruction, the overflow flag remains set even after execution of the clear instruction. chapter 7 16-bit timer/event counter p (tmp) preliminary user?s manual u17702ej1v0ud 306 7.5.8 timer output operations the following table shows the operations and out put levels of the top00 and top01 pins. table 7-4. timer output control in each mode operation mode top01 pin top00 pin interval timer mode square wave output external event count mode square wave output ? external trigger pulse output mode external trigger pulse output one-shot pulse output mode one-shot pulse output pwm output mode pwm output square wave output free-running timer mode square wave output (only when compare function is used) pulse width measurement mode ? table 7-5. truth table of top00 and top01 pins under control of timer output control bits tp0ioc0.tp0ola bit tp0ioc0.tp0oea bit tp0ctl0.tp0ce bit level of top0a pin 0 low-level output 0 low-level output 0 1 1 low level immediately before counting, high level after counting is started 0 high-level output 0 high-level output 1 1 1 high level immediately before counting, low level after counting is started remark a = 0, 1 chapter 7 16-bit timer/event counter p (tmp) preliminary user?s manual u17702ej1v0ud 307 7.6 eliminating noise on capture trigger input pin (tip0a) the tip0a pin has a digital noise eliminator. however, this circuit is valid only when the pin is used as a capture trigger input pin; it is invalid when the pin is used as an external event count input pin or external trigger input pin. digital noise can be eliminated by specifying the alter nate function of the tip0a pi n using the pmc3, pfc3, and pfce3 registers. the number of times of sampling can be selected from three or two by using the panfc.panfsts bit. the sampling clock can be selected from f xx , f xx /2, f xx /4, f xx /16, f xx /32, or f xx /64, by using the panfc.panfc2 to panfc.panfc0 bits. (1) tip0a noise elimination control register (panfc) this register is used to select the sampling clock and t he number of times of sampling for eliminating digital noise. this register can be read or written in 8-bit or 1-bit units. reset input clears this register to 00h. 0 panfc (a = 0, 1) panfsts 0 0 0 panfc2 panfc1 panfc0 number of times of sampling = 3 number of times of sampling = 2 panfsts 0 1 setting of number of times of sampling for eliminating digital noise after reset: 00h r/w address: p0nfc fffffb00h, p1nfc fffffb04h f xx f xx /2 f xx /4 f xx /16 f xx /32 f xx /64 panfc2 0 0 0 0 1 1 panfc1 0 0 1 1 0 0 panfc0 0 1 0 1 0 1 sampling clock selection setting prohibited other than above cautions 1. enable starting the 16-bit counter of tmp0 (tp0ctl.tp0ce bit = 1) after the lapse of the sampling clock period number of times of sampling. 2. be sure to clear bits 7, 5 to 3 to 0. chapter 7 16-bit timer/event counter p (tmp) preliminary user?s manual u17702ej1v0ud 308 chapter 7 16-bit timer/event counter p (tmp) preliminary user?s manual u17702ej1v0ud 309 7.7 cautions (1) capture operation when the capture operation is used and f xx /8, f xx /16, f xx /32, f xx /64, f xx /128, or the external event counter (tp0clt1.tp0eee bit = 1) is selected as the count clock, ffffh, not 0000h, may be captured in the tp0ccrn register if the capture trigger is input immediately after the tp0ce bit is set to 1. (a) free-running timer mode count clock 0000h ffffh tp0ce bit tp0ccr0 register ffffh 0001h 0000h tip00 pin input capture trigger input 16-bit counter sampling clock (f xx ) capture trigger input (b) pulse width measurement mode 0000h ffffh ffffh 0002h 0000h count clock tp0ce bit tp0ccr0 register tip00 pin input capture trigger input 16-bit counter sampling clock (f xx ) capture trigger input preliminary user?s manual u17702ej1v0ud 310 chapter 8 16-bit timer/event counter 0 in the v850es/kj2, six channels of 16-bi t timer/event counter 0 are provided. 8.1 functions 16-bit timer/event counter 0n has the following functions (n = 0 to 5). (1) interval timer 16-bit timer/event counter 0n generates an inte rrupt request at the preset time interval. (2) square-wave output 16-bit timer/event counter 0n can output a square wave with any selected frequency. (3) external event counter 16-bit timer/event counter 0n c an measure the number of pulses of an externally input signal. (4) one-shot pulse output 16-bit timer/event counter 0n can output a one-shot pulse whose output pulse width can be set freely. (5) ppg output 16-bit timer/event counter 0n can output a rectangular wa ve whose frequency and output pulse width can be set freely. (6) pulse width measurement 16-bit timer/event counter 0n can measure the pulse width of an externally input signal. chapter 8 16-bit timer/event counter 0 preliminary user?s manual u17702ej1v0ud 311 8.2 configuration 16-bit timer/event counter 0n includes the following hardware. table 8-1. configuration of 16-bit timer/event counter 0n item configuration time/counter 16-bit timer counter 0n (tm0n) register 16-bit timer capture/ compare registers: 16-bit 2 (cr0n0, cr0n1) timer input 2 (ti0n0, ti0n1 pins) timer output 1 (to0n pin), output controller control registers note 16-bit timer mode control register 0n (tmc0n) capture/compare control register 0n (crc0n) 16-bit timer output control register 0n (toc0n) prescaler mode register 0n (prm0n) selector operation control register 1 (selcnt1) note to use the ti0n0, ti0n1, and to0n pin functions, refer to table 4-19 settings when port pins are used for alternate functions . the block diagram is shown below. figure 8-1. block diagram of 16-bit timer/event counter 0n inttm0n0 to0n inttm0n1 tl0n1 f xx /4 tl0n0 3 crc0n2 crc0n1 crc0n0 tmc0n3 tmc0n2 tmc0n1 ovf0n ospt0n ospe0n toc0n4 lvs0n lvr0n toc0n1 toe0n match clear noise eliminator noise eliminator 16-bit timer capture/compare register 0n0 (cr0n0) 16-bit timer capture/compare register 0n1 (cr0n1) 16-bit timer counter 0n (tm0n) match internal bus count clock capture/compare control register 0n (crc0n) output controller selector timer output control register 0n (toc0n) noise eliminator 16-bit timer mode control register 0n (tmc0n) selector selector internal bus selector prescaler mode register 0n (prm0n) selector operation control register 1 (selcnt1) prm0n1 isel1n prm0n0 remarks 1. f xx : main clock frequency 2. n = 0 to 5 chapter 8 16-bit timer/event counter 0 preliminary user?s manual u17702ej1v0ud 312 (1) 16-bit timer counter 0n (tm0n) the tm0n register is a 16-bit read-only register that counts count pulses. the counter is incremented in synchronization with the rising edge of the count clock. tm0n (n = 0 to 5) 12 10 8 6 4 2 after reset: 0000h r address: tm00 fffff600h, tm01 fffff610h, tm02 fffff620h, tm03 fffff630h, tm04 fffff640h, tm05 fffff650h 14 0 13 11 9 7 5 3 15 1 the count value of the tm0n regist er can be read by reading the tm0n register when the values of the tmc0n.tmc0n3 and tmc0n.tmc0n2 bits are other than 00. t he value of the tm0n register is 0000h if it is read when the tmc0n3 and tmc0n2 bits are 00. the count value is reset to 0000h in the following cases. ? at reset signal generation ? if the tmc0n3 and tmc0n2 bits are cleared to 00 ? if the valid edge of the ti0n0 pin is input in the mode in which the clear & start occurs when inputting the valid edge to the ti0n0 pin ? if the tm0n register and the cr0n0 register match in the mode in which the clear & start occurs when the tm0n register and the cr0n0 register match ? the toc0n.ospt0n bit is set to 1 in one-shot pulse out put mode or the valid edge is input to the ti0n0 pin remark n = 0 to 5 (2) 16-bit timer capture/compare regi ster 0n0 (cr0n0), 16-bit timer captu re/compare register 0n1 (cr0n1) the cr0n0 and cr0n1 registers are 16-bi t registers that are used with a capt ure function or comparison function selected by using the crc0n register. change of the value of the cr0n0 register while th e timer is operating (tmc0n.tmc0n3 and tmc0n.tmc0n2 bits = other than 00) is prohibited. the value of the cr0n1 register can be changed during operat ion if the value has been set in a specific way. for details, see 8.5.1 rewriting cr0n0 regi ster during tm0n operation . these registers can be read or written in 16-bit units. reset sets these registers to 0000h. (a) 16-bit timer capture/comp are register 0n0 (cr0n0) cr0n0 (n = 0 to 5) 12108642 after reset: 0000h r/w address: cr000 fffff602h, cr010 fffff612h, cr020 fffff622h, cr030 fffff632h, cr040 fffff642h, cr050 fffff652h 14 0 13 11 9 7 5 3 15 1 chapter 8 16-bit timer/event counter 0 preliminary user?s manual u17702ej1v0ud 313 (i) when the cr0n0 register is used as a compare register the value set in the cr0n0 register is constantly compar ed with the tm0n register count value, and an interrupt request signal (inttm0n0) is generated if they match. the va lue is held until the cr0n0 register is rewritten. (ii) when the cr0n0 register is used as a capture register the count value of the tm0n register is captured to the cr0n0 register when a capture trigger is input. as the capture trigger, an edge of a phase reverse to that of the ti0n0 pin or the valid edge of the ti0n1 pin can be selected by using the crc0n or prm0n register. (b) 16-bit timer capture/comp are register 0n1 (cr0n1) cr0n1 (n = 0 to 5) 12 10 8 6 4 2 after reset: 0000h r/w address: cr001 fffff604h, cr011 fffff614h, cr021 fffff624h, cr031 fffff634h, cr041 fffff644h, cr051 fffff654h 14 0 13 11 9 7 5 3 15 1 (i) when using the cr0n1 register as a compare register the value set to the cr0n1 register and the count value of the tm0n re gister are always compared and when these values match, an interrupt re quest signal (inttm0n1) is generated. (ii) when using the cr0n1 regi ster as a capture register the tm0n register count value is captured to the cr0n1 register by inputting a capture trigger. the valid edge of the ti0n0 pin can be selected as t he capture trigger. the valid edge of the ti0n0 pin is set with the prm0n register. cautions 1. when the p33, p35, p92, and p94 pins are used as the valid edg es of ti000, ti010, ti020, and ti030, and the timer output function is used, set the p34, p32, p30, and p31 pins as the timer output pins (to00 to to03). 2. if clearing of the tmc0n3 and tmc0n2 bits to 00 and input of the capture trigger conflict, then the captured data is undefined. 3. to change the mode from the capture mode to the comparis on mode, first clear the tmc0n3 and tmc0n2 bits to 00, and then change the setting. a value that has been on ce captured remains stored in the cr0n0 and cr0n1 registers unless the device is reset. if the mode has b een changed to the comparison mode, be sure to set a comparison value. chapter 8 16-bit timer/event counter 0 preliminary user?s manual u17702ej1v0ud 314 (c) setting range when u sed as compare register when the cr0n0 or cr0n1 register is used as a compare register, set it as shown below. operation cr0n0 register cr0n1 register ? operation as interval timer ? operation as square-wave output ? operation as external event counter 0000h < n ffffh 0000h note m ffffh normally, this setting is not used. mask the match interrupt signal (inttm0n1). ? operation in the clear & start mode entered by ti0n0 pin valid edge input ? operation as free-running timer 0000h note n ffffh 0000h note m ffffh ? operation as ppg output m < n ffffh 0000h note m n ? operation as one-shot pulse output 0000h note n ffffh (n m) 0000h note m ffffh (m n) note when 0000h is set, a match interrupt immediately after the timer operation does not occur and timer output is not changed, and the first match timing is as follows . a match interrupt occurs at the timing when the timer counter (tm0n register) is changed from 0000h to 0001h. ? when the timer counter is cleared due to overflow ? when the timer counter is cleared due to ti0n0 pin valid edge (when clear & start mode is entered by ti0n0 pin valid edge input) ? when the timer counter is cleared due to compare ma tch (when clear & start mode is entered by match between tm0n and cr0n0 (cr0n0 = other than 0000h, cr0n1 = 0000h)) operation enabled (other than 00) tm0n register timer counter clear interrupt signal is not generated interrupt signal is generated timer operation enable bit interrupt request signal compare register set value (0000h) operation disabled (00) remarks 1. n: cr0n0 register set value m: cr0n1 register set value 2. for details of operation enable bits (tmc 0n.tmc0n3, tmc0n.tmc0n2 bits), refer to 8.3 (1) 16-bit timer mode control register 0n (tmc0n) . chapter 8 16-bit timer/event counter 0 preliminary user?s manual u17702ej1v0ud 315 table 8-2. capture operation of cr0n0 and cr0n1 registers external input signal capture operation ti0n0 pin input ti0n1 pin input set values of esn01 and esn00 position of edge to be captured set values of esn11 and esn10 position of edge to be captured 01: rising 01: rising 00: falling 00: falling crc0n1 bit = 1 ti0n0 pin input (reverse phase) 11: both edges (cannot be captured) crc0n1 bit = 0 ti0n1 pin input 11: both edges capture operation of cr0n0 register interrupt signal inttm0n0 signal is not generated even if value is captured. interrupt signal inttm0n0 signal is generated each time value is captured. set values of esn01 and esn00 position of edge to be captured 01: rising 00: falling ti0n0 pin input note 11: both edges capture operation of cr0n1 register interrupt signal inttm0n1 signal is generated each time value is captured. note the capture operation of the cr0n1 register is not affected by the setting of the crc0n1 bit. caution to capture the count value of the tm0n regi ster to the cr0n0 regist er by using the phase reverse to that input to the ti 0n0 pin, the interrupt request si gnal (inttm0n0) is not generated after the value has been captured . if the valid edge is detect ed on the ti0n1 pin during this operation, the capture operation is not performe d but the inttm0n0 signal is generated as an external interrupt signal. to not use the external interrupt, mask the inttm0n0 signal. remarks 1. crc0n1: see 8.3 (2) capture/compare control register 0n (crc0n) . esn11, esn10, esn01, esn00: see 8.3 (4) prescaler mode register 0n (prm0n) . 2. n = 0 to 5 chapter 8 16-bit timer/event counter 0 preliminary user?s manual u17702ej1v0ud 316 8.3 registers registers used to control 16-bit time r/event counter 0n are shown below. ? 16-bit timer mode control register 0n (tmc0n) ? capture/compare contro l register 0n (crc0n) ? 16-bit timer output control register 0n (toc0n) ? prescaler mode register 0n (prm0n) ? selector operation control register 1 (selcnt1) remark to use the ti0n0, ti0n1, and to0n pin functions, refer to table 4-19 settings when port pins are used for alternate functions . (1) 16-bit timer mode cont rol register 0n (tmc0n) tmc0n is an 8-bit register that sets the 16-bit time r/event counter 0n operation mo de, the tm0n register clear mode, and output timing, and detects an overflow. rewriting tmc0n is prohibited during operation (when the tmc0n3 and tmc0n2 bits = other than 00). however, it can be changed when the tmc0n3 and tmc0n2 bits are cleared to 00 (stopping operation) and when the ovf0n bit is cleared to 0. this register can be read or writt en in 8-bit or 1-bit units. reset sets this register to 00h. cautions 1. 16-bit timer/event counter 0n starts operation at the moment tmc0n2 and tmc0n3 are set to values other than 00 (operation stop mode), resp ectively. set tmc0n2 and tmc0n3 to 00 to stop the operation. 2. do not access the tmc0n re gister when the main clock is stopped and the subclock is operating. for details, refer to 3.4.8 (1) (b). remark n = 0 to 5 chapter 8 16-bit timer/event counter 0 preliminary user?s manual u17702ej1v0ud 317 after reset: 00h r/w address: tmc00 fffff606h, tmc01 fffff616h, tmc02 fffff626h tmc03 fffff636h, tmc04 fffff646h, tmc05 fffff656h 7 6 5 4 3 2 1 <0> tmc0n 0 0 0 0 tmc0n3 tmc0n2 tmc0n1 ovf0n (n = 0 to 5) tmc0n3 tmc0n2 enable operation of 16-bit timer/event counter 0n 0 0 disables tm0n operation. stops suppl ying operating clock. clears 16-bit timer counter (tm0n). 0 1 free-running timer mode 1 0 clear & start mode entered by ti0n0 pin valid edge input note 1 1 1 clear & start mode entered upon a match between tm0n and cr0n0 tmc0n1 note 2 condition to reverse timer output (to0n) 0 ? match between tm0n and cr0n0 or match between tm0n and cr0n1 1 ? match between tm0n and cr0n0 or match between tm0n and cr0n1 ? trigger input of ti0n0 pin valid edge ovf0n tm0n register overflow flag clear (0) clears ovf0n to 0 or tmc0n.tmc0n3 and tmc0n.tmc0n2 = 00 set (1) overflow occurs. ovf0n is set to 1 when the value of tm0n changes from ffffh to 0000h in all the operation modes (free-running timer mode, clear & start mode entered by ti0n0 pin valid edge input, and clear & start mode entered upon a match between tm0n and cr0n0). it can also be set to 1 by writing 1 to the ovf0n bit. notes 1. the ti0n0 pin valid edge is set by the prm0n register. 2. be sure to clear the tmc0m1 bit to 0 when the to0m pin and ti0m0 pin are used alternately (m = 0 to 3). chapter 8 16-bit timer/event counter 0 preliminary user?s manual u17702ej1v0ud 318 (2) capture/compare control register 0n (crc0n) the crc0n register is the register that controls the operation of the cr0n0 and cr0n1 registers. changing the value of the crc0n register is prohib ited during operation (when the tmc0n.tmc0n3 and tmc0n.tmc0n2 bits = other than 00). this register can be read or writt en in 8-bit or 1-bit units. reset sets this register to 00h. after reset: 00h r/w address: crc00 fffff608h, crc01 fffff618h, crc02 fffff628h crc03 fffff638h, crc04 fffff648h, crc05 fffff658h 7 6 5 4 3 2 1 0 crc0n 0 0 0 0 0 crc0n2 crc0n1 crc0n0 (n = 0 to 5) crc0n2 cr0n1 register operating mode selection 0 operates as compare register 1 operates as capture register crc0n1 cr0n0 register capt ure trigger selection 0 captures on valid edge of ti0n1 pin 1 captures on valid edge of ti0n0 pin by reverse phase note the valid edge of the ti0n1 and ti0n0 pin is set by the prm0n register. if prm0n.esn01 and prm0n.esn00 are set to 11 (both edges) when crc0n1 is 1, the valid edge of the ti0n0 pin cannot be detected. crc0n0 cr0n0 register operating mode selection 0 operates as compare register 1 operates as capture register if tmc0n3 and tmc0n2 are set to 11 (clear & start mode entered upon a match between tm0n and cr0n0), be sure to set the crc0n0 bit to 0. note when the valid edge is detected from the ti0n1 pin, the capture oper ation is not performed but the inttm0n0 signal is generated as an external interrupt signal. caution to ensure that the capture operation is pe rformed properly, the cap ture trigger requires a pulse two cycles longer than th e count clock selected by th e prm0n or selcnt1 register. chapter 8 16-bit timer/event counter 0 preliminary user?s manual u17702ej1v0ud 319 (3) 16-bit timer output control register 0n (toc0n) the toc0n register is an 8-bit register that controls the to0n pin output. the toc0n register can be rewritt en while only the ospt0n bit is oper ating (when the tmc0n.tmc0n3 and tmc0n.tmc0n2 bits = other than 00). rewriting t he other bits is prohibited during operation. however, toc0n4 can be rewritten during timer operati on as a means to rewrite the cr0n1 register (see 8.5.1 rewriting cr0n1 register during tm0n operation ). this register can be read or writt en in 8-bit or 1-bit units. reset sets this register to 00h. caution be sure to set the toc0n regi ster using the following procedure. <1> set the toc0n4 a nd toc0n1 bits to 1. <2> set only the toe0n bit to 1. <3> set either of the l vs0n or lvr0n bits to 1. (1/2) after reset: 00h r/w address: toc00 fffff609h, toc01 fffff619h, toc02 fffff629h, toc03 fffff639h, toc04 fffff649h, toc05 fffff659h 7 <6> <5> 4 <3> <2> 1 <0> toc0n 0 ospt0n ospe0n toc0n4 lvs0n lvr0n toc0n1 toe0n (n = 0 to 5) ospt0n one-shot pulse out put trigger via software 0 ? 1 one-shot pulse output the value of this bit is always ?0? when it is read. if it is set to 1, tm0n is cleared and started. ospe0n one-shot pulse output operation control 0 successive pulse output 1 one-shot pulse output one-shot pulse output operates correctly in the fr ee-running timer mode or clear & start mode entered by ti0n0 pin valid edge input. the one-shot pulse cannot be output in the clear & start mode entered upon a match between the tm0n and cr0n0 registers. toc0n4 to0n pin output control on match between cr0n1 and tm0n registers 0 disables inversion operation 1 enables inversion operation the interrupt signal (inttm0n1) is generated even when the toc0n4 bit = 0. chapter 8 16-bit timer/event counter 0 preliminary user?s manual u17702ej1v0ud 320 (2/2) lvs0n lvr0n setting of to0n pin output status 0 0 no change 0 1 initial value of to0n pin output is low level (to0n pin output is cleared to 0). 1 0 initial value of to0n pin output is high level (to0n pin output is set to 1). 1 1 setting prohibited ? the lvs0n and lvr0n bits can be used to set the initial value of the output level of the to0n pin. if the initial value does not have to be set, leave the lvs0n and lvr0n bits as 00n. ? be sure to set the lvs0n and lvr0n bits when toe0n = 1. the lvs0n, lvr0n, and toe0n bits being simultaneously set to 1 is prohibited. ? the lvs0n and lvr0n bits are trigger bits. by sett ing these bits to 1, the initial value of the output level of the to0n pin can be set. even if these bits are cleared to 0, output of the to0n pin is not affected. ? the values of the lvs0n and lvr0n bits are always 0 when they are read. ? for how to set the lvs0n and lvr0n bits, see 8.5.2 setting lvs0n and lvr0n bits . toc0n1 to0n pin output control on match between cr0n0 and tm0n registers 0 disables inversion operation 1 enables inversion operation the interrupt signal (inttm0n0) is generated even when the toc0n1 bit = 0. toe0n to0n pin output control 0 disables output (to0n pin output fixed to low level) 1 enables output chapter 8 16-bit timer/event counter 0 preliminary user?s manual u17702ej1v0ud 321 (4) prescaler mode register 0n (prm0n) the prm0n register is the register that sets the tm0n register count clock and ti0n0 and ti0n1 pin input valid edges. the prm0n1 and prm0n0 bits are set in combination with the selcnt1.isel1n bit. refer to 8.3 (6) count clock setting for 16-bit timer/event counter 0n for details. rewriting the prm0n register is pr ohibited during operation (when the tm c0n.tmc0n3 and tmc0n.tmc0n2 bits = other than 00). this register can be read or writt en in 8-bit or 1-bit units. reset sets this register to 00h. cautions 1. do not apply the following setting wh en setting the prm0n1 and prm0n0 bits to 11 (to specify the valid edge of th e ti0n0 pin as a count clock). ? clear & start mode entered by the ti0n0 pin valid edge ? setting the ti0n0 pin as a capture trigger 2. if the operation of the 16- bit timer/event counter 0n is enab led when the ti0n0 or ti0n1 pin is at high level and when the va lid edge of the ti0n0 or ti0n1 pi n is specified to be the rising edge or both edges, the high level of the ti0n 0 or ti0n1 pin is detected as a rising edge. note this when the ti0n0 or ti 0n1 pin is pulled up. however, th e rising edge is not detected when the timer operation has been once stopped and is then enabled again. 3. when the p33, p35, p92, and p94 pins are used as the valid edges of ti000, ti010, ti020, and ti030, and the timer output function is used, set the p34, p32, p30, and p31 pins as the timer output pins (to00 to to03). (n = 0 to 5) esn11 esn10 ti0n1 pin valid edge selection 0 0 falling edge 0 1 rising edge 1 0 setting prohibited 1 1 both falling and rising edges esn01 esn00 ti0n0 pin valid edge selection 0 0 falling edge 0 1 rising edge 1 0 setting prohibited 1 1 both falling and rising edges after reset: 00h r/w address: prm00 fffff607h, prm01 fffff617h, prm02 fffff627h, prm03 fffff637h, prm04 fffff647h, prm05 fffff657h 7 6 5 4 3 2 1 0 prm0n esn11 esn10 esn01 esn00 0 0 prm0n1 prm0n0 chapter 8 16-bit timer/event counter 0 preliminary user?s manual u17702ej1v0ud 322 (5) selector operation control register 1 (selcnt1) the selcnt1 register sets the count cl ock of 16-bit timer/event counter 0n. the selcnt1 register is set in combination with th e prm0n.prmn01 and prm0n.prmn00 bits. refer to 8.3 (6) count clock setting for 16-bit timer/event counter 0n for details. this register can be read or writt en in 8-bit or 1-bit units. reset sets this register to 00h. 0 selcnt1 0 isel15 isel14 isel13 isel12 isel11 isel10 after reset: 00h r/w address: fffff30ah 76 54 32 1 0 (6) count clock setting for 16- bit timer/event counter 0n the count clock for 16-bit timer/event counter 0n is set by using the prm0n.pr m0n1, prm0n.prm0n0, and selcnt1.isel1n bits in combination. (a) count clock for 16-bit timer/event counters 00 and 02 selcnt1 register prm0n register selection of count clock note 1 isel1n bit prm0n1 bit prm0n0 bit count clock f xx = 20 mhz f xx = 16 mhz f xx = 10 mhz 0 0 0 f xx /2 100 ns 125 ns 200 ns 0 0 1 f xx /4 200 ns 250 ns 400 ns 0 1 0 f xx /8 400 ns 500 ns 800 ns 0 1 1 valid edge of ti0n0 note 2 ? ? ? 1 0 0 f xx /32 1.6 s 2.0 s 3.2 s 1 0 1 f xx /64 3.2 s 4.0 s 6.4 s 1 1 0 f xx /128 6.4 s 8.0 s 12.8 s 1 1 1 setting prohibited notes 1. when the internal clock is selected, set so as to satisfy the following conditions: v dd = regc = 4.0 to 5.5 v: count clock 10 mhz v dd = 4.0 to 5.5 v, regc = 10 f: count clock 5 mhz v dd = regc = 2.7 to 4.0 v: count clock 5 mhz 2. the external clock requires a pulse lon ger than two cycles of the internal clock (f xx /4). remark n = 0 or 2 chapter 8 16-bit timer/event counter 0 preliminary user?s manual u17702ej1v0ud 323 (b) count clock for 16-bit timer/event counter 01 selcnt1 register prm01 register selection of count clock note 1 isel11 bit prm011 bit prm010 bit count clock f xx = 20 mhz f xx = 16 mhz f xx = 10 mhz 0 0 0 f xx setting prohibited setting prohibited 100 ns 0 0 1 f xx /4 200 ns 250 ns 400 ns 0 1 0 intwt ? ? ? 0 1 1 valid edge of ti010 note 2 ? ? ? 1 0 0 f xx /2 100 ns 125 ns 200 ns 1 0 1 f xx /8 400 ns 500 ns 800 ns 1 1 0 f xx /16 800 ns 1.0 s 1.6 s 1 1 1 setting prohibited notes 1. when the internal clock is selected, set so as to satisfy the following conditions: v dd = regc = 4.0 to 5.5 v: count clock 10 mhz v dd = 4.0 to 5.5 v, regc = 10 f: count clock 5 mhz v dd = regc = 2.7 to 4.0 v: count clock 5 mhz 2. the external clock requires a pulse lon ger than two cycles of the internal clock (f xx /4). (c) count clock for 16-bit timer/event counter 03 selcnt1 register prm03 register selection of count clock note 1 isel13 bit prm031 bit prm030 bit count clock f xx = 20 mhz f xx = 16 mhz f xx = 10 mhz 0 0 0 f xx /4 200 ns 250 ns 400 ns 0 0 1 f xx /16 800 ns 1.0 s 1.6 s 0 1 0 f xx /512 25.6 s 32.0 s 51.2 s 0 1 1 valid edge of ti030 note 2 ? ? ? 1 0 0 f xx setting prohibited setting prohibited 100 ns 1 0 1 f xx /2 100 ns 125 ns 200 ns 1 1 0 f xx /8 400 ns 500 ns 800 ns 1 1 1 setting prohibited notes 1. when the internal clock is selected, set so as to satisfy the following conditions: v dd = regc = 4.0 to 5.5 v: count clock 10 mhz v dd = 4.0 to 5.5 v, regc = 10 f: count clock 5 mhz v dd = regc = 2.7 to 4.0 v: count clock 5 mhz 2. the external clock requires a pulse lon ger than two cycles of the internal clock (f xx /4). chapter 8 16-bit timer/event counter 0 preliminary user?s manual u17702ej1v0ud 324 (d) count clock for 16-bit timer/event counter 04 selcnt1 register prm04 register selection of count clock note 1 isel14 bit prm041 bit prm040 bit count clock f xx = 20 mhz f xx = 16 mhz f xx = 10 mhz 0 0 0 f xx /2 100 ns 125 ns 200 ns 0 0 1 f xx /4 200 ns 250 ns 400 ns 0 1 0 f xx /8 400 ns 500 ns 800 ns 0 1 1 valid edge of ti040 note 2 ? ? ? 1 0 0 f xx /32 1.6 s 2.0 s 3.2 s 1 0 1 f xx /64 3.2 s 4.0 s 6.4 s 1 1 0 f xx /512 25.6 s 32.0 s 51.2 s 1 1 1 setting prohibited notes 1. when the internal clock is selected, set so as to satisfy the following conditions: v dd = regc = 4.0 to 5.5 v: count clock 10 mhz v dd = 4.0 to 5.5 v, regc = 10 f: count clock 5 mhz v dd = regc = 2.7 to 4.0 v: count clock 5 mhz 2. the external clock requires a pulse lon ger than two cycles of the internal clock (f xx /4). (e) count clock for 16-bit timer/event counter 05 selcnt1 register prm05 register selection of count clock note 1 isel15 bit prm051 bit prm050 bit count clock f xx = 20 mhz f xx = 16 mhz f xx = 10 mhz 0 0 0 f xx setting prohibited setting prohibited 100 ns 0 0 1 f xx /4 200 ns 250 ns 400 ns 0 1 0 f xx /256 12.8 s 16.0 s 25.6 s 0 1 1 valid edge of ti050 note 2 ? ? ? 1 0 0 f xx /2 100 ns 125 ns 200 ns 1 0 1 f xx /8 400 ns 500 ns 800 ns 1 1 0 f xx /16 800 ns 1.0 s 1.6 s 1 1 1 setting prohibited notes 1. when the internal clock is selected, set so as to satisfy the following conditions: v dd = regc = 4.0 to 5.5 v: count clock 10 mhz v dd = 4.0 to 5.5 v, regc = 10 f: count clock 5 mhz v dd = regc = 2.7 to 4.0 v: count clock 5 mhz 2. the external clock requires a pulse lon ger than two cycles of the internal clock (f xx /4). chapter 8 16-bit timer/event counter 0 preliminary user?s manual u17702ej1v0ud 325 8.4 operation 8.4.1 interval timer operation if the tmc0n.tmc0n3 and tmc0n.tmc0n2 bits are set to 11 (clear & start mode entered upon a match between the tm0n register and the cr0n0 register), the count operation is started in synchronization with the count clock. when the value of the tm0n register late r matches the value of the cr0n0 regist er, the tm0n register is cleared to 0000h and a match interrupt signal (inttm0n0) is generat ed. this inttm0n0 signal enables the tm0n register to operate as an interval timer. remarks 1. for the alternate-function pin settings, refer to table 4-19 settings when port pins are used for alternate functions . 2. for enabling the inttm0n0 interrupt, refer to chapter 21 interrupt/exception processing function . figure 8-2. block diagram of interval timer operation 16-bit counter (tm0n) cr0n0 register operable bits tmc0n3, tmc0n2 count clock clear match signal inttm0n0 signal remark n = 0 to 5 figure 8-3. basic timing exampl e of interval timer operation tm0n register 0000h operable bits (tmc0n3, tmc0n2) compare register (cr0n0) compare match interrupt (inttm0n0) n 11 00 n n n n interval (n + 1) interval (n + 1) interval (n + 1) interval (n + 1) remark n = 0 to 5 chapter 8 16-bit timer/event counter 0 preliminary user?s manual u17702ej1v0ud 326 figure 8-4. example of register se ttings for interval timer operation (a) 16-bit timer mode cont rol register 0n (tmc0n) 00001100 tmc0n3 tmc0n2 tmc0n1 ovf0n clears and starts on match between tm0n and cr0n0. (b) capture/compare cont rol register 0n (crc0n) 00000000 crc0n2 crc0n1 crc0n0 cr0n0 used as compare register (c) 16-bit timer output control register 0n (toc0n) 00000 lvr0n lvs0n toc0n4 ospe0n ospt0n toc0n1 toe0n 000 (d) prescaler mode register 0n (prm0n), sel ector operation control register 1 (selcnt1) 0 prm0n 0 0 0 0 prm0n1 prm0n0 selcnt1 esn11 esn10 esn01 esn00 selects count clock. 0 0/1 0/1 isel1n 0/1 (e) 16-bit timer counter 0n (tm0n) by reading the tm0n register, the count value can be read. (f) 16-bit capture/compare register 0n0 (cr0n0) if m is set to the cr0n0 register, the interval time is as follows. ? interval time = (m + 1) count clock cycle setting the cr0n0 register to 0000h is prohibited. (g) 16-bit capture/compare register 0n1 (cr0n1) usually, the cr0n1 register is not used for the interval timer function. however, a compare match interrupt (inttm0n1) is generated when the set value of the cr0n1 register matches the value of the tm0n register. therefore, mask the interrupt request by using the interrupt mask flag (tm0mkn1). remark n = 0 to 5 chapter 8 16-bit timer/event counter 0 preliminary user?s manual u17702ej1v0ud 327 figure 8-5. example of software pr ocessing for interval timer function tm0n register 0000h operable bits (tmc0n3, tmc0n2) compare register (cr0n0) compare match interrupt (inttm0n0) n 11 00 00 n n n <1> <2> tmc0n3, tmc0n2 bits = 11 tmc0n3, tmc0n2 bits = 00 register initial setting prm0n register, selcnt1 register, crc0n register, cr0n0 register, port setting initial setting of these registers is performed before setting the tmc0n3 and tmc0n2 bits to 11. starts count operation the counter is initialized and counting is stopped by clearing the tmc0n3 and tmc0n2 bits to 00. start stop <1> count operation start flow <2> count operation stop flow remark n = 0 to 5 chapter 8 16-bit timer/event counter 0 preliminary user?s manual u17702ej1v0ud 328 8.4.2 square wave output operation when 16-bit timer/event counter 0n operates as an interval timer (see 8.4.1 ), a square wave can be output from the to0n pin by setting the toc0n register to 03h. when the tmc0n.tmc0n3 and tmc0n.tmc0n2 bits are set to 11 (count clear & start mode entered upon a match between the tm0n register and the cr0n0 register), the c ounting operation is started in synchronization with the count clock. when the value of the tm0n register late r matches the value of the cr0n0 regist er, the tm0n register is cleared to 0000h, an interrupt signal (inttm0n0) is generated, and output of the to0n pin is invert ed. this to0n pin output that is inverted at fixed interval s enables to0n to output a square wave. remarks 1. for the alternate-function pin settings, refer to table 4-19 settings when port pins are used for alternate functions . 2. for enabling the inttm0n0 interrupt, refer to chapter 21 interrupt/exception processing function . figure 8-6. block diagram of square wave output operation 16-bit counter (tm0n) cr0n0 register operable bits tmc0n3, tmc0n2 count clock clear match signal inttm0n0 signal output controller to0n pin remark n = 0 to 5 figure 8-7. basic timing example of square wave output operation tm0n register 0000h operable bits (tmc0n3, tmc0n2) compare register (cr0n0) to0n pin output compare match interrupt (inttm0n0) n 11 00 n n n n interval (n + 1) interval (n + 1) interval (n + 1) interval (n + 1) remark n = 0 to 5 chapter 8 16-bit timer/event counter 0 preliminary user?s manual u17702ej1v0ud 329 figure 8-8. example of register setti ngs for square wave output operation (a) 16-bit timer mode cont rol register 0n (tmc0n) 00001100 tmc0n3 tmc0n2 tmc0n1 ovf0n clears and starts on match between tm0n and cr0n0. (b) capture/compare cont rol register 0n (crc0n) 00000000 crc0n2 crc0n1 crc0n0 cr0n0 used as compare register (c) 16-bit timer output control register 0n (toc0n) 0 0 0 0 0/1 lvr0n lvs0n toc0n4 ospe0n ospt0n toc0n1 toe0n enables to0n pin output. inverts to0n pin output on match between tm0n and cr0n0. specifies the initial value of to0n output f/f. 0/1 1 1 (d) prescaler mode register 0n (prm0n), sel ector operation control register 1 (selcnt1) 0 prm0n 0 0 0 0 prm0n1 prm0n0 selcnt1 esn11 esn10 esn01 esn00 selects count clock. 0 0/1 0/1 isel1n 0/1 (e) 16-bit timer counter 0n (tm0n) by reading the tm0n register, the count value can be read. (f) 16-bit capture/compare register 0n0 (cr0n0) if m is set to the cr0n0 register, the square wave frequency is as follows. 1 / [2 (m + 1) count clock cycle] setting the cr0n0 register to 0000h is prohibited. (g) 16-bit capture/compare register 0n1 (cr0n1) usually, the cr0n1 register is not used for the square wave output func tion. however, a compare match interrupt (inttm0n1) is generated when the set val ue of the cr0n1 register ma tches the value of the tm0n register. therefore, mask the interrupt request by using the interrupt mask flag (tm0mkn1). remark n = 0 to 5 chapter 8 16-bit timer/event counter 0 preliminary user?s manual u17702ej1v0ud 330 figure 8-9. example of software proc essing for square wave output function tm0n register 0000h operable bits (tmc0n3, tmc0n2) compare register (cr0n0) to0n pin output compare match interrupt (inttm0n0) to0n output control bit (toc0n1, toe0n) n 11 00 00 n n n <1> <2> tmc0n3, tmc0n2 bits = 11 tmc0n3, tmc0n2 bits = 00 register initial setting prm0n register, selcnt1 register, crc0n register, toc0n register note , cr0n0 register, port setting initial setting of these registers is performed before setting the tmc0n3 and tmc0n2 bits to 11. starts count operation. the counter is initialized and counting is stopped by clearing the tmc0n3 and tmc0n2 bits to 00. start stop <1> count operation start flow <2> count operation stop flow note care must be exercised when setting the toc0n register. for details, see 8.3 (3) 16-bit timer output control register 0n (toc0n) . remark n = 0 to 5 chapter 8 16-bit timer/event counter 0 preliminary user?s manual u17702ej1v0ud 331 8.4.3 external event counter operation when the prm0n.prm0n1 and prm0n.prm0n0 bits are set to 11 (for counting up with the valid edge of the ti0n0 pin) and the tmc0n.tmc0n3 and tmc0n.tm c0n2 bits are set to 11, the valid edge of an external event input is counted, and a match interrupt signal indicating matc hing between the tm0n register and the cr0n0 register (inttm0n0) is generated. to input the external event, the ti0n0 pin is used. th erefore, the timer/event co unter cannot be used as an external event counter in the clear & start mode entered by the ti0n0 pin va lid edge input (when the tmc0n3 and tmc0n2 bits = 10). the inttm0n0 signal is generated with the following timing. ? timing of generation of inttm0n0 signal (second time or later) = number of times of detection of valid edge of external event (set value of the cr0n0 register + 1) however, the first match interrupt immediately after the timer/event counter has start ed operating is generated with the following timing. ? number of times of detection of valid edge of external event input (set value of the cr0n0 register + 2) to detect the valid edge, the signal input to t he ti0n0 pin is sampled during the clock cycle of f prs . the valid edge is not detected until it is detected two times in a row. t herefore, a noise with a short pul se width can be eliminated. remarks 1. for the alternate-function pin (ti0n0) settings, refer to table 4-19 settings when port pins are used for alternate functions . 2. for enabling the inttm0n0 interrupt, refer to chapter 21 interrupt/exception processing function . figure 8-10. block diagram of ex ternal event counter operation 16-bit counter (tm0n) cr0n0 register operable bits tmc0n3, tmc0n2 clear match signal inttm0n0 signal f xx /4 edge detection ti0n0 pin output controller to0n pin remark n = 0 to 5 chapter 8 16-bit timer/event counter 0 preliminary user?s manual u17702ej1v0ud 332 figure 8-11. example of register setti ngs in external event counter mode (a) 16-bit timer mode cont rol register 0n (tmc0n) 00001100 tmc0n3 tmc0n2 tmc0n1 ovf0n clears and starts on match between tm0n and cr0n0. (b) capture/compare cont rol register 0n (crc0n) 00000000 crc0n2 crc0n1 crc0n0 cr0n0 used as compare register (c) 16-bit timer output control register 0n (toc0n) 0 0 0 0/1 0/1 lvr0n lvs0n toc0n4 ospe0n ospt0n toc0n1 toe0n 0: disables to0n output. 1: enables to0n output. 00: does not invert to0n output on match between tm0n and cr0n0/cr0n1. 01: inverts to0n output on match between tm0n and cr0n0. 10: inverts to0n output on match between tm0n and cr0n1. 11: inverts to0n output on match between tm0n and cr0n0/cr0n1. specifies initial value of to0n output f/f. 0/1 0/1 0/1 (d) prescaler mode register 0n (prm0n), sel ector operation control register 1 (selcnt1) 0 prm0n 0 0/1 0/1 0 prm0n1 prm0n0 isel1n esn11 esn10 esn01 esn00 selects count clock (specifies valid edge of ti0n0). 00: falling edge detection 01: rising edge detection 10: setting prohibited 11: both edges detection 00 1 1 selcnt1 (e) 16-bit timer counter 0n (tm0n) by reading the tm0n register, the count value can be read. (f) 16-bit capture/compare register 0n0 (cr0n0) if m is set to the cr0n0 register, the interrupt signal (inttm0n0) is generated when the number of external events reaches (m + 1). setting the cr0n0 register to 0000h is prohibited. (g) 16-bit capture/compare register 0n1 (cr0n1) when this register?s value matches the count value of the tm0n register, an interrupt signal (inttm0n1) is generated. the count value of t he tm0n register is not cleared. remark n = 0 to 5 chapter 8 16-bit timer/event counter 0 preliminary user?s manual u17702ej1v0ud 333 figure 8-12. example of software proce ssing in external event counter mode compare register (cr0n0) operable bits (tmc0n3, tmc0n2) 0000h tm0n register to0n pin output compare match interrupt (inttm0n0) to0n output control bit (toc0n4, toc0n1, toe0n) tmc0n3, tmc0n2 bits = 11 tmc0n3, tmc0n2 bits = 00 register initial setting prm0n register, selcnt1 register, crc0n register, toc0n register note , cr0n0 register, port setting initial setting of these registers is performed before setting the tmc0n3 and tmc0n2 bits to 11. starts count operation. the counter is initialized and counting is stopped by clearing the tmc0n3 and tmc0n2 bits to 00. start stop <1> count operation start flow <2> count operation stop flow 11 00 n n n n 00 <1> <2> note care must be exercised when setting the toc0n register. for details, see 8.3 (3) 16-bit timer output control register 0n (toc0n) . remark n = 0 to 5 chapter 8 16-bit timer/event counter 0 preliminary user?s manual u17702ej1v0ud 334 8.4.4 operation in clear & start mode entered by ti0n0 pin valid edge input when the tmc0n.tmc0n3 and tmc0n.tmc0n2 bits are set to 10 (clear & start mode entered by the ti0n0 pin valid edge input) and the count clock (set by the prm0n, selcnt1 registers) is supplied to the timer/event counter, the tm0n register starts counting up. when the valid edge of the ti0n0 pin is detected du ring the counting operation, the tm0n register is cleared to 0000h and starts counting up again. if the valid edge of the ti0n0 pin is not detected, the tm0n register overflow s and continues counting. the valid edge of the ti0n0 pin is a cause to clear th e tm0n register. starting t he counter is not controlled immediately after the st art of the operation. the cr0n0 and cr0n1 registers are used as compare registers and capture registers. (a) when the cr0n0 and cr0n1 regist ers are used as compare registers signals inttm0n0 and inttm0n1 are generated when the va lue of the tm0n register matches the value of the cr0n0 and cr0n1 registers. (b) when the cr0n0 and cr0n1 regist ers are used as capture registers the count value of the tm0n register is captur ed to the cr0n0 register and the inttm0n0 signal is generated when the valid edge is input to the ti0n1 pin (or when the pha se reverse to that of the valid edge is input to the ti0n0 pin). when the valid edge is input to the ti0n0 pin, the count va lue of the tm0n register is captured to the cr0n1 register and the inttm0n1 signal is generated. as s oon as the count value has been captured, the counter is cleared to 0000h. caution do not set the count clock as the valid edge of the ti0n0 pin (rpm0n.prm0n1 and rpm0n.prm0n0 bits = 11). when the prm0n1 a nd prm0n0 bits = 11, the tm0n register is cleared. remarks 1. for the alternate-function pin settings, refer to table 4-19 settings when port pins are used for alternate functions . 2. for enabling the inttm0n0 interrupt, refer to chapter 21 interrupt/exception processing function . chapter 8 16-bit timer/event counter 0 preliminary user?s manual u17702ej1v0ud 335 (1) operation in clear & start mode en tered by ti0n0 pin valid edge input (cr0n0 register: compare register , cr0n1 register: compare register) figure 8-13. block diagram of clear & start mode entered by ti0n0 pin valid edge input (cr0n0 register: compare register , cr0n1 register: compare register) 16-bit counter (tm0n) clear output controller edge detection compare register (cr0n1) match signal to0n pin match signal interrupt signal (inttm0n0) interrupt signal (inttm0n1) ti0n0 pin compare register (cr0n0) operable bits tmc0n3, tmc0n2 count clock remark n = 0 to 5 chapter 8 16-bit timer/event counter 0 preliminary user?s manual u17702ej1v0ud 336 figure 8-14. timing example of clear & star t mode entered by ti0n0 pin valid edge input (cr0n0 register: compare register , cr0n1 register: compare register) (a) toc0n = 13h, prm0n = 10h, crc0n = 00h, tmc0n = 08h tm0n register 0000h operable bits (tmc0n3, tmc0n2) count clear input (ti0n0 pin input) compare register (cr0n0) compare match interrupt (inttm0n0) compare register (cr0n1) compare match interrupt (inttm0n1) to0 n pin output m 10 m nn nn mmm 00 n (b) toc0n = 13h, prm0n = 10h, crc0n, = 00h, tmc0n = 0ah tm0n register 0000h operable bits (tmc0n3, tmc0n2) count clear input (ti0n0 pin input) compare register (cr0n0) compare match interrupt (inttm0n0) compare register (cr0n1) compare match interrupt (inttm0n1) to0n pin output m 10 m nn nn mmm 00 n (a) and (b) differ as follows depending on the setting of the tmc0n register. (a) the output level of the to0n pi n is inverted when the tm0n register matches a compare register. (b) the output level of the to0n pin is inverted w hen the tm0n register matches a compare register or when the valid edge of the ti0n0 pin is detected. remark n = 0 to 5 chapter 8 16-bit timer/event counter 0 preliminary user?s manual u17702ej1v0ud 337 (2) operation in clear & start mode en tered by ti0n0 pin valid edge input (cr0n0 register: compare register , cr0n1 register: capture register) figure 8-15. block diagram of clear & start mode entered by ti0n0 pin valid edge input (cr0n0 register: compare register, cr0n1 register: capture register) 16-bit counter (tm0n) clear output controller edge detector capture register (cr0n1) capture signal to0n pin match signal interrupt signal (inttm0n0) interrupt signal (inttm0n1) ti0n0 pin compare register (cr0n0) operable bits tmc0n3, tmc0n2 count clock remark n = 0 to 5 chapter 8 16-bit timer/event counter 0 preliminary user?s manual u17702ej1v0ud 338 figure 8-16. timing example of clear & star t mode entered by ti0n0 pin valid edge input (cr0n0 register: compare register, cr0n1 register: capture register) (1/2) (a) toc0n = 13h, prm0n = 10h, crc0n , = 04h, tmc0n = 08h, cr0n0 = 0000h tm0n register 0000h operable bits (tmc0n3, tmc0n2) capture & count clear input (ti0n0 pin input) compare register (cr0n0) compare match interrupt (inttm0n0) capture register (cr0n1) capture interrupt (inttm0n1) to0n pin output 0000h 10 q p n m s 00 0000h m n s p q this is an application example where the output level of t he to0n pin is inverted when the count value has been captured & cleared. the count value is captured to the cr0n1 register and the tm0n regist er is cleared (to 0000h) when the valid edge of the ti0n0 pin is det ected. when the count va lue of the tm0n register is 0000h, a compare match interrupt signal (inttm0n0) is generated, and t he output level of the to0n pin is inverted. remark n = 0 to 5 chapter 8 16-bit timer/event counter 0 preliminary user?s manual u17702ej1v0ud 339 figure 8-16. timing example of clear & star t mode entered by ti0n0 pin valid edge input (cr0n0 register: compare register, cr0n1 register: capture register) (2/2) (b) toc0n = 13h, prm0n = 10h, crc0n = 04h, tmc0n = 0ah, cr0n0 = 0003h tm0n register 0000h operable bits (tmc0n3, tmc0n2) capture & count clear input (ti0n0 pin input) compare register (cr0n0) compare match interrupt (inttm0n0) capture register (cr0n1) capture interrupt (inttm0n1) to0n pin output 0003h 0003h 10 q p n m s 00 0000h m 4444 ns pq this is an application exampl e where the width set to the cr0n0 register (4 clocks in this example) is to be output from the to0n pin when the count value has been captured & cleared. the count value is captured to t he cr0n1 register, a capture interrupt signal (inttm0n1) is generated, the tm0n register is cleared (to 0000h), and the output level of the to0n pin is inverted when the valid edge of the ti0n0 pin is detected. when the count value of the tm0n register is 0003h (four clocks have been counted), a compare match interrupt signal (inttm0n0) is generat ed and the output level of the to0n pin is inverted. remark n = 0 to 5 chapter 8 16-bit timer/event counter 0 preliminary user?s manual u17702ej1v0ud 340 (3) operation in clear & start mode en tered by ti0n0 pin valid edge input (cr0n0 register: capture register , cr0n1 register: compare register) figure 8-17. block diagram of clear & start mode entered by ti0n0 pin valid edge input (cr0n0 register: capture register , cr0n1 register: compare register) 16-bit counter (tm0n) clear output controller edge detection capture register (cr0n0) capture signal to0n pin match signal interrupt signal (inttm0n1) interrupt signal (inttm0n0) ti0n0 pin compare register (cr0n1) operable bits tmc0n3, tmc0n2 count clock remark n = 0 to 5 chapter 8 16-bit timer/event counter 0 preliminary user?s manual u17702ej1v0ud 341 figure 8-18. timing example of clear & start mode entered by ti0n0 pin valid edge input (cr0n0 register: capture register, cr0n1 register: compare register) (1/2) (a) toc0n = 13h, prm0n = 10h, crc0n = 03h, tmc0n = 08h, cr0n1 = 0000h 10 p n m s 00 l 0000h 0000h mns p tm0n register 0000h operable bits (tmc0n3, tmc0n2) capture & count clear input (ti0n0 pin input) capture register (cr0n0) capture interrupt (inttm0n0) compare register (cr0n1) compare match interrupt (inttm0n1) to0n pin output this is an application example where the output level of the to0n pin is to be inverted when the count value has been captured & cleared. the tm0n register is cleared at the rising edge detecti on of the ti0n0 pin and it is captured to the cr0n0 register at the falling edge detection of the ti0n0 pin. when the crc0n.crc0n1 bit is set to 1, the count valu e of the tm0n register is captured to cr0n0 in the phase reverse to that of the signal input to the ti0n0 pi n, but the capture interrupt signal (inttm0n0) is not generated. however, the inttm0n0 signal is generated when the valid edge of the ti0n1 pin is detected. mask the inttm0n0 signal when it is not used. remark n = 0 to 5 chapter 8 16-bit timer/event counter 0 preliminary user?s manual u17702ej1v0ud 342 figure 8-18. timing example of clear & star t mode entered by ti0n0 pin valid edge input (cr0n0 register: capture register, cr0n1 register: compare register) (2/2) (b) toc0n = 13h, prm0n = 10h, crc0n = 03h, tmc0n = 0ah, cr0n1 = 0003h tm0n register 0000h operable bits (tmc0n3, tmc0n2) capture & count clear input (ti0n0 pin input) compare register (cr0n0) compare match interrupt (inttm0n0) capture register (cr0n1) capture interrupt (inttm0n1) to0n pin output 0003h 0003h 10 p n m s 00 4444 l 0000h m n s p this is an application exampl e where the width set to the cr0n1 register (4 clocks in this example) is to be output from the to0n pin when the count value has been captured & cleared. the tm0n register is cleared (to 0000h) at the rising edge detection of the ti 0n0 pin and captured to the cr0n0 register at the falling edge detec tion of the ti0n0 pin. the output level of the to0n pin is inverted when the tm0n register is cleared (to 0000h) because the rising edge of the ti 0n0 pin has been detected or when the value of the tm0n register matches that of a compare register (cr0n1). when the crc0n.crc0n1 bit is 1, the count value of the tm0n register is captured to the cr0n0 register in the phase reverse to that of the input signal of the ti0n0 pin, but the captur e interrupt signal (inttm0n0) is not generated. however, the inttm0n0 inte rrupt is generated when the valid edg e of the ti0n1 pin is detected. mask the inttm0n0 signal when it is not used. remark n = 0 to 5 chapter 8 16-bit timer/event counter 0 preliminary user?s manual u17702ej1v0ud 343 (4) operation in clear & start mode en tered by ti0n0 pin valid edge input (cr0n0 register: capture register , cr0n1 register: capture register) figure 8-19. block diagram of clear & start mode entered by ti0n0 pin valid edge input (cr0n0 register: capture register , cr0n1 register: capture register) 16-bit counter (tm0n) clear output controller capture register (cr0n0) capture signal capture signal to0n pin interrupt signal (inttm0n1) interrupt signal (inttm0n0) capture register (cr0n1) operable bits tmc0n3, tmc0n2 count clock edge detection ti0n0 pin edge detection ti0n1 pin selector remark n = 0 to 5 chapter 8 16-bit timer/event counter 0 preliminary user?s manual u17702ej1v0ud 344 figure 8-20. timing example of clear & start mode entered by ti0n0 pin valid edge input (cr0n0 register: capture register, cr0n1 register: capture register) (1/3) (a) toc0n = 13h, prm0n = 30h , crc0n = 05h, tmc0n = 0ah tm0n register 0000h operable bits (tmc0n3, tmc0n2) capture & count clear input (ti0n0 pin input) capture register (cr0n0) capture interrupt (inttm0n0) capture register (cr0n1) capture interrupt (inttm0n1) to0n pin output 10 r s t o l m n p q 00 l 0000h 0000h lm nopqrst this is an application example where t he count value is captured to the cr0 n1 register, the tm0n register is cleared, and the to0n pin output is inverted when the rising or falling edge of t he ti0n0 pin is detected. when the edge of the ti0n1 pin is det ected, an interrupt signal (inttm 0n0) is generated. mask the inttm0n0 signal when it is not used. remark n = 0 to 5 chapter 8 16-bit timer/event counter 0 preliminary user?s manual u17702ej1v0ud 345 figure 8-20. timing example of clear & start mode entered by ti0n0 pin valid edge input (cr0n0 register: capture register, cr0n1 register: capture register) (2/3) (b) toc0n = 13h, prm0n = c0h, crc0n = 05h, tmc0n = 0ah tm0n register 0000h operable bits (tmc0n3, tmc0n2) capture trigger input (ti0n1 pin input) capture register (cr0n0) capture interrupt (inttm0n0) capture & count clear input (ti0n0) capture register (cr0n1) capture interrupt (inttm0n1) to0n pin output 10 r s t o l m n p q 00 ffffh l l l 0000h 0000h lmn o pq r s t this is a timing example where an edge is not input to t he ti0n0 pin, in an application where the count value is captured to the cr0n0 register when the rising or falling edge of the ti0n1 pin is detected. because the to0n0 pin does not detect any edges, the to0n pin output is not inverted and remains low level. remark n = 0 to 5 chapter 8 16-bit timer/event counter 0 preliminary user?s manual u17702ej1v0ud 346 figure 8-20. timing example of clear & start mode entered by ti0n0 pin valid edge input (cr0n0 register: capture register, cr0n1 register: capture register) (3/3) (c) toc0n = 13h, prm0n = 00h , crc0n = 07h, tmc0n = 0ah tm0n register 0000h operable bits (tmc0n3, tmc0n2) capture & count clear input (ti0n0 pin input) capture register (cr0n0) capture register (cr0n1) capture interrupt (inttm0n1) to0n pin output capture input (ti0n1) capture interrupt (inttm0n0) 0000h 10 p o m q r t s w n l 00 l l ln r pt 0000h moq sw this is an application example where the pulse width of the signal input to the ti0n0 pin is measured. by setting the crc0n register, the count value can be ca ptured to the cr0n0 register in the phase reverse to the falling edge of the ti0n0 pin (i.e., rising edge) and to the cr0n1 register at the falling edge of the ti0n0 pin. the high- and low-level widths of the input pulse can be calculated by the following expressions. ? high-level width = [cr0n1 register value] ? [cr0n0 register value] [count clock cycle] ? low-level width = [cr0n0 register value] [count clock cycle] if the reverse phase of the ti0n0 pin is selected as a trigger to capture the count value to the cr0n0 register, the inttm0n0 signal is not generated. read the val ues of the cr0n0 and cr0n1 registers to measure the pulse width immediately after the inttm0n1 signal is generated. however, if the valid edge specifi ed by the prm0n.esn11 and prm0n.esn10 bi ts is input to the ti0n1 pin, the count value is not captured but the inttm0n0 signal is ge nerated. to measure the pulse width of the ti0n0 pin, mask the inttm0n0 signal when it is not used. remark n = 0 to 5 chapter 8 16-bit timer/event counter 0 preliminary user?s manual u17702ej1v0ud 347 figure 8-21. example of register settings in clear & st art mode entered by ti0n0 pin valid edge input (1/2) (a) 16-bit timer mode cont rol register 0n (tmc0n) 0000100/10 tmc0n3 tmc0n2 tmc0n1 ovf0n clears and starts at valid edge input of ti0n0 pin. 0: inverts to0n output on match between cr0n0 and cr0n1. 1: inverts to0n output on match between cr0n0 and cr0n1 and valid edge of ti0n0 pin. (b) capture/compare cont rol register 0n (crc0n) 000000/10/10/1 crc0n2 crc0n1 crc0n0 0: cr0n0 used as compare register 1: cr0n0 used as capture register 0: cr0n1 used as compare register 1: cr0n1 used as capture register 0: ti0n1 pin is used as capture trigger of cr0n0. 1: reverse phase of ti0n0 pin is used as capture trigger of cr0n0. (c) 16-bit timer output control register 0n (toc0n) 0 0 0 0/1 0/1 lvr0n lvs0n toc0n4 ospe0n ospt0n toc0n1 toe0n 0: disables to0n output 1: enables to0n output 00: does not invert to0n output on match between tm0n and cr0n0/cr0n1. 01: inverts to0n output on match between tm0n and cr0n0. 10: inverts to0n output on match between tm0n and cr0n1. 11: inverts to0n output on match between tm0n and cr0n0/cr0n1. specifies initial value of to0n output f/f 0/1 0/1 0/1 remark n = 0 to 5 chapter 8 16-bit timer/event counter 0 preliminary user?s manual u17702ej1v0ud 348 figure 8-21. example of register settings in clear & st art mode entered by ti0n0 pin valid edge input (2/2) (d) prescaler mode register 0n (prm0n), sel ector operation control register 1 (selcnt1) 0/1 prm0n 0/1 0/1 0/1 0 prm0n1 prm0n0 esn11 esn10 esn01 esn00 count clock selection (setting ti0n0 valid edge is prohibited) 00: falling edge detection 01: rising edge detection 10: setting prohibited 11: both edges detection (setting prohibited when crc0n1 = 1) 00: falling edge detection 01: rising edge detection 10: setting prohibited 11: both edges detection 0 0/1 0/1 selcnt1 isel1n 0/1 (e) 16-bit timer counter 0n (tm0n) by reading the tm0n register, the count value can be read. (f) 16-bit capture/compare register 0n0 (cr0n0) when this register is used as a co mpare register and when its value ma tches the count value of the tm0n register, an interrupt signal (inttm0n0) is generated. the count value of the tm0n register is not cleared. to use this register as a capture register, select eit her the ti0n0 or ti0n1 pin input as a capture trigger. when the valid edge of the capt ure trigger is detected, t he count value of the tm0n r egister is stored in the cr0n0 register. (g) 16-bit capture/compare register 0n1 (cr0n1) when this register is used as a co mpare register and when its value ma tches the count value of the tm0n register, an interrupt signal (inttm0n1) is generated. the count value of the tm0n register is not cleared. when this register is used as a capt ure register, the ti0n0 pin input is us ed as a capture trigger. when the valid edge of the capture trigger is detected, the count value of the tm0n register is stored in the cr0n1 register. remark n = 0 to 5 chapter 8 16-bit timer/event counter 0 preliminary user?s manual u17702ej1v0ud 349 figure 8-22. example of software processing in clear & start mode entered by ti 0n0 pin valid edge input tm0n register 0000h operable bits (tmc0n3, tmc0n2) count clear input (ti0n0 pin input) compare register (cr0n0) compare match interrupt (inttm0n0) compare register (cr0n1) compare match interrupt (inttm0n1) to0n pin output m 10 m n n n n mmm 00 <1> <2> <2> <2> <3> <2> 00 n tmc0n3, tmc0n2 bits = 10 edge input to ti0n0 pin register initial setting prm0n register, selcnt1 register, crc0n register, toc0 n register note , cr0n0, cr0n1 registers, tmc0n.tmc0n1 bit, port setting initial setting of these registers is performed before setting the tmc0n3 and tmc0n2 bits to 10. starts count operation when the valid edge is input to the ti0n0 pin, the value of the tm0n register is cleared. start <1> count operation start flow <2> tm0n register clear & start flow tmc0n3, tmc0n2 bits = 00 the counter is initialized and counting is stopped by clearing the tmc0n3 and tmc0n2 bits to 00. stop <3> count operation stop flow note care must be exercised when setting the toc0n register. for details, see 8.3 (3) 16-bit timer output control register 0n (toc0n) . remark n = 0 to 5 chapter 8 16-bit timer/event counter 0 preliminary user?s manual u17702ej1v0ud 350 8.4.5 free-running timer operation when the tmc0n.tmc0n3 and tmc0n.tmc0n2 bits are set to 01 (free-running timer mode), 16-bit timer/event counter 0n continues counting up in synchronization with t he count clock. when it has counted up to ffffh, the overflow flag (tmc0n.ovf0n bit) is set to 1 at the nex t clock, and the tm0n register is cleared (to 0000h) and continues counting. clear the ovf0n bit to 0 by executing the clr instruction via software. the following three types of free-runn ing timer operations are available. ? both the cr0n0 and cr0n1 register s are used as compare registers. ? either of the cr0n0 or cr0n1 regist ers is used as a compare register and the other is used as a capture register. ? both the cr0n0 and cr0n1 register s are used as capture registers. remarks 1. for the alternate-function pin (to0n) settings, refer to table 4-19 settings when port pins are used for alternate functions . 2. for enabling the inttm0n0 and inttm0n1 interrupts, refer to chapter 21 interrupt/exception processing function . (1) free-running timer mode operation (cr0n0 register: compare register , cr0n1 register: compare register) figure 8-23. block diagram of free-running timer mode (cr0n0 register: compare register, cr0n1 register: compare register) 16-bit counter (tm0n) output controller compare register (cr0n1) match signal to0n pin match signal interrupt signal (inttm0n0) interrupt signal (inttm0n1) compare register (cr0n0) operable bits tmc0n3, tmc0n2 count clock remark n = 0 to 5 chapter 8 16-bit timer/event counter 0 preliminary user?s manual u17702ej1v0ud 351 figure 8-24. timing example of free-running timer mode (cr0n0 register: compare register, cr0n1 register: compare register) ? toc0n = 13h, prm0n = 00h, crc0n = 00h, tmc0n = 04h ffffh tm0n register 0000h operable bits (tmc0n3, tmc0n2) compare register (cr0n0) compare match interrupt (inttm0n0) compare register (cr0n1) compare match interrupt (inttm0n1) to0n pin output overflow flag (ovf0n) 01 m n m n m n m n 00 00 n 0 write clear 0 write clear 0 write clear 0 write clear m this is an application example where two compare registers are used in the free-running timer mode. the output level of the to0n pin is reversed each time the count value of the tm0n register matches the set values of the cr0n0 and cr0n1 register s. when the count value matches t he register value, the inttm0n0 or inttm0n1 signal is generated. remark n = 0 to 5 (2) free-running timer mode operation (cr0n0 register: compare register , cr0n1 register: capture register) figure 8-25. block diagram of free-running timer mode (cr0n0 register: compare register, cr0n1 register: capture register) 16-bit counter (tm0n) output controller edge detection capture register (cr0n1) capture signal to0n pin match signal interrupt signal (inttm0n0) interrupt signal (inttm0n1) ti0n0 pin compare register (cr0n0) operable bits tmc0n3, tmc0n2 count clock remark n = 0 to 5 chapter 8 16-bit timer/event counter 0 preliminary user?s manual u17702ej1v0ud 352 figure 8-26. timing example of free-running timer mode (cr0n0 register: compare register, cr0n1 register: capture register) ? toc0n = 13h, prm0n = 10h, crc0n = 04h, tmc0n = 04h 01 m n s p q 00 0000h 0000h mn s p q ffffh tm0n register 0000h operable bits (tmc0n3, tmc0n2) capture trigger input (ti0n0) compare register (cr0n0) compare match interrupt (inttm0n0) compare register (cr0n1) capture interrupt (inttm0n1) to0n pin output overflow flag (ovf0n) 0 write clear 0 write clear 0 write clear 0 write clear this is an application example where a compare register a nd a capture register are used at the same time in the free-running timer mode. in this example, the inttm0n0 signal is generated and th e output level of the to0n pin is reversed each time the count value of the tm0n register matches the set value of the cr0n0 register (compare register). in addition, the inttm0n1 signal is generated and the count va lue of the tm0n register is captured to the cr0n1 register each time the valid ed ge of the ti0n0 pin is detected. remark n = 0 to 5 chapter 8 16-bit timer/event counter 0 preliminary user?s manual u17702ej1v0ud 353 (3) free-running timer mode operation (cr0n0 register: capture register , cr0n1 register: capture register) figure 8-27. block diagram of free-running timer mode (cr0n0 register: capture register, cr0n1 register: capture register) 16-bit counter (tm0n) capture register (cr0n0) capture signal capture signal interrupt signal (inttm0n1) interrupt signal (inttm0n0) capture register (cr0n1) operable bits tmc0n3, tmc0n2 count clock edge detection ti0n0 pin edge detection ti0n1 pin selector remarks 1. if both the cr0n0 and cr0n1 registers are used as capture registers in the free-running timer mode, the output level of t he to0n pin is not inverted. however, it can be inverted each time the valid edge of the ti0n0 pin is detected if the tmc0n.tmc0n1 bit is set to 1. 2. n = 0 to 5 chapter 8 16-bit timer/event counter 0 preliminary user?s manual u17702ej1v0ud 354 figure 8-28. timing example of free-running timer mode (cr0n0 register: capture register, cr0 n1 register: capture register) (1/2) (a) toc0n = 13h, prm0n = 0 to 50h, crc0n = 05h, tmc0n = 04h 01 m a b c de n s p q 00 0000h abc d e 0000h mn s p q ffffh tm0n register 0000h operable bits (tmc0n3, tmc0n2) capture trigger input (ti0n0) capture register (cr0n1) capture interrupt (inttm0n1) capture trigger input (ti0n1) capture register (cr0n0) capture interrupt (inttm0n0) overflow flag (ovf0n) 0 write clear 0 write clear 0 write clear 0 write clear this is an application example where the count values that have been captured at t he valid edges of separate capture trigger signals are stor ed in separate capture registers in the free-running timer mode. the count value is captured to the cr0n1 register when the valid ed ge of the ti0n0 pin input is detected and to the cr0n0 register when the valid edge of the ti0n1 pin input is detected. remark n = 0 to 5 chapter 8 16-bit timer/event counter 0 preliminary user?s manual u17702ej1v0ud 355 figure 8-28. timing example of free-running timer mode (cr0n0 register: capture register, cr0 n1 register: capture register) (2/2) (b) toc0n = 13h, prm0n = c0h, crc0n = 05h, tmc0n = 04h ffffh tm0n register 0000h operable bits (tmc0n3, tmc0n2) capture trigger input (ti0n1) capture register (cr0n0) capture interrupt (inttm0n0) capture trigger input (ti0n0) capture register (cr0n1) capture interrupt (inttm0n1) 01 l m p s n o r q t 00 0000h 0000h lmn o pq r s t l l this is an application example where both the edges of the ti0n1 pin are detect ed and the count value is captured to the cr0n0 register in the free-running timer mode. when both the cr0n0 and cr0n1 registers are used as capt ure registers and when the valid edge of only the ti0n1 pin is to be detected, the count val ue cannot be captured to the cr0n1 register. remark n = 0 to 5 chapter 8 16-bit timer/event counter 0 preliminary user?s manual u17702ej1v0ud 356 figure 8-29. example of register setti ngs in free-running timer mode (1/2) (a) 16-bit timer mode cont rol register 0n (tmc0n) 0000010/10 tmc0n3 tmc0n2 tmc0n1 ovf0n free-running timer mode 0: inverts to0n pin output on match between cr0n0 and cr0n1. 1: inverts to0n pin output on match between cr0n0 and cr0n1 and valid edge of ti0n0 pin. (b) capture/compare cont rol register 0n (crc0n) 000000/10/10/1 crc0n2 crc0n1 crc0n0 0: cr0n0 used as compare register 1: cr0n0 used as capture register 0: cr0n1 used as compare register 1: cr0n1 used as capture register 0: ti0n1 pin is used as capture trigger of cr0n0. 1: reverse phase of ti0n0 pin is used as capture trigger of cr0n0. (c) 16-bit timer output control register 0n (toc0n) 0 0 0 0/1 0/1 lvr0n lvs0n toc0n4 ospe0n ospt0n toc0n1 toe0n 0: disables to0n output 1: enables to0n output 00: does not invert to0n output on match between tm0n and cr0n0/cr0n1. 01: inverts to0n output on match between tm0n and cr0n0. 10: inverts to0n output on match between tm0n and cr0n1. 11: inverts to0n output on match between tm0n and cr0n0/cr0n1. specifies initial value of to0n output f/f 0/1 0/1 0/1 remark n = 0 to 5 chapter 8 16-bit timer/event counter 0 preliminary user?s manual u17702ej1v0ud 357 figure 8-29. example of register setti ngs in free-running timer mode (2/2) (d) prescaler mode register 0n (prm0n), sel ector operation control register 1 (selcnt1) 0/1 prm0n 0/1 0/1 0/1 0 prm0n1 prm0n0 esn11 esn10 esn01 esn00 count clock selection (setting ti0n0 valid edge is prohibited) 00: falling edge detection 01: rising edge detection 10: setting prohibited 11: both edges detection (setting prohibited when crc0n1 = 1) 00: falling edge detection 01: rising edge detection 10: setting prohibited 11: both edges detection 0 0/1 0/1 selcnt1 isel1n 0/1 (e) 16-bit timer counter 0n (tm0n) by reading the tm0n register, the count value can be read. (f) 16-bit capture/compare register 0n0 (cr0n0) when this register is used as a co mpare register and when its value ma tches the count value of the tm0n register, an interrupt signal (inttm0n0) is generated. the count value of the tm0n register is not cleared. to use this register as a capture register, select eit her the ti0n0 or ti0n1 pin input as a capture trigger. when the valid edge of the capt ure trigger is detected, t he count value of the tm0n r egister is stored in the cr0n0 register. (g) 16-bit capture/compare register 0n1 (cr0n1) when this register is used as a co mpare register and when its value ma tches the count value of the tm0n register, an interrupt signal (inttm0n1) is generated. the count value of the tm0n register is not cleared. when this register is used as a capt ure register, the ti0n0 pin input is us ed as a capture trigger. when the valid edge of the capture trigger is detected, the count value of the tm0n register is stored in the cr0n1 register. remark n = 0 to 5 chapter 8 16-bit timer/event counter 0 preliminary user?s manual u17702ej1v0ud 358 figure 8-30. example of software pr ocessing in free-running timer mode ffffh tm0n register 0000h operable bits (tmc0n3, tmc0n2) compare register (cr0n0) compare match interrupt (inttm0n0) compare register (cr0n1) compare match interrupt (inttm0n1) timer output control bits (toe0n, toc0n4, toc0n1) to0n pin output m 01 n n n n m m m 00 <1> <2> 00 n tmc0n3, tmc0n2 bits = 0, 1 register initial setting prm0n register, selcnt1 register, crc0n register, toc0n register note , cr0n0/cr0n1 register, tmc0n.tmc0n1 bit, port setting initial setting of these registers is performed before setting the tmc0n3 and tmc0n2 bits to 01. starts count operation start <1> count operation start flow tmc0n3, tmc0n2 bits = 0, 0 the counter is initialized and counting is stopped by clearing the tmc0n3 and tmc0n2 bits to 00. stop <2> count operation stop flow note care must be exercised when setting the toc0n register. for details, see 8.3 (3) 16-bit timer output control register 0n (toc0n) . remark n = 0 to 5 chapter 8 16-bit timer/event counter 0 preliminary user?s manual u17702ej1v0ud 359 8.4.6 ppg output operation a rectangular wave having a pulse width set in advance by the cr0n1 register is out put from the to0n pin as a ppg (programmable pulse generator) signal during a cycle set by the cr0n0 register when the tmc0n.tmc0n3 and tmc0n.tmc0n2 bits are set to 11 (clear & start upon a ma tch between the tm0n register and the cr0n0 register). the pulse cycle and duty factor of the pulse generated as the ppg output are as follows. ? pulse cycle = (set value of the cr0n0 register + 1) count clock cycle ? duty = (set value of the cr0n1 register + 1) / (set value of the cr0n0 register + 1) caution to change the duty factor (value of the cr0 n1 register) during operat ion, see 8.5.1 rewriting cr0n1 register durin g tm0n operation. remarks 1. for the alternate-function pin settings, refer to table 4-19 settings when port pins are used for alternate functions . 2. for enabling the inttm0n0 and inttm0n1 interrupts, refer to chapter 21 interrupt/ exception processing function . figure 8-31. block diagram of ppg output operation 16-bit counter (tm0n) clear output controller compare register (cr0n1) match signal to0n pin match signal interrupt signal (inttm0n0) interrupt signal (inttm0n1) compare register (cr0n0) operable bits tmc0n3, tmc0n2 count clock remark n = 0 to 5 chapter 8 16-bit timer/event counter 0 preliminary user?s manual u17702ej1v0ud 360 figure 8-32. example of register settings for ppg output operation (a) 16-bit timer mode cont rol register 0n (tmc0n) 00001100 tmc0n3 tmc0n2 tmc0n1 ovf0n clears and starts on match between tm0n and cr0n0. (b) capture/compare cont rol register 0n (crc0n) 00000000 crc0n2 crc0n1 crc0n0 cr0n0 used as compare register cr0n1 used as compare register (c) 16-bit timer output control register 0n (toc0n) 0 0 0 1 0/1 lvr0n lvs0n toc0n4 ospe0n ospt0n toc0n1 toe0n enables to0n output 11: inverts to0n output on match between tm0n and cr0n0/cr0n1. 00: disables one-shot pulse output specifies initial value of to0n output f/f 0/1 1 1 (d) prescaler mode register 0n (prm0n), sel ector operation control register 1 (selcnt1) 0 prm0n 0 0 0 0 prm0n1 prm0n0 isel1n esn11 esn10 esn01 esn00 selects count clock 0 0/1 0/1 0/1 selcnt1 (e) 16-bit timer counter 0n (tm0n) by reading the tm0n register, the count value can be read. (f) 16-bit capture/compare register 0n0 (cr0n0) an interrupt signal (inttm0n0) is generated when the valu e of this register matches the count value of the tm0n register. (g) 16-bit capture/compare register 0n1 (cr0n1) an interrupt signal (inttm0n1) is generated when the valu e of this register matches the count value of the tm0n register. caution set values to the cr0n0 and cr0n1 registers such that the condition 0000h cr0n1 < cr0n0 ffffh is satisfied. remark n = 0 to 5 chapter 8 16-bit timer/event counter 0 preliminary user?s manual u17702ej1v0ud 361 figure 8-33. example of software pr ocessing for ppg output operation tm0n register 0000h operable bits (tmc0n3, tmc0n2) compare register (cr0n0) compare match interrupt (inttm0n0) compare register (cr0n1) compare match interrupt (inttm0n1) timer output control bits (toe0n, toc0n4, toc0n1) to0n pin output m 11 m m m n n n 00 <1> n + 1 <2> 00 n tmc0n3, tmc0n2 bits = 11 register initial setting prm0n register, selcnt1 register, crc0n register, toc0n register note , cr0n0, cr0n1 registers, port setting initial setting of these registers is performed before setting the tmc0n3 and tmc0n2 bits. starts count operation start <1> count operation start flow tmc0n3, tmc0n2 bits = 00 the counter is initialized and counting is stopped by clearing the tmc0n3 and tmc0n2 bits to 00. stop <2> count operation stop flow n + 1 n + 1 m + 1 m + 1 m + 1 note care must be exercised when setting the toc0n register. for details, see 8.3 (3) 16-bit timer output control register 0n (toc0n) . remarks 1. ppg pulse cycle = (m + 1) count clock cycle ppg duty = (n + 1)/(m + 1) 2. n = 0 to 5 chapter 8 16-bit timer/event counter 0 preliminary user?s manual u17702ej1v0ud 362 8.4.7 one-shot pulse output operation a one-shot pulse can be output by setting the tmc0n.tm c0n3 and tmc0n.tmc0n2 bits to 01 (free-running timer mode) or to 10 (clear & start mode entered by the ti0n0 pin valid edge) and setting the toc0n.ospe0n bit to 1. when the toc0n.ospt0n is set to 1 or when the valid edge is input to the ti0n0 pin during timer operation, clearing & starting of the tm0n register is triggered, and a pulse of the di fference between the values of the cr0n0 and cr0n1 registers is output onl y once from the to0n pin. caution do not input the trigger again (setting ospt0n to 1 or detecting the valid edge of the ti0n0 pin) while the one-shot pulse is output. to output th e one-shot pulse again, gene rate the trigger after the current one-shot pulse output has completed. remarks 1. for the alternate-function pin settings, refer to table 4-19 settings when port pins are used for alternate functions . 2. for enabling the inttm0n0 and inttm0n1 interrupts, refer to chapter 21 interrupt/ exception processing function . figure 8-34. block diagram of on e-shot pulse output operation 16-bit counter (tm0n) output controller compare register (cr0n1) match signal to0n pin match signal interrupt signal (inttm0n0) interrupt signal (inttm0n1) compare register (cr0n0) operable bits tmc0n3, tmc0n2 count clock ti0n0 edge detection ospt0n bit ospe0n bit clear remark n = 0 to 5 chapter 8 16-bit timer/event counter 0 preliminary user?s manual u17702ej1v0ud 363 figure 8-35. example of register settings for one-shot pulse output operation (1/2) (a) 16-bit timer mode cont rol register 0n (tmc0n) 00000/10/100 tmc0n3 tmc0n2 tmc0n1 ovf0n 01: free running timer mode 10: clear and start mode by valid edge of ti0n0 pin. (b) capture/compare cont rol register 0n (crc0n) 00000000 crc0n2 crc0n1 crc0n0 cr0n0 used as compare register cr0n1 used as compare register (c) 16-bit timer output control register 0n (toc0n) 0 0/1 1 1 0/1 lvr0n lvs0n toc0n4 ospe0n ospt0n toc0n1 toe0n enables to0n pin output inverts to0n output on match between tm0n and cr0n0/cr0n1. specifies initial value of to0n pin output enables one-shot pulse output software trigger is generated by writing 1 to this bit (operation is not affected even if 0 is written to it). 0/1 1 1 (d) prescaler mode register 0n (prm0n), sel ector operation control register 1 (selcnt1) 0 prm0n 0 0 0 0 prm0n1 prm0n0 isel1n esn11 esn10 esn01 esn00 selects count clock 0 0/1 0/1 0/1 selcnt1 remark n = 0 to 5 chapter 8 16-bit timer/event counter 0 preliminary user?s manual u17702ej1v0ud 364 figure 8-35. example of register settings for one-shot pulse output operation (2/2) (e) 16-bit timer counter 0n (tm0n) by reading the tm0n register, the count value can be read. (f) 16-bit capture/compare register 0n0 (cr0n0) this register is used as a compare register when a one-shot pulse is output. when the value of the tm0n register matches that of the cr0 n0 register, an interrupt signal (i nttm0n0) is generated and the output level of the to0n pin is inverted. (g) 16-bit capture/compare register 0n1 (cr0n1) this register is used as a compare register when a one-shot pulse is output. when the value of the tm0n register matches that of the cr0 n1 register, an interrupt signal (i nttm0n1) is generated and the output level of the to0n pin is inverted. remark n = 0 to 5 chapter 8 16-bit timer/event counter 0 preliminary user?s manual u17702ej1v0ud 365 figure 8-36. example of software processing for one-shot pulse output operation (1/2) ffffh tm0n register 0000h operable bits (tmc0n3, tmc0n2) one-shot pulse enable bit (ospen) one-shot pulse trigger bit (osptn) one-shot pulse trigger input (ti0n0 pin) overflow plug (ovf0n) compare register (cr0n0) compare match interrupt (inttm0n0) compare register (cr0n1) compare match interrupt (inttm0n1) to0n pin output to0n output control bits (toe0n, toc0n4, toc0n1) n m n ? m n ? m 01 or 10 00 00 n n n m m m m + 1 m + 1 <1> <2> <2> <3> to0n output level is not inverted because no one- shot trigger is input. ? time from when the one-shot pulse trigger is input until the one-shot pulse is output = (m + 1) count clock cycle ? one-shot pulse output active level width = (n ? m) count clock cycle remark n = 0 to 5 chapter 8 16-bit timer/event counter 0 preliminary user?s manual u17702ej1v0ud 366 figure 8-36. example of software processing for one-shot pulse output operation (2/2) tmc0n3, tmc0n2 bits = 01 or 10 register initial setting prm0n register, selcnt1 register, crc0n register, toc0n register note , cr0n0, cr0n1 registers, port setting initial setting of these registers is performed before setting the tmc0n3 and tmc0n2 bits. starts count operation start <1> count operation start flow <2> one-shot trigger input flow tmc0n3, tmc0n2 bits = 00 the counter is initialized and counting is stopped by clearing the tmc0n3 and tmc0n2 bits to 00. stop <3> count operation stop flow toc0n.ospt0n bit = 1 or edge input to ti0n0 pin write the same value to the bits other than the ospt0n bit. note care must be exercised when setting the toc0n register. for details, see 8.3 (3) 16-bit timer output control register 0n (toc0n) . remark n = 0 to 5 chapter 8 16-bit timer/event counter 0 preliminary user?s manual u17702ej1v0ud 367 8.4.8 pulse width measurement operation the tm0n register can be used to m easure the pulse width of the signal input to the ti0n0 and ti0n1 pins. measurement can be accomplished by operating the 16-bit ti mer/event counter 0n in the free-running timer mode or by restarting the timer in synchronizati on with the signal input to the ti0n0 pin. when an interrupt is generated, read the value of the valid capture register and measure the pulse width. check the tmc0n.ovf0n flag. if it is set (to 1), clear it to 0 by software. figure 8-37. block di agram of pulse width measureme nt (free-running timer mode) 16-bit counter (tm0n) capture register (cr0n0) capture signal capture signal interrupt signal (inttm0n1) interrupt signal (inttm0n0) capture register (cr0n1) operable bits tmc0n3, tmc0n2 count clock edge detection ti0n0 pin edge detection ti0n1 pin selector remark n = 0 to 5 figure 8-38. block diagram of pulse width measurement (clear & start mode entered by ti0n0 pin valid edge input) 16-bit counter (tm0n) capture register (cr0n0) capture signal capture signal interrupt signal (inttm0n1) interrupt signal (inttm0n0) capture register (cr0n1) operable bits tmc0n3, tmc0n2 count clock edge detection ti0n0 pin edge detection ti0n1 pin clear selector remark n = 0 to 5 chapter 8 16-bit timer/event counter 0 preliminary user?s manual u17702ej1v0ud 368 a pulse width can be measured in the following three ways. ? measuring the pulse width by using two input signals of the ti0n0 and ti0n1 pins (free-running timer mode) ? measuring the pulse width by using one input signal of the ti0n0 pin (free-running timer mode) ? measuring the pulse width by using one input signal of the ti0n0 pin (clear & start mode entered by the ti0n0 pin valid edge input) (1) measuring the pulse width by using two input sign als of the ti0n0 and ti0n1 pins (free-running timer mode) set the free-running timer mode (the tmc0n.tmc0n3 an d tmc0n.tmc0n2 bits = 01). when the valid edge of the ti0n0 pin is detected, the count valu e of the tm0n register is captured to the cr0n1 register. when the valid edge of the ti0n1 pin is detected, the count value of the tm 0n register is captured to the cr0n0 register. specify detection of both the edges of the ti0n0 and ti0n1 pins. by this measurement method, the prev ious count value is subt racted from the count valu e captured by the edge of each input signal. therefore, sa ve the previously captured value to a separate register in advance. if an overflow occurs, the value becomes negative if the pr eviously captured value is si mply subtracted from the current captured value and, therefore, a borrow occurs (the psw.cy bit is set to 1). if this happens, ignore cy and take the calculated value as the pulse width. in addition, clear the tmc0n.ovf0n bit to 0. figure 8-39. timing example of pulse width measurement (1) ? tmc0n = 04h, prm0n = f0h, crc0n = 05h ffffh tm0n register 0000h operable bits (tmc0n3, tmc0n2) capture trigger input (ti0n0) capture register (cr0n1) capture interrupt (inttm0n1) capture trigger input (ti0n1) capture register (cr0n0) capture interrupt (inttm0n0) overflow flag (ovf0n) 01 m a b c de n s p q 00 0 write clear 0 write clear 0 write clear 0 write clear 0000h abc d e 0000h mn s p q remark n = 0 to 5 chapter 8 16-bit timer/event counter 0 preliminary user?s manual u17702ej1v0ud 369 (2) measuring the pulse width by using one input si gnal of the ti0n0 pin (free-running timer mode) set the free-running timer mode (the tmc0n.tmc0n3 and tmc0n.tmc0n2 bits = 01). the count value of the tm0n register is captured to the cr0n0 r egister in the phase reverse to the valid edge detected on the ti0n0 pin. when the valid edge of the ti0n0 pin is detected, the count value of the tm0n register is captured to the cr0n1 register. by this measurement method, values are stored in se parate capture registers when a width from one edge to another is measured. theref ore, the capture values do not have to be saved. by subtracting the value of one capture register from that of a nother, a high-level width, low-level width, and cycle are calculated. if an overflow occurs, the value becomes negative if one c aptured value is simply subtracted from another and, therefore, a borrow occurs (the psw.cy bit is set to 1). if this happens, ignore cy and take the calculated value as the pulse width. in addition, clear the tmc0n.ovf0n bit to 0. figure 8-40. timing example of pulse width measurement (2) ? tmc0n = 04h, prm0n = 10h, crc0n = 07h ffffh tm0n register 0000h operable bits (tmc0n3, tmc0n2) capture trigger input (ti0n0) capture register (cr0n0) capture register (cr0n1) capture interrupt (inttm0n1) overflow flag (ovf0n) capture trigger input (ti0n1) capture interrupt (inttm0n0) 01 m a b c de n s p q 00 0 write clear 0 write clear 0 write clear 0 write clear 0000h l l abc d e 0000h mn s p q remark n = 0 to 5 chapter 8 16-bit timer/event counter 0 preliminary user?s manual u17702ej1v0ud 370 (3) measuring the pulse width by using one input signal of the ti0n0 pin (clear & st art mode entered by the ti0n0 pin valid edge input) set the clear & start mode entered by the ti0n0 pin va lid edge (the tmc0n.tmc0n3 and tmc0n.tmc0n2 bits = 10). the count value of the tm0n regist er is captured to the cr0n0 register in the phase reverse to the valid edge of the ti0n0 pin, and the count value of the tm0n regi ster is captured to the cr0n1 register and the tm0n register is cleared (0000h) when the valid edge of the ti0n0 pin is detected. ther efore, a cycle is stored in the cr0n1 register if the tm0n register does not overflow. if an overflow occurs, take the value that results from addi ng 10000h to the value stored in the cr0n1 register as a cycle. clear the tmc0n.ovf0n bit to 0. figure 8-41. timing example of pulse width measurement (3) ? tmc0n = 08h, prm0n = 10h, crc0n = 07h ffffh tm0n register 0000h operable bits (tmc0n3, tmc0n2) capture & count clear input (ti0n0) capture register (cr0n0) capture register (cr0n1) capture interrupt (inttm0n1) overflow flag (ovf0n) capture trigger input (ti0n1) capture interrupt (inttm0n0) 10 <1> <2> <3> <3> <3> <3> <2> <2> <2> <1> <1> <1> m a b cd n s p q 00 00 0 write clear 0000h l l abc d 0000h mn s p q <1> pulse cycle = (10000h number of times ovf0n bit is set to 1 + captured value of the cr0n1 register) count clock cycle <2> high-level pulse width = (10000h number of times ovf0n bit is set to 1 + captured value of the cr0n0 register) count clock cycle <3> low-level pulse width = (pulse cycle ? high-level pulse width) remark n = 0 to 5 chapter 8 16-bit timer/event counter 0 preliminary user?s manual u17702ej1v0ud 371 figure 8-42. example of register setti ngs for pulse width measurement (1/2) (a) 16-bit timer mode cont rol register 0n (tmc0n) 00000/10/100 tmc0n3 tmc0n2 tmc0n1 ovf0n 01: free running timer mode 10: clear and start mode entered by valid edge of ti0n0 pin. (b) capture/compare cont rol register 0n (crc0n) 0000010/11 crc0n2 crc0n1 crc0n0 1: cr0n0 used as capture register 1: cr0n1 used as capture register 0: ti0n1 pin is used as capture trigger of cr0n0. 1: reverse phase of ti0n0 pin is used as capture trigger of cr0n0. (c) 16-bit timer output control register 0n (toc0n) 00000 lvr0n lvs0n toc0n4 ospe0n ospt0n toc0n1 toe0n 000 (d) prescaler mode register 0n (prm0n), sel ector operation control register 1 (selcnt1) selects count clock (setting valid edge of ti0n0 is prohibited) 00: falling edge detection 01: rising edge detection 10: setting prohibited 11: both edges detection (setting when crc0n1 = 1 is prohibited) 00: falling edge detection 01: rising edge detection 10: setting prohibited 11: both edges detection 0/1 prm0n 0/1 0/1 0/1 0 prm0n1 prm0n0 esn11 esn10 esn01 esn00 0 0/1 0/1 selcnt1 isel1n 0/1 remark n = 0 to 5 chapter 8 16-bit timer/event counter 0 preliminary user?s manual u17702ej1v0ud 372 figure 8-42. example of register setti ngs for pulse width measurement (2/2) (e) 16-bit timer counter 0n (tm0n) by reading the tm0n register, the count value can be read. (f) 16-bit capture/compare register 0n0 (cr0n0) this register is used as a capture register. either t he ti0n0 or ti0n1 pin is select ed as a capture trigger. when a specified edge of the capture trigger is detected, the count value of the tm 0n register is stored in the cr0n0 register. (g) 16-bit capture/compare register 0n1 (cr0n1) this register is used as a capture register. the signal input to the ti 0n0 pin is used as a capture trigger. when the capture trigger is detected, the count value of the tm0n register is stored in the cr0n1 register. remark n = 0 to 5 chapter 8 16-bit timer/event counter 0 preliminary user?s manual u17702ej1v0ud 373 figure 8-43. example of software proce ssing for pulse width measurement (1/2) (a) example of free-running timer mode ffffh tm0n register 0000h operable bits (tmc0n3, tmc0n2) capture trigger input (ti0n0) capture register (cr0n1) capture interrupt (inttm0n1) capture trigger input (ti0n1) capture register (cr0n0) capture interrupt (inttm0n0) 01 d 00 d 00 d 01 d 01 d 02 d 02 d 03 d 03 d 04 d 04 d 10 d 10 d 11 d 11 d 12 d 12 d 13 d 13 00 00 0000h 0000h <1> <2> <2> <2> <2> <2> <2> <2> <2> <2> <3> (b) example of clear & start mode entered by ti0n0 pin valid edge ffffh tm0n register 0000h operable bits (tmc0n3, tmc0n2) capture & count clear input (ti0n0) capture register (cr0n0) capture interrupt (inttm0n0) capture register (cr0n1) capture interrupt (inttm0n1) 10 d 0 l d 0 d 1 d 1 d 2 d 2 d 3 d 3 d 4 d 4 d 5 d 5 d 6 d 6 d 7 d 7 d 8 d 8 00 00 0000h 0000h <1> <2> <2> <2> <2> <2> <2> <2> <2> <3> <2> remark n = 0 to 5 chapter 8 16-bit timer/event counter 0 preliminary user?s manual u17702ej1v0ud 374 figure 8-43. example of software proce ssing for pulse width measurement (2/2) <2> capture trigger input flow edge detection of ti0n0, ti0n1 pins calculated pulse width from capture value stores count value to cr0n0, cr0n1 registers. generates capture interrupt note . tmc0n3, tmc0n2 bits = 01 or 10 register initial setting prm0n register, selcnt1 register, crc0n register, port setting initial setting of these registers is performed before setting the tmc0n3 and tmc0n2 bits. starts count operation start <1> count operation start flow tmc0n3, tmc0n2 bits = 00 the counter is initialized and counting is stopped by clearing the tmc0n3 and tmc0n2 bits to 00. stop <3> count operation stop flow note the capture interrupt signal (i nttm0n0) is not generated when the re verse-phase edge of the ti0n0 pin input is selected to the valid edge of the cr0n0 register. remark n = 0 to 5 chapter 8 16-bit timer/event counter 0 preliminary user?s manual u17702ej1v0ud 375 8.5 special use of tm0n 8.5.1 rewriting cr0n1 regi ster during tm0n operation in principle, rewriting the cr0n0 and cr0n1 registers of the v850es/kj 2 when they are used as compare registers is prohibited while the tm 0n register is operating (tmc0n.tmc0n3 and tmc0n.tm c0n2 bits = other than 00). however, the value of the cr0n1 register can be changed, even while the tm0n register is operating, using the following procedure if the cr0n1 register is used for ppg output and the duty fa ctor is changed (change the value of the cr0n1 register immediately after its value matches th e value of the tm0n register. if the value of the cr0n1 register is changed immediately before its value matc hes the tm0n register, an une xpected operation may be performed). procedure for changing value of the cr0n1 register <1> disable interrupt inttm0n1 (tm0icn0.tm0mkn1 bit = 1). <2> disable reversal of the timer output when the value of the tm0n register matches that of the cr0n1 register (toc0n.toc0n4 bit = 0). <3> change the value of the cr0n1 register. <4> wait for one cycle of the count clock of the tm0n register. <5> enable reversal of the timer output when the value of the tm0n register matches that of the cr0n1 register (toc0n.toc0n4 bit = 1). <6> clear the interrupt flag of inttm 0n1 (tm0icn0.tm0ifn1 bit = 0) to 0. <7> enable interrupt inttm0n1 (tm0icn0.tm0mkn1 bit = 0). remark for the tm0icn0 register, see chapter 21 interrupt/exception processing function . 8.5.2 setting lvs0n and lvr0n bits (1) usage of the lvs0n and lvr0n bits the toc0n.lvs0n and toc0n.lvr0n bits are used to set the default value of the to0n pin output and to invert the timer output without enabling the ti mer operation (tmc0n.tmc0n3 and tmc 0n.tmc0n2 bits = 00). clear the lvs0n and lvr0n bits to 00 (default value: low- level output) when software control is unnecessary. lvs0n bit lvr0n bit timer output status 0 0 not changed (low-level output) 0 1 cleared (low-level output) 1 0 set (high-level output) 1 1 setting prohibited remark n = 0 to 5 chapter 8 16-bit timer/event counter 0 preliminary user?s manual u17702ej1v0ud 376 (2) setting the lvs0n and lvr0n bits set the lvs0n and lvr0n bits using the following procedure. figure 8-44. example of flow for setting lvs0n and lvr0n bits setting toc0n.ospe0n, toc0n4, toc0n1 bits setting toc0n.toe0n bit setting toc0n.lvs0n, lvr0n bits setting tmc0n.tmc0n3, tmc0n2 bits <3> enabling timer operation <2> setting of timer output f/f <1> setting of timer output operation caution be sure to set the lvs0n and lvr0n bits following steps <1>, <2>, and <3> above. step <2> can be performed after <1> and before <3>. remark n = 0 to 5 figure 8-45. timing example of lvr0n and lvs0n bits toc0n.lvs0n bit toc0n.lvr0n bit operable bits (tmc0n3, tmc0n2) to0n pin output inttm0n0 signal <1> 00 <2> <1> <3> <4> <4> <4> 01, 10, or 11 <1> the to0n pin output goes high wh en the lvs0n and lvr0n bits = 10. <2> the to0n pin output goes low when the lvs0n and lvr0n bits = 01 (the pin output remains unchanged from the high level even if the lvs0n and lvr0n bits are cleared to 00). <3> the timer starts operating when the tmc0n3 and tm c0n2 bits are set to 01, 10, or 11. because the lvs0n and lvr0n bits were set to 10 before the operat ion was started, the to0n pin output starts from the high level. after the timer st arts operating, setting the lvs0n and lvr0n bits is prohibited until the tmc0n3 and tmc0n2 bits = 00 (disabling the timer operation). <4> the output level of the to0n pi n is inverted each time an interrupt signal (inttm0n0) is generated. remark n = 0 to 5 chapter 8 16-bit timer/event counter 0 preliminary user?s manual u17702ej1v0ud 377 8.6 cautions (1) alternate functions of ti0n0/to0n pins channel pin alternate function remarks ti000 p33/to00/tip00/top00 shares the pin with to00. ti001 p34/to00/tip01/top01 shares the pin with to00. p33/ti000/tip00/top00 tm00 to00 p34/ti001/tip01/top01 assigned to two pins, p33 and p34. ti010 p35/to01 shares the pin with to01. ti011 p50/kr0/rtp00 ? p32/asck0/adtrg tm01 to01 p35/ti010 assigned to two pins, p32 and p35. ti020 p92/a2/to02 shares the pin with to02. ti021 p93/a3 ? p30/txd0 tm02 to02 p92/ti020/a2 assigned to two pins, p30 and p92. ti030 p94/a4/to03 shares the pin with to03. ti031 p95/a5 ? p31/rxd0/intp7 tm03 to03 p94/ti030/a4 assigned to two pins, p31 and p94. ti040 p69 ? ti041 p610 ? tm04 to04 p611 ? ti050 p612 ? ti051 p613/to05 shares the pin with to05. tm05 to05 p613/ti051 ? (a) for tm00 ? to perform the one-shot pulse out put with detecting the valid edge of t he ti000 pin as a trigger, use the to00 pin output that functions alternately as p34. when using the to00 pin output that functions alternately as p33, the ti000 pin that functions alternately as p33 cannot be used. when using only a software trigger (setting (1) toc00 .ospt00 bit) as the start trigger for the one-shot pulse output, either of the p33 and p34 pi ns can be used as the to00 pin output. ? to perform the to00 pin output inversion operation by detecting the valid edge of the ti000 pin input, use the to00 pin output that f unctions alternately as p34. when using the to00 pin output that functions alternately as p33, the ti000 pin that functions alternately as p33 cannot be used. therefore, the to00 pin output inversion operation by detecting the valid edge of the ti000 pin input cannot be performed. when usin g the to00 pin that functions alternately as p33, clear the tmc00.tmc001 bit to 0. chapter 8 16-bit timer/event counter 0 preliminary user?s manual u17702ej1v0ud 378 (b) for tm01 ? to perform the one-shot pulse out put with detecting the valid edge of t he ti010 pin as a trigger, use the output of the to01 pin that fu nctions alternately as p32. when using the output of the to01 pin that functions alternately as p35, t he ti010 pin that functions alternately as p35 cannot be used. when using only a software trigger (setting (1) toc 01.ospt01 bit ) as the start trigger for the one-shot pulse output, either of the p32 and p35 pi ns can be used as the to01 pin output. ? to perform the to01 pin output inversion operation by detecting the valid edge of the ti010 pin input, use the output of the to01 pin that functions alternately as p32. when using the output of the to01 pin that functions alternately as p35, t he ti010 pin that functions alternately as p35 cannot be used. therefore, the to01 pin output inversion operation by detecting the valid edge of the ti010 pin input cannot be performed. when usin g the to01 pin that functions alternately as p35, clear the tmc01.tmc011 bit to 0. (c) for tm02 ? to perform the one-shot pulse output, use the output of the to02 pin that functions alternately as p30. the output of the to02 pin that f unctions alternately as p92 cannot be used for one-shot pulse output not only when using the detection of the ti020 pin va lid edge as a trigger but also when using only the software trigger (setting (1) toc02.ospt02 bit) as a start trigger. ? to perform the to02 pin output inversion operation by detecting the valid edge of the ti020 pin input, use the output of the to02 pin that functions alternately as p30. when using the output of the to02 pin that functions alternately as p92, t he ti020 pin that functions alternately as p92 cannot be used. therefore, the to02 pin output inversion operation by detecting the valid edge of the ti020 pin input cannot be performed. when usin g the to02 pin that functions alternately as p92, clear the tmc02.tmc021 bit to 0. (d) for tm03 ? to perform the one-shot pulse output, use the output of the to03 pin that functions alternately as p31. the output of the to03 pin that f unctions alternately as p94 cannot be used for one-shot pulse output not only when using the detection of the ti030 pin va lid edge as a trigger but also when using only the software trigger (setting (1) toc03.ospt03 bit) as a start trigger. ? to perform the to03 pin output inversion operation by detecting the valid edge of the ti030 pin input, use the output of the to03 pin that functions alternately as p31. when using the output of the to03 pin that functions alternately as p94, t he ti030 pin that functions alternately as p94 cannot be used. therefore, the to03 pin output inversion operation by detecting the valid edge of the ti030 pin input cannot be performed. when usin g the to03 pin that functions alternately as p94, clear the tmc03.tmc031 bit to 0. (e) for tm04 and tm05 ? ti040 and to04 do not share a pin (used independently). ? ti050 and to05 do not share a pin (used independently). chapter 8 16-bit timer/event counter 0 preliminary user?s manual u17702ej1v0ud 379 (2) error on starting timer an error of up to 1 clock occurs before the match signal is generated after the timer has been started. this is because the count of the tm0n register is st arted asynchronously to the count pulse. figure 8-46. count start timing of tm0n register 0000h timer start 0001h 0002h 0003h 0004h count pulse tm0n count value remark n = 0 to 5 (3) setting cr0n0 and cr0n1 registers (in the mode in which clear & start occurs upon match between tm0n register and cr0n0 register) set the cr0n0 and cr0n1 registers to a value other than 0000h (when using these registers as external event counters, one-pulse count operation is not possible). remark n = 0 to 5 chapter 8 16-bit timer/event counter 0 preliminary user?s manual u17702ej1v0ud 380 (4) data hold timing of capture register (a) if the valid edge of the ti0n1/ti 0n0 pin is input while the cr0n0/cr0n1 register is read, the cr0n0/cr0n1 register performs capture oper ation, but the read value at this time is not guaranteed. howe ver, the interrupt request signal (inttm0n0/inttm0n1) is generated as a result of detection of the valid edge. figure 8-47. data hold timing of capture register n n + 1 n + 2 x n + 1 m m + 1 m + 2 count pulse tm0n count value edge input inttm0n1 value captured to cr0n1 capture read signal capture operation is performed but read value is not guaranteed. capture operation remark n = 0 to 5 (b) the values of the cr0n0 and cr0n1 registers are no t guaranteed after 16-bit timer/event counter 0n has stopped. (5) setting valid edge set the valid edge of the ti0n0 pin while the timer operation is stopped (tmc 0n.tmc0n3 and tmc0n.tmc0n2 bits = 00). set the valid edge by us ing the prm0n.esn00 and prm0n.esn01 bits. (6) re-triggering one-shot pulse make sure that the trigger is not generated while an active level is being output in t he one-shot pulse output mode. be sure to input the next trigger afte r the current active level is output. remark n = 0 to 5 chapter 8 16-bit timer/event counter 0 preliminary user?s manual u17702ej1v0ud 381 (7) operation of ovf0n flag (a) setting of ovf0n flag the tmc0n.ovf0n flag is set to 1 in the following case in addition to when the tm0n register overflows. select the mode in which clear & start occurs upon match between the tm0n r egister and the cr0n0 register. set the cr0n0 register to ffffh when the tm0n register is cleared from ffffh to 0000h upon match with the cr0n0 register figure 8-48. operation timing of ovf0n flag fffeh ffffh ffffh 0000h 0001h count pulse tm0n inttm0n0 ovf0n cr0n0 remark n = 0 to 5 (b) clearing of ovf0n flag after the tm0n register overflows, cl earing ovf0n flag is invalid and set (1) again even if the ovf0n flag is cleared (0) before the next count clock is count ed (before tm0n register becomes 0001h). remark n = 0 to 5 chapter 8 16-bit timer/event counter 0 preliminary user?s manual u17702ej1v0ud 382 (8) one-shot pulse output one-shot pulse output operates normally in either the free-running timer mode or the mode in which clear & start occurs on the valid edge of the ti0n0 pin. in the mode in which clear & start occurs upon match between the tm0n register and the cr0n0 register, one-shot pul se output is not possible. remark n = 0 to 5 (9) capture operation (a) if valid edge of ti0n0 pin is specified for count clock if the valid edge of the ti0n0 pin is spec ified for the count clock, the captur e register that s pecified the ti0n0 pin as the trigger does not operate normally. (b) to ensure that signals input from ti0n 1 and ti0n0 pins are correctly captured to accurately capture the count value, the pulse input to the ti0n0 and ti0n1 pins as a capture trigger must be wider than two count clocks selected by the prm0n and selcnt1 registers. (c) interrupt signal generation although a capture operation is performed at the falling ed ge of the count clock, an interrupt request signal (inttm0n0, inttm0n1) is generated at the ri sing edge of the next count clock. (d) note when crc0n.crc0n1 bit is set to 1 when the count value of the tm0n regist er is captured to the cr0n0 regi ster in the phase reverse to the signal input to the ti0n0 pin, the interrupt signal (i nttm0n0) is not generated after the count value is captured. if the valid edge is detect ed on the ti0n1 pin during this operat ion, the capture operation is not performed but the inttm0n0 signal is generated as an ex ternal interrupt signal. mask the inttm0n0 signal when the external interrupt is not used. remark n = 0 to 5 chapter 8 16-bit timer/event counter 0 preliminary user?s manual u17702ej1v0ud 383 (10) edge detection (a) specifying valid edge after reset if the operation of the 16-bit timer/ev ent counter 0n is enabled after reset and while the ti0n0 or ti0n1 pin is at high level and when the rising edge or both the edges are specified as the vali d edge of the ti0n0 or ti0n1 pin, then the high level of the ti0n0 or ti0n1 pin is detected as the rising edge. note this when the ti0n0 or ti0n1 pin is pulled up. however, t he rising edge is not detected when the operation is once stopped and then enabled again. (b) sampling clock for noise elimination the sampling clock for noise elimination differs depending on whether the valid edge of ti0n0 is used for the count clock or as a capture trigger. in the former case, sampling is performed using f xx /4, and in the latter case, sampling is performed using the count clo ck selected by the prm0n and selcnt1 registers. when the signal input to the ti0n0 pin is sampled and the valid level is detected two times in a row, the valid edge is detected. therefore, noise having a short pulse width can be eliminated. remarks 1. f xx : main clock frequency 2. n = 0 to 5 preliminary user?s manual u17702ej1v0ud 384 chapter 9 8-bit timer/event counter 5 in the v850es/kj2, two channels of 8-bi t timer/event counter 5 are provided. 9.1 functions 8-bit timer/event counter 5n has the following two modes (n = 0, 1). ? mode using 8-bit timer/event counter alone (individual mode) ? mode using cascade connection (16-bit resolution: cascade connection mode) these two modes are described below. (1) mode using 8-bit timer/event counter alone (i ndividual mode) 8-bit timer/event counter 5n operates as an 8-bit timer/event counter. the following functions can be used. ? interval timer ? external event counter ? square-wave output ? pwm output (2) mode using cascade connection (16-bi t resolution: cascade connection mode) 8-bit timer/event counter 5n operates as a 16-bit time r/event counter by connecti ng the tm5n register in cascade. the following functions can be used. ? interval timer with 16-bit resolution ? external event counter with 16-bit resolution ? square-wave output with 16-bit resolution the block diagram of 8-bit timer/event counter 5n is shown next. chapter 9 8-bit timer/event counter 5 preliminary user?s manual u17702ej1v0ud 385 figure 9-1. block diagram of 8-bit timer/event counter 5n ovf ti5n 3 tcl5n2 tcl5n1 tcl5n0 tce5n tmc5n6 tmc5n4 lvs5n lvr5n tmc5n1 toe5n to5n inttm5n s r q inv s r q match clear count clock note selector internal bus internal bus 8-bit timer mode control register 5n (tmc5n) 8-bit timer compare register 5n (cr5n) 8-bit timer counter 5n (tm5n) selector invert level mask circuit timer clock selection register 5n (tcl5n) selector selector note the count clock is set by the tcl5n register. remark n = 0, 1 9.2 configuration 8-bit timer/event counter 5n consists of the following hardware. table 9-1. configuration of 8-bit timer/event counter 5n item configuration timer registers 8-bit timer counter 5n (tm5n) 16-bit timer counter 5 (tm5): on ly when using cascade connection registers 8-bit timer compare register 5n (cr5n) 16-bit timer compare register 5 (cr5 ): only when using cascade connection timer output 1 (to5n pin) control registers note timer clock selection register 5n (tcl5n) 8-bit timer mode control register 5n (tmc5n) 16-bit timer mode control register 5 (t mc5): only when using cascade connection note when using the functions of the ti5n and to5n pins, refer to table 4-19 settings when port pins are used for alternate functions . remark n = 0, 1 chapter 9 8-bit timer/event counter 5 preliminary user?s manual u17702ej1v0ud 386 (1) 8-bit timer counter 5n (tm5n) the tm5n register is an 8-bit read-only re gister that counts the count pulses. the counter is incremented in synchronization with the rising edge of the count clock. through cascade connection, the tm5n registers can be used as a 16-bit timer. when using the tm50 register and the tm51 register in ca scade as a 16-bit timer, these registers can be read only in 16-bit units. therefore, r ead these registers twice and compare t he values, taking into consideration that the reading occurs during a count change. tm5n (n = 0, 1) 642 after reset: 00h r address: tm50 fffff5c0h, tm51 fffff5c1h 0 753 1 the count value is reset to 00h in the following cases. <1> reset <2> when the tmc5n.tce5n bit is cleared (0) <3> the tm5n register and cr5n register match in t he mode in which clear & start occurs on a match between the tm5n register and the cr5n register caution when connected in cascade, these registers become 0000h ev en when the tce50 bit in the lowest timer (tm50) is cleared. remark n = 0, 1 chapter 9 8-bit timer/event counter 5 preliminary user?s manual u17702ej1v0ud 387 (2) 8-bit timer compare register 5n (cr5n) the cr5n register can be read and written in 8-bit units. in a mode other than the pwm mode, the value set to the cr5n register is always compared to the count value of the tm5n register, and if the two values match, an interrupt request signal (inttm5n) is generated. in the pwm mode, tm5n register overfl ow causes the to5n pin output to chan ge to the active level, and when the values of the tm5n register and the cr5n register match, the to5n pi n output changes to the inactive level. the value of the cr5n register can be set in the range of 00h to ffh. when using the tm50 register and tm51 register in ca scade as a 16-bit timer, the cr50 register and cr51 register operate as 16-bit timer compare register 5 (cr5 ). the counter value and register value are compared in 16-bit lengths, and if they match, an inte rrupt request signal (inttm50) is generated. cr5n (n = 0, 1) 642 after reset: 00h r/w address: cr50 fffff5c2h, cr51 fffff5c3h 0 753 1 cautions 1. in the mode in which clear & start occurs upon a match of the tm5n register and cr5n register (tmc5n.tmc5n6 bit = 0), do not writ e a different value to the cr5n register during the count operation. 2. in the pwm mode, set the cr5n register re write interval to thr ee or more count clocks (clock selected with the tcl5n register). 3. before changing the value of the cr5n re gister when using a cascade connection, be sure to stop the timer operation. remark n = 0, 1 chapter 9 8-bit timer/event counter 5 preliminary user?s manual u17702ej1v0ud 388 9.3 registers the following two registers are used to co ntrol 8-bit timer/event counter 5n. ? timer clock selection register 5n (tcl5n) ? 8-bit timer mode control register 5n (tmc5n) remark to use the functions of the ti5n and to5n pins, refer to table 4-19 settings when port pins are used for alternate functions . (1) timer clock selection register 5n (tcl5n) the tcl5n register sets the count clock of 8-bit timer/event counter 5n and the valid edge of the ti5n pin input. the tcl5n register can be read or written in 8-bit units. after reset, this register is cleared to 00h. falling edge of ti5n rising edge of ti5n f xx f xx /2 f xx /4 f xx /64 f xx /256 inttm010 count clock selection note tcl5n2 0 0 0 0 1 1 1 1 tcl5n1 0 0 1 1 0 0 1 1 tcl5n0 0 1 0 1 0 1 0 1 20 mhz 10 mhz ? ? setting prohibited 100 ns 200 ns 3.2 s 12.8 s ? ? ? 100 ns 200 ns 0.4 s 6.4 s 25.6 s ? clock f xx 0 tcl5n (n = 0, 1) 0 0 0 0 tcl5n2 tcl5n1 tcl5n0 after reset: 00h r/w address: tcl50 fffff5c4h, tcl51 fffff5c5h 76 54 32 1 0 note when the internal clock is selected, set so as to satisfy the following conditions. regc = v dd = 4.0 to 5.5 v: count clock 10 mhz regc = 10 f, v dd = 4.0 to 5.5 v: count clock 5 mhz regc = v dd = 2.7 to 4.0 v: count clock 5 mhz caution before overwriting the tcl5n register with different data, stop the timer operation. remark when the tm5n register is connected in casc ade, the tcl51 register settings are invalid. chapter 9 8-bit timer/event counter 5 preliminary user?s manual u17702ej1v0ud 389 (2) 8-bit timer mode control register 5n (tmc5n) the tmc5n register performs the following six settings. ? controls counting by the tm5n register ? selects the operation m ode of the tm5n register ? selects the individual mode or cascade connection mode ? sets the status of t he timer output flip-flop ? controls the timer output flip-flop or selects the active level in the pwm (free-running timer) mode ? controls timer output the tmc5n register can be read or written in 8-bit or 1-bit units. after reset, this register is cleared to 00h. chapter 9 8-bit timer/event counter 5 preliminary user?s manual u17702ej1v0ud 390 tce5n counting is disabled after the counter is cleared to 0 (counter disabled) start count operation tce5n 0 1 control of count operation of 8-bit timer/event counter 5n tmc5n (n = 0, 1) tmc5n6 0 tmc514 note lvs5n lvr5n tmc5n1 toe5n mode in which clear & start occurs on match between tm5n register and cr5n register pwm (free-running timer) mode tmc5n6 0 1 selection of operation mode of 8-bit timer/event counter 5n individual mode cascade connection mode (connected with 8-bit timer/event counter 50) tmc514 0 1 selection of individual mode or cascade connection mode for 8-bit timer/event counter 51 unchanged reset timer output f/f to 0 set timer output f/f to 1 setting prohibited lvs5n 0 0 1 1 setting of status of timer output f/f lvr5n 0 1 0 1 after reset: 00h r/w address: tmc50 fffff5c6h, tmc51 fffff5c7h disable inversion operation enable inversion operation high active low active tmc5n1 0 1 other than pwm (free-running timer) mode (tmc5n6 bit = 0) controls timer f/f pwm (free-running timer) mode (tmc5n6 bit = 1) selects active level disable output (to5n pin is low level) enable output toe5n 0 1 timer output control <7> 6 5 4 <3> <2> 1 <0> note bit 4 of the tmc50 register is fixed to 0. cautions 1. because the to51 and ti51 pins are al ternate functions of the same pin, only one can be used at one time. 2. the lvs5n and lvr5n bit settings are val id in modes other than the pwm mode. 3. do not set <1> to <4> below at the same time. set as follows. <1> set the tmc5n1 , tmc5n6, and tmc514 note bits: setting of operation mode <2> set the toe5n bit for timer output enable: timer output enable <3> set the lvs5n and lvr5n bits (caution 2): setting of timer output f/f <4> set the tce5n bit remarks 1. in the pwm mode, the pwm output is set to the inactive level by the tce5n bit = 0. 2. when the lvs5n and lvr5n bits are read, 0 is read. 3. the values of the tmc5n6, l vs5n, lvr5n, tmc5n1, and toe 5n bits are reflected to the to5n output regardless of the tce5n bit value. chapter 9 8-bit timer/event counter 5 preliminary user?s manual u17702ej1v0ud 391 9.4 operation 9.4.1 operation as interval timer 8-bit timer/event counter 5n operates as an interval timer t hat repeatedly generates interrupt s at the interval of the count value preset in the cr 5n register. if the count value in the tm5n register matches the value set in the cr5n register, the value of the tm5n register is cleared to 00h and counting is continued, and at the same time, an interrupt request signal (inttm5n) is generated. setting method <1> set each register. ? tcl5n register: selects the count clock (t). ? cr5n register: compare value (n) ? tmc5n register: stops count operation and selects t he mode in which clear & start occurs on a match between the tm5n register and cr5n regist er (tmc5n register = 0000xx00b, : don?t care). <2> when the tmc5n.tce5n bit is set to 1, the count operation starts. <3> when the values of the tm5n regi ster and cr5n register match, the inttm5n signal is generated (tm5n register is cleared to 00h). <4> then, the inttm5n signal is repe atedly generated at the same interval . to stop counting, set the tce5n bit = 0. interval time = (n + 1) t: n = 00h to ffh caution during interval timer operation, do not rewrite the value of the cr5n register. remark n = 0, 1 figure 9-2. timing of interval timer operation (1/2) basic operation t interval time interval time 00h n 01h 01h 00h n n n n n n 01h 00h clear interrupt acknowledgment interrupt acknowledgment clear count clock tm5n count value cr5n tce5n inttm5n count start remark n = 0, 1 chapter 9 8-bit timer/event counter 5 preliminary user?s manual u17702ej1v0ud 392 figure 9-2. timing of interval timer operation (2/2) when cr5n register = 00h t interval time 00h 00h 00h 00h 00h count clock tm5n count value cr5n tce5n inttm5n remark n = 0, 1 when cr5n register = ffh t 01h 00h feh ffh 00h feh ffh 00h ffh ffh ffh count clock tm5n count value cr5n tce5n inttm5n interval time interrupt acknowledgment interrupt acknowledgment remark n = 0, 1 chapter 9 8-bit timer/event counter 5 preliminary user?s manual u17702ej1v0ud 393 9.4.2 operation as external event counter the external event counter c ounts the number of clock pulses input to the ti5n pin from an external source by using the tm5n register. each time the valid edge specified by the tcl5n register is input to the ti5n pin, the tm5n register is incremented. either the rising edge or the falling e dge can be specified as the valid edge. when the count value of the tm5n regist er matches the value of the cr5n regi ster, the tm5n register is cleared to 00h and an interrupt request signal (inttm5n) is generated. setting method <1> set each register. ? tcl5n register: selects the ti5n pin input edge. falling edge of ti5n pin tlc5n register = 00h rising edge of ti5n pin tcl5n register = 01h ? cr5n register: compare value (n) ? tmc5n register: stops count operation, selects t he mode in which clear & start occurs on a match between the tm5n register and cr5n register , disables timer output f/f inversion operation, and disables timer output. (tmc5n register = 0000xx00b, : don?t care) ? for the alternate-function pin settings, refer to table 4-19 settings when port pins are used for alternate functions. <2> when the tmc5n.tce5n bit is set to 1, the counter co unts the number of pulses in put from the ti5n pin. <3> when the values of the tm5n regi ster and cr5n register match, the inttm5n signal is generated (tm5n register is cleared to 00h). <4> then, the inttm5n signal is generat ed each time the values of t he tm5n register and cr5n register match. inttm5n signal is generated when the valid edge of ti5n pin is input n + 1 times: n = 00h to ffh caution during external event counter operation, do not rewrite the value of the cr5n register. remark n = 0, 1 figure 9-3. timing of external event coun ter operation (with rising edge specified) 00h 01h 02h 03h 04h 05h n ? 1n n 00h 01h 02h 03h ti5n cr5n inttm5n tce5n tm5n count value count start remark n = 0, 1 chapter 9 8-bit timer/event counter 5 preliminary user?s manual u17702ej1v0ud 394 9.4.3 square-wave output operation a square wave with any frequency can be output at an interval determined by the value preset in the cr5n register. by setting the tmc5n.toe5n bit to 1, the output status of the to5n pin is inverted at an interval determined by the count value preset in the cr 5n register. in this way, a square wave of any frequency can be output (duty = 50%) (n = 0, 1). setting method <1> set each register. ? tcl5n register: selects the count clock (t). ? cr5n register: compare value (n) ? tmc5n register: stops count operation, selects t he mode in which clear & start occurs on a match between the tm5n register and cr5n register, sets initial value of timer output, enables timer output f/f inversion operation, and enables timer output. (tmc5n register = 00001011b or 00000111b) ? for the alternate-function pin settings, refer to table 4-19 settings when port pins are used for alternate functions. <2> when the tmc5n.tce5n bit is set to 1, counting starts. <3> when the values of the tm5n register and cr5n regi ster match, the timer output f/f is inverted. moreover, the inttm5n signal is generated and the tm5n register is cleared to 00h. <4> then, the timer output f/f is inve rted during the same interval and a s quare wave is output from the to5n pin. frequency = 1/2t(n + 1): n = 00h to ffh caution do not rewrite the value of the cr5n register during square-wave output. chapter 9 8-bit timer/event counter 5 preliminary user?s manual u17702ej1v0ud 395 figure 9-4. timing of square-wave output operation t interval time interval time 00h n 01h 01h 00h n n n n n n 01h 00h clear interrupt acknowledgment interrupt acknowledgment clear count clock tm5n count value cr5n to5n note tce5n inttm5n count start note the initial value of the to5n pin output can be set using the tmc5n.lvs5n and tmc5n.lvr5n bits. remark n = 0, 1 chapter 9 8-bit timer/event counter 5 preliminary user?s manual u17702ej1v0ud 396 9.4.4 8-bit pwm output operation by setting the tmc5n.tmc5n6 bit to 1, 8-bit ti mer/event counter 5n performs pwm output. pulses with a duty factor determined by the value set in the cr5n register are out put from the to5n pin. set the width of the active level of the pwm pulse in t he cr5n register. the active level can be selected using the tmc5n.tmc5n1 bit. the count clock can be select ed using the tcl5n register. pwm output can be enabled/disabled by the tmc5n.toe5n bit. caution the cr5n register rewrite interval must be three or more operation clocks (set by the tcl5n register). use method <1> set each register. ? tcl5n register: selects the count clock (t). ? cr5n register: compare value (n) ? tmc5n register: stops count operation, se lects pwm mode, and leave timer output f/f unchanged, sets active level, and enables timer output. (tmc5n register = 01000001b or 01000011b) ? for the alternate-function pin settings, refer to table 4-19 settings when port pins are used for alternate functions. <2> when the tmc5n.tce5n bit is set to 1, counting starts. pwm output operation <1> when counting starts, pwm output (output from the to5n pin) outputs the inactive level until an overflow occurs. <2> when an overflow occurs, the active level set by setting method <1> is output. the active level is output until the value of the cr5n register and the count value of the tm5n register match. an interrupt request signal (inttm5n) is generated. <3> when the value of the cr5n register and the count value of the tm5n register match, the inactive level is output and continues to be output until an overflow occurs again. <4> then, steps <2> and <3> are repeat ed until counting is stopped. <5> when counting is stopped by clearing tce5n bit to 0, pwm output becomes inactive. cycle = 256t, active level width = nt, duty = n/256: n = 00h to ffh remarks 1. n = 0, 1 2. for the detailed timing, refer to figure 9-5 timing of pwm output operation and figure 9-6 timing of operation b ased on cr5n register transitions . chapter 9 8-bit timer/event counter 5 preliminary user?s manual u17702ej1v0ud 397 (a) basic operation of pwm output figure 9-5. timing of pwm output operation basic operation (active level = h) 00h n + 1 n n 00h m 00h ffh 01h 02h 01h 00h ffh 02h 01h active level inactive level active level count clock tm5n count value cr5n tce5n inttm5n to5n t when cr5n register = 00h 00h n + 1 n + 2 n 00h 00h m 00h ffh 01h 02h 01h 00h ffh 02h 01h inactive level inactive level count clock tm5n count value cr5n tce5n inttm5n to5n t when cr5n register = ffh 00h n + 1 n + 2 n ffh 00h m 00h ffh 01h 02h 01h 00h ffh 02h 01h inactive level inactive level inactive level active level active level count clock tm5n count value cr5n tce5n inttm5n to5n t remark n = 0, 1 chapter 9 8-bit timer/event counter 5 preliminary user?s manual u17702ej1v0ud 398 (b) operation based on cr5n register transitions figure 9-6. timing of operation b ased on cr5n register transitions when the value of the cr5n register changes from n to m before the rising edge of the ffh clock the value of the cr5n register is transferred at the overflow that occurs immediately after. n n + 1 n + 2 m n <1> cr5n transition (n m) m m + 1 m + 2 m m + 1 m + 2 ffh 02h 00h 01h ffh 02h 00h 01h count clock tm5n count value cr5n tce5n h inttm5n to5n <2> t when the value of the cr5n register changes from n to m after the rising edge of the ffh clock the value of the cr5n register is transferred at the second overflow. n n + 1 n + 2 n nn <1> cr5n transition (n m) m n + 1 n + 2 m m + 1 m + 2 ffh 03h 02h 00h 01h ffh 02h 00h 01h count clock tm5n count value cr5n tce5n h inttm5n to5n <2> t caution in the case of reload from the cr5n register between <1> and <2>, the value that is actually used differs (read value: m; actu al value of cr5n register: n). remark n = 0, 1 chapter 9 8-bit timer/event counter 5 preliminary user?s manual u17702ej1v0ud 399 9.4.5 operation as inter val timer (16 bits) the 16-bit resolution timer/event counter mode is se lected by setting the tmc51.tmc514 bit to 1. 8-bit timer/event counter 5n operates as an interval time r by repeatedly generating inte rrupts using the count value preset in 16-bit timer compare register 5 (cr5) as the interval. setting method <1> set each register. ? tcl50 register: selects the count clock (t) (the tcl51 register does not need to be set in cascade connection) ? cr50 register: compare value (n) ... lower 8 bits (settable from 00h to ffh) ? cr51 register: compare value (n) ... higher 8 bits (settable from 00h to ffh) ? tmc50, tmc51 register: selects the mode in wh ich clear & start occurs on a match between tm5 register and cr5 register ( : don?t care) tmc50 register = 0000xx00b tmc51 register = 0001xx00b <2> set the tmc51.tce51 bit to 1. then set the tmc 50.tce50 bit to 1 to start the count operation. <3> when the values of the tm5 r egister and cr5 register connected in cascade match, the inttm50 signal is generated (the tm5 register is cleared to 0000h). <4> the inttm50 signal is then generated repeatedly at the same interval. interval time = (n + 1) t: n = 0000h to ffffh cautions 1. to write using 8-bit access during cascade connection, set th e tce51 bit to 1 at operation start and then set the tce50 bit to 1. when operation is stopped, clear the tce50 bit to 0 and then clear the tce51 bit to 0. 2. during cascade connection, ti50 input, to50 output, and the inttm50 signal are used. do not use ti51 input, to51 out put, and the inttm51 signal; mask them instead (for details, refer to chapte r 21 interrupt/exception processing function). clear the lvs51, lvr51, tmc511, and toe51 bits to 0. 3. do not change the value of the cr5 register during timer operation. chapter 9 8-bit timer/event counter 5 preliminary user?s manual u17702ej1v0ud 400 figure 9-7 shows a timing example of the cascade connection mode with 16-bit resolution. figure 9-7. cascade connection mode with 16-bit resolution 00h n + 1 01h 00h ffh 00h 01h ffh 00h ffh m ? 1 01h 00h 00h na 01h 00h 02h m 00h 00h b n n m interval time operation enabled, count start interrupt occurrence, counter cleared operation stopped count clock tm50 count value tm51 count value tce51 inttm50 cr51 tce50 cr50 t chapter 9 8-bit timer/event counter 5 preliminary user?s manual u17702ej1v0ud 401 9.4.6 operation as external event counter (16 bits) the 16-bit resolution timer/event counter mode is selected by setting the tmc51.tmc514 bit to 1. the external event counter counts the number of clock pulse s input to the ti50 pin from an external source using 16-bit timer counter 5 (tm5). setting method <1> set each register. ? tcl50 register: selects the ti50 pin input edge. (the tcl51 register does not have to be set during cascade connection.) falling edge of ti50 pin tcl50 register = 00h rising edge of ti50 pin tcl50 register = 01h ? cr50 register: compare value (n) ... lower 8 bits (settable from 00h to ffh) ? cr51 register: compare value (n) ... higher 8 bits (settable from 00h to ffh) ? tmc50, tmc51 registers: stops count operation, selects the clear & stop mode entered on a match between the tm5 register and cr5 regi ster, disables timer output f/f inversion, and disables timer output. ( : don?t care) tmc50 register = 0000xx00b tmc51 register = 0001xx00b ? for the alternate-function pin settings, refer to table 4-19 settings when port pins are used for alternate functions. <2> set the tmc51.tce51 bit to 1. then set the tmc 50.tce50 bit to 1 and count the number of pulses input from the ti50 pin. <3> when the values of the tm5 r egister and cr5 register connected in cascade match, the inttm50 signal is generated (the tm5 register is cleared to 0000h). <4> the inttm50 signal is then generated each time the va lues of the tm5 register and cr5 register match. inttm50 signal is generated when t he valid edge of ti50 pin is input n + 1 times: n = 0000h to ffffh cautions 1. during external event counter opera tion, do not rewrite the value of the cr5n register. 2. to write using 8-bit access during cascade connection, set the tce51 bit to 1 and then set the tce50 bit to 1. when operation is stopped, clear the tce50 bit to 0 and then clear the tce51 bit to 0 (n = 0, 1). 3. during cascade connection, ti50 input and the inttm50 si gnal are used. do not use ti51 input, to51 output, and the inttm51 signal; mask them instead (for details, refer to chapter 21 interrupt/except ion processing function). clear the lvs51, lvr51, tmc511, and toe51 bits to 0. 4. do not change the value of the cr5 regi ster during external event counter operation. chapter 9 8-bit timer/event counter 5 preliminary user?s manual u17702ej1v0ud 402 9.4.7 square-wave output operat ion (16-bit resolution) the 16-bit resolution timer/event counter mode is se lected by setting the tmc51.tmc514 bit to 1. 8-bit timer/event counter 5n outputs a square wave of any frequency using the interval preset in 16-bit timer compare register 5 (cr5). setting method <1> set each register. ? tcl50 register: selects the count clock (t) (the tcl51 register does not have to be set in cascade connection) ? cr50 register: compare value (n) ... lower 8 bits (settable from 00h to ffh) ? cr51 register: compare value (n) ... higher 8 bits (settable from 00h to ffh) ? tmc50, tcm51 registers: stops count operation, se lects the mode in which clear & start occurs on a match between the tm5 register and cr5 register. lvs50 lvr50 timer output f/f status settings 1 0 high-level output 0 1 low-level output enables timer output f/f inversion, and enables timer output. tmc50 register = 00001011b or 00000111b tmc51 register = 00010000b ? for the alternate-function pin settings, refer to table 4-19 settings when port pins are used for alternate functions. <2> set the tmc51.tce51 bit to 1. then set the tmc 50.tce50 bit to 1 to start the count operation. <3> when the values of the tm5 regi ster and the cr5 register connected in cascade match, the to50 timer output f/f is inverted. moreover, the inttm50 sign al is generated and the tm 5 register is cleared to 0000h. <4> then, the timer output f/f is inve rted during the same interval and a s quare wave is output from the to50 pin. frequency = 1/2t(n + 1): n = 0000h to ffffh caution do not write a different value to the cr5 register during operation. chapter 9 8-bit timer/event counter 5 preliminary user?s manual u17702ej1v0ud 403 9.4.8 cautions (1) error on starting timer an error of up to 1 clock occurs before the match signal is generated after the timer has been started. this is because the tm5n register is started a synchronously to the count pulse. figure 9-8. count start timing of tm5n register 00h timer start 01h 02h 03h 04h count pulse tm5n count value remark n = 0, 1 preliminary user?s manual u17702ej1v0ud 404 chapter 10 8-bit timer h in the v850es/kj2, two channels of 8-bit timer h are provided. 10.1 functions 8-bit timer hn has the following functions (n = 0, 1). ? interval timer ? square ware output ? pwm output ? carrier generator 10.2 configuration 8-bit timer hn consists of the following hardware. table 10-1. configuration of 8-bit timer hn item configuration timer registers 8-bit ti mer counter hn: 1 each register 8-bit timer h compare register n0 (cmpn0): 1 each 8-bit timer h compare register n1 (cmpn1): 1 each timer outputs tohn, output controller control registers note 8-bit timer h mode register n (tmhmdn) 8-bit timer h carrier control register n (tmcycn) note to use the tohn pin function, refer to table 4-19 settings when port pins are used for alternate functions . remark n = 0, 1 chapter 10 8-bit timer h preliminary user?s manual u17702ej1v0ud 405 the block diagram is shown below. figure 10-1. block diag ram of 8-bit timer hn match selector internal bus tmhen ckshn2 ckshn1 ckshn0 tmmdn1tmmdn0 tolevn toenn decoder 8-bit timer h compare register n0 (cmpn0) reload/ interrupt control tohn inttmhn inttm5n selector rmc n nrzb n f xx f xx /2 f xx /2 2 f xx /2 4 f xx /2 6 note interrupt generator output controller level inversion nrz n 1 0 f/f r 8-bit timer counter hn carrier generator mode signal pwm mode signal timer h enable signal clear 3 2 8-bit timer h compare register n1 (cmpn1) 8-bit timer h mode register n (tmhmdn) 8-bit timer h carrier control register n (tmcycn) note f xx /2 10 when n = 0, f xt when n = 1 remark n = 0, 1 (1) 8-bit timer h compare register n0 (cmpn0) this register can be read or written in 8-bit units. this register is used in all of the timer operation modes. this register constantly compares the value set to the cmpn0 register with the count value of 8-bit timer counter hn and, when the two values match, generates an interrupt request signal (inttmhn) and inverts the output level of the tohn pin. rewrite the value of the cmpn0 register while the timer is stopped (tmhmdn.tmhen bit = 0). reset sets this register to 00h. cmpn0 (n = 0, 1) after reset: 00h r/w address: cmp00 fffff582h, cmp10 fffff592h 76 54 32 1 0 caution rewriting the cmpn0 register during timer count operation is prohibited. chapter 10 8-bit timer h preliminary user?s manual u17702ej1v0ud 406 (2) 8-bit timer h compare register n1 (cmpn1) this register can be read or written in 8-bit units. this register is used in the pwm out put mode and carrier generator mode. in the pwm output mode, this register constantly compares the value set to the cmpn1 register with the count value of 8-bit timer counter hn and, when the two values match, inverts the output leve l of the tohn pin. no interrupt request signal is generated. in the carrier generator mode, the cm pn1 register always compares the value set to the cmpn1 register with the count value of 8-bit timer counter hn and, when the two values match, generates an interrupt request signal (inttmhn). at the same time, the count value is cleared. the cmpn1 register can be rewri tten during timer count operation. if the value of the cmpn1 register is rewritten while the timer is operat ing, the new value is latched and transferred to the cmpn1 register when the count valu e of the timer matches the old value of the cmpn1 register, and then the value of the cmp n1 register is changed to the new val ue. if matching of the count value and the cmpn1 register value and writing a value to the cmpn1 register conflict, the value of the cmpn1 register is not changed. reset sets this register to 00h. cmpn1 (n = 0, 1) after reset: 00h r/w address: cmp01 fffff583h, cmp11 fffff593h 76 54 32 1 0 the cmpn1 register can be rewritt en during timer count operation. in the carrier generator mode, after the cmpn1 register is set, if the count value of 8-bit timer counter hn and the set value of the cmpn1 register match, an interrupt request signal (in ttmhn) is generated. at the same time, the value of 8-bit timer counter hn is cleared to 00h. if the set value of the cmpn1 register is rewritten dur ing timer operation, the reload timing is when the count value of 8-bit timer counter hn and the set value of the cmpn1 register match. if the transfer timing and write to the cmpn1 register from the cpu conflict, transfer is not performed. caution in the pwm output mode a nd carrier generator mode, be su re to set the cmpn1 register when starting the timer count operation (t mhmdn.tmhen bit = 1) after the timer count operation was stopped (tmhen bit = 0) (be sure to set again even if setting the same value to the cmpn1 register). chapter 10 8-bit timer h preliminary user?s manual u17702ej1v0ud 407 10.3 registers the registers that control 8-bit timer hn are as follows. ? 8-bit timer h mode register n (tmhmdn) ? 8-bit timer h carrier control register n (tmcycn) remarks 1. to use the tohn pin function, refer to table 4-19 settings when port pins are used for alternate functions . 2. n = 0, 1 (1) 8-bit timer h mode register n (tmhmdn) the tmhmdn register controls the mode of 8-bit timer hn. tmhmdn register can be read or written in 8-bit or 1-bit units. after reset, tmhmdn is cleared to 00h. remark n = 0, 1 chapter 10 8-bit timer h preliminary user?s manual u17702ej1v0ud 408 (a) 8-bit timer h mode register 0 (tmhmd0) tmhe0 stop timer count operation (8-bit timer counter h0 = 00h) enable timer count operation (counting starts when clock is input) tmhe0 0 1 8-bit timer h0 operation enable tmhmd0 cksh02 cksh01 cksh00 tmmd01 tmmd00 tolev0 toen0 after reset: 00h r/w address: fffff580h f xx f xx /2 f xx /4 f xx /16 f xx /64 f xx /1024 cksh02 0 0 0 0 1 1 cksh01 0 0 1 1 0 0 cksh00 0 1 0 1 0 1 setting prohibited 125 ns 250 ns 1 s 4 s 64 s selection of count clock count clock note interval timer mode carrier generator mode pwm output mode setting prohibited tmmd01 0 0 1 1 tmmd00 0 1 0 1 8-bit timer h0 operation mode other than above low level high level tolev0 0 1 timer output level control (default) disable output enable output toen0 0 1 timer output control f xx = 16.0 mhz <7> 6 5 4 3 2 <1> <0> setting prohibited f xx = 10.0 mhz setting prohibited 100 ns 200 ns 800 ns 1.6 s 51.2 s f xx = 20 mhz 100 ns 200 ns 400 ns 1.6 s 6.4 s 102.4 s note set so as to satisfy the following conditions. regc = v dd = 4.0 to 5.5 v: count clock 10 mhz regc = 10 f, v dd = 4.0 to 5.5 v: count clock 5 mhz regc = v dd = 2.7 to 4.0 v: count clock 5 mhz cautions 1. when the tmhe0 bit = 1, setting bits other than those of the tmhmd0 register is prohibited. 2. in the pwm output mode and carrier generator mode, be sure to set the cmp01 register when starting the timer count ope ration (tmhe0 bit = 1) after the timer count operation was stopped (tmhe0 bit = 0) (be sure to set again even if setting the same value to th e cmp01 register). 3. when using the carrier generator mode , set 8-bit timer h0 count clock frequency to six times 8-bit timer/event counter 50 count clock frequency or higher. chapter 10 8-bit timer h preliminary user?s manual u17702ej1v0ud 409 (b) 8-bit timer h mode register 1 (tmhmd1) tmhe1 stop timer count operation (8-bit timer counter h1 = 00h) enable timer count operation (counting starts when clock is input) tmhe1 0 1 8-bit timer h1 operation enable tmhmd1 cksh12 cksh11 cksh10 tmmd11 tmmd10 tolev1 toen1 after reset: 00h r/w address: fffff590h f xx f xx /2 f xx /4 f xx /16 f xx /64 cksh12 0 0 0 0 1 1 cksh11 0 0 1 1 0 0 cksh10 0 1 0 1 0 1 setting prohibited 125 ns 250 ns 1 s 4 s selection of count clock count clock note interval timer mode carrier generator mode pwm output mode setting prohibited tmmd11 0 0 1 1 tmmd10 0 1 0 1 8-bit timer h1 operation mode f xt (subclock) setting prohibited other than above low level high level tolev1 0 1 timer output level control (default) disable output enable output toen1 0 1 timer output control f xx = 16.0 mhz <7> 6 5 4 3 2 <1> <0> setting prohibited 100 ns 200 ns 800 ns 1.6 s f xx = 20.0 mhz f xx = 10.0 mhz 100 ns 200 ns 400 ns 1.6 s 6.4 s note set so as to satisfy the following conditions. regc = v dd = 4.0 to 5.5 v: count clock 10 mhz regc = 10 f, v dd = 4.0 to 5.5 v: count clock 5 mhz regc = v dd = 2.7 to 4.0 v: count clock 5 mhz cautions 1. when the tmhe1 bit = 1, setting bits other than those of the tmhmd1 register is prohibited. 2. in the pwm output mode and carrier generator mode, be sure to set the cmp11 register when starting the timer count ope ration (tmhe1 bit = 1) after the timer count operation was stopped (tmhe1 bit = 0) (be sure to set again even if setting the same value to th e cmp11 register). 3. when using the carrier generator mode , set 8-bit timer h1 count clock frequency to six times 8-bit timer/event counter 51 count clock frequency or higher. chapter 10 8-bit timer h preliminary user?s manual u17702ej1v0ud 410 (2) 8-bit timer h carrier cont rol register n (tmcycn) this register controls the 8-bit timer hn remote control output and carrier pulse output status. tmcycn register can be read or written in 8-bit or 1-bit units. the nrzn bit is a read-only bit. after reset, tmcycn is cleared to 00h. remark n = 0, 1 0 tmcycn (n = 0, 1) 0 0 0 0 rmcn nrzbn nrzn after reset: 00h r/w address: tmcyc0 fffff581h, tmcyc1 fffff591h low-level output high-level output low-level output carrier pulse output rmcn 0 0 1 1 nrzbn 0 1 0 1 remote control output carrier output disabled status (low-level status) carrier output enable status nrzn 0 1 carrier pulse output status flag 76 54 32 1<0> chapter 10 8-bit timer h preliminary user?s manual u17702ej1v0ud 411 10.4 operation 10.4.1 operation as interval timer/square wave output when the count value of 8-bit timer counter hn and the set value of the cmpn0 register match, an interrupt request signal (inttmhn) is generated and 8-bit timer counter hn is cleared to 00h. the cmpn1 register cannot be used in the interval timer mode. even if the cmpn1 register is set, this has no effect on the timer output because matches between 8-bit timer counter hn and the cmpn1 regi ster are not detected. a square wave of the desired frequency (duty = 50%) is out put from the tohn pin, by setting the tmhmdn.toenn bit to 1. remarks 1. for the alternate-function pin (tohn) settings, refer to table 4-19 settings when port pins are used for alternate functions . 2. for inttmhn interrupt enable, refer to chapter 21 interrupt/exception processing function . setting <1> set each register. figure 10-2. register settings in interval timer mode (i) 8-bit timer h mode register n (tmhmdn) settings 0 0/1 0/1 0/1 0 sets timer output sets timer output default level sets interval timer mode selects count clock (f cnt ) stops count operation 0 0/1 0/1 tmmdn0 tolevn toenn ckshn1 ckshn2 tmhen tmhmdn ckshn0 tmmdn1 (ii) cmpn0 register settings the interval time is as follows if n is set as a comparison value. ? interval time = (n + 1)/f cnt <2> when the tmhen bit is set to 1, counting starts. <3> when the count value of 8-bit timer counter hn an d the set value of the cmpn0 register match, the inttmhn signal is generated and 8-bit timer counter hn is cleared to 00h. <4> then, the inttmhn signal is generated in the same in terval. to stop the count operation, clear the tmhen bit to 0. chapter 10 8-bit timer h preliminary user?s manual u17702ej1v0ud 412 figure 10-3. timing of interval timer/ square wave output operation (1/2) basic operation (operation when 01h cmpn0 feh) 00h count clock count start 8-bit timer counter hn count value cmpn0 tmhen inttmhn tohn 01h n clear clear n 00h 01h n 00h 01h 00h <1> <2> level inversion, match interrupt occurrence, 8-bit timer counter clear <2> level inversion, match interrupt occurrence, 8-bit timer counter clear <3> interval time <1> when the tmhen bit is set to 1, the count operation is enabled. the count clock starts counting no more than one clock after operation has been enabled. <2> when the count value of 8-bit timer counter hn and t he set value of the cmpn0 r egister match, the value of 8-bit timer counter hn is cleared, the tohn outpu t level is inverted, and the inttmhn signal is output at the rising edge of the count clock. <3> the inttmhn signal and tohn output are set to t he default level when the tmhen bit is cleared to 0 during 8-bit timer hn operation. if the level is alre ady at the default level bef ore the tmhmdn.tmhen bit is cleared to 0, that level is maintained. remarks 1. n = 0, 1 2. 01h n feh chapter 10 8-bit timer h preliminary user?s manual u17702ej1v0ud 413 figure 10-3. timing of interval timer/ square wave output operation (2/2) operation when cmpn0 = ffh 00h count clock count start cmpn0 tmhen inttmhn tohn 01h feh clear clear ffh 00h feh ffh 00h ffh interval time 8-bit timer counter hn count value operation when cmpn0 = 00h count clock count start cmpn0 tmhen inttmhn tohn 00h 00h interval time 8-bit timer counter hn count value remark n = 0, 1 chapter 10 8-bit timer h preliminary user?s manual u17702ej1v0ud 414 10.4.2 pwm output mode operation in the pwm output mode, a pulse of any duty and cycle can be output. the cmpn0 register controls the time r output (tohn) cycle. rewriting the cmpn0 register during timer operation is prohibited. the cmpn1 register controls the time r output (tohn) duty. the cmpn1 r egister can be rewritten during timer operation. the operation in the pwm out put mode is as follows. after timer counting starts, when the count value of 8-bit timer counter hn and the set value of the cmpn0 register match, the tohn output level is invert ed and 8-bit timer counter hn is cleared to 00h. when the count value of 8-bit timer counter hn and the set value of the cmpn1 regi ster match, the tohn output level is inverted. remarks 1. for the alternate-function pin (tohn) settings, refer to table 4-19 settings when port pins are used for alternate functions . 2. for inttmhn interrupt enable, refer to chapter 21 interrupt/exception processing function . setting <1> set each register. figure 10-4. register settings in pwm output mode (i) 8-bit timer h mode register n (tmhmdn) settings 0 0/1 0/1 0/1 1 enables timer output sets timer output default level selects pwm output mode selects count clock (f cnt ) stops count operation 0 0/1 1 tmmdn0 tolevn toenn ckshn1 ckshn2 tmhen tmhmdn ckshn0 tmmdn1 (ii) cmpn0 register setting ? compare value (n): sets cycle (ii) cmpn1 register setting ? compare value (m): sets duty remarks 1. n = 0, 1 2. 00h cmpn1 (m) < cmpn0 (n) ffh <2> when the tmhen bit is set to 1, counting starts. chapter 10 8-bit timer h preliminary user?s manual u17702ej1v0ud 415 <3> after the count operation is enabled, the first com pare register to be compared is the cmpn0 register. when the count value of 8-bit timer counter hn and the set value of the cmpn0 register match , 8-bit timer counter hn is cleared, an interrupt request signal (in ttmhn) is generated, and the tohn output level is inverted. at the same time, the register that is compared with 8-bit timer counter hn changes from the cmpn0 register to the cmpn1 register. <4> when the count value of 8-bit timer counter hn and t he set value of the cmpn1 re gister match, the tohn output level is inverted, and at the same time the register that is compared with 8-bit timer counter hn changes from the cmpn1 register to the cmpn0 register. at this time, 8-bit timer counter hn is not cleared and the inttmhn signal is not generated. <5> a pulse of any duty can be obtained throug h the repetition of steps <3> and <4> above. <6> to stop the count operation, clear the tmhen bit to 0. designating the set value of the cmpn0 register as (n), the set value of th e cmpn1 register as (m), and the count clock frequency as f cnt , the pwm pulse output cycle and duty are as follows. pwm pulse output cycle = (n + 1)/f cnt duty = inactive width: active width = (m + 1) : (n + 1) cautions 1. the set value of the cmpn1 register ca n be changed while the time r counter is operating. however, this takes a duration of at least three operating clocks (signal selected by the ckshn2 to ckshn0 bits of the tmhmdn regi ster) from when the value of the cmpn1 register is changed until the value is transferred to the register. 2. be sure to set the cmpn1 register when starting the timer count operation (tmhen bit = 1) after the timer count operation was stopped (tmhen bit = 0) (be sure to set again even if setting the same value to the cmpn1 register). 3. make sure that the cmpn1 register set value (m) and cmpn 0 register set value (n) are within the following range. 00h cmpn1 (m) < cmpn0 (n) ffh chapter 10 8-bit timer h preliminary user?s manual u17702ej1v0ud 416 figure 10-5. operation timing in pwm output mode (1/4) basic operation count clock cmpn0 tmhen inttmhn tohn (tolevn = 0) tohn (tolevn = 1) 00h 01h a5h 00h 01h 02h a5h 00h a5h 00h 01h 02h <1> <3> <2> cmpn1 <4> a5h 01h 8-bit timer counter hn count value <1> when the tmhen bit is set to 1, counting starts. at this time tohn output remains the default level. <2> when the count value of 8-bit timer counter hn and t he set value of the cmpn0 r egister match, the tohn output level is inverted, 8-bit timer counter hn is cleared, and the inttmhn signal is output. <3> when the count value of 8-bit timer counter hn and t he set value of the cmpn1 r egister match, the tohn output level is inverted. at this time, the value of 8-bit timer counter hn is not cleared and the inttmhn signal is not output. <4> when the tmhen bit is cleared to 0 during 8-bit timer hn operation, the inttmhn signal and tohn output are set to the default level. remark n = 0, 1 chapter 10 8-bit timer h preliminary user?s manual u17702ej1v0ud 417 figure 10-5. operation timing in pwm output mode (2/4) operation when cmpn0 = ffh, cmpn1 = 00h count clock cmpn0 tmhen inttmhn tohn (tolevn = 0) 00h 01h ffh 00h 01h 02h ffh 00h ffh 00h 01h 02h cmpn1 ffh 00h 8-bit timer counter hn count value operation when cmpn0 = ffh, cmpn1 = feh count clock cmpn0 tmhen inttmhn tohn (tolevn = 0) 00h 01h feh ffh 00h 01h feh ffh 00h 01h feh ffh 00h cmpn1 ffh feh 8-bit timer counter hn count value remark n = 0, 1 chapter 10 8-bit timer h preliminary user?s manual u17702ej1v0ud 418 figure 10-5. operation timing in pwm output mode (3/4) operation when cmpn0 = 01h, cmpn1 = 00h count clock cmpn0 tmhen inttmhn tohn (tolevn = 0) 01h 00h 01h 00h 01h 00h 00h 01h 00h 01h cmpn1 00h 8-bit timer counter hn count value remark n = 0, 1 chapter 10 8-bit timer h preliminary user?s manual u17702ej1v0ud 419 figure 10-5. operation timing in pwm output mode (4/4) operation by changing cmpn1 (cmpn1 = 02h 03h, cmpn0 = a5h) count clock 8-bit timer counter hn cmpn0 tmhen inttmhn tohn (tolevn = 0) 00h 01h 02h a5h 00h 01h 02h 03h a5h 00h 01h 02h 03h a5h 00h <1> <4> <3> <2> cmpn1 <6> <5> 02h a5h 03h 02h (03h) <2>? 80h <1> when the tmhen bit is set to 1, counting starts. at this time, the tohn output remains the default level. <2> the set value of the cmpn1 register can be changed during count operati on. this operation is asynchronous to the count clock. <3> when the count value of 8-bit timer counter hn and t he set value of the cmpn0 register match, 8-bit timer counter hn is cleared, the tohn output level is in verted, and the inttmhn signal is generated. <4> even if the value of the cmpn1 register is chang ed, that value is latched and not transferred to the register. when the count value of 8-bit timer counter hn and the set value of the cmpn1 register prior to the change match, the changed value is transferred to the cmpn1 register and the value of the cmpn1 register is changed (<2>?). however, three or more count clocks are required fr om the time the value of the cmpn1 register is changed until it is transferred to the register. even if a match signal is generated within three count clocks, the changed valu e cannot be transferred to the register. <5> when the count value of 8-bit timer counter hn ma tches the changed set value of the cmpn1 register, the tohn output level is inverted. 8-bit timer count er hn is not cleared and the inttmhn signal is not generated. <6> when the tmhen bit is cleared to 0 during 8-bit timer hn operation, the inttmhn signal and tohn output are set to the default level. chapter 10 8-bit timer h preliminary user?s manual u17702ej1v0ud 420 10.4.3 carrier genera tor mode operation the carrier clock generated by 8-bit timer hn is output using the cycle set with 8-bit timer/event counter 5n. in the carrier generator mode, 8-bit timer/ event counter 5n is used to control the extent to wh ich the carrier pulse of 8-bit timer hn is output, and the carrier pulse is output from the tohn output. remarks 1. for the alternate-function pin (tohn) settings, refer to table 4-19 settings when port pins are used for alternate functions . 2. for inttmhn interr upt enable, refer to chapter 21 interrupt/exception processing function . (1) carrier generation in the carrier generator mode, the cmpn0 register gener ates a waveform with the low-level width of the carrier pulse and the cmpn1 register generates a waveform with the high-level width of the carrier pulse. during 8-bit timer hn operation, the cmpn1 register can be rewritten, but rewriting of the cmpn0 register is prohibited. (2) carrier output control carrier output control is performed wit h the interrupt request signal (inttm 5n) of 8-bit timer/event counter 5n and the tmcycn.nrzbn and tmcycn.rmcn bits. t he output relationships are as follows. rmcn bit nrzbn bit output 0 0 low level output 0 1 high level output 1 0 low level output 1 1 carrier pulse output remark n = 0, 1 chapter 10 8-bit timer h preliminary user?s manual u17702ej1v0ud 421 to control carrier pulse output during count operati on, the tmcycn.nrzn and tm cycn.nrzbn bits have a master and slave bit configuration. the nrzn bit is read-only while the nrzbn bit can be read and written. the inttm5n signal is synchronized with the 8-bit timer hn clock and output as the inttm5hn signal. the inttm5hn signal becomes the data transfer signal of the nrzn bit and the value of the nrzbn bit is transferred to the nrzn bit. the transfer timing from the nrzbn bit to the nrzn bit is as follows. figure 10-6. transfer timing 8-bit timer hn count clock tmhen inttm5n inttm5hn nrzn nrzbn rmcn 1 1 1 0 00 <1> <2> <3> <1> the inttm5n signal is synchronized with the count clock of 8-bit timer hn and is output as the inttm5hn signal. <2> the value of the nrzbn bit is transferred to the nrzn bit at the second clock from the rising edge of the inttm5hn signal. <3> write the next value to the nrzbn bit in the inte rrupt servicing programming that has been started by the inttm5hn interrupt or after timing has been chec ked by polling the interrupt request flag. write data to count the next time to the cr5n register. cautions 1. do not rewrite the nrzbn bit again until at least the second cl ock after it has been rewritten, or else transfer from the nrzbn bit to the nrzn bit is not guaranteed. 2. when using 8-bit timer/event counter 5n in the carrier generator mode, an interrupt occurs at the timing of <1>. an interrupt o ccurs at a different timing when it is used in other than the carrier generator mode. remark n = 0, 1 chapter 10 8-bit timer h preliminary user?s manual u17702ej1v0ud 422 setting <1> set each register. figure 10-7. register settings in carrier generator mode ? 8-bit timer h mode register n (tmhmdn) 0 0/1 0/1 0/1 0 enables timer output sets timer output default level selects carrier generator mode selects count clock (f cnt ) stops count operation 1 0/1 1 tmmdn0 tolevn toenn ckshn1 ckshn2 tmhen tmhmdn ckshn0 tmmdn1 ? cmpn0 register: compare value ? cmpn1 register: compare value ? tmcycn register: rmcn = 1 ... re mote control output enable bit nrzbn = 0/1 ... carrier output enable bit ? tcl5n, tmc5n registers: refer to 9.3 registers . remark n = 0, 1 <2> when the tmhen bit is set to 1, 8-bit timer hn count operation starts. <3> when the tmc5n.tce5n bit is set to 1, 8-bi t timer/event counter 5n count operation starts. <4> after the count operation is enabled, the first compar e register to be compared is the cmpn0 register. when the count value of 8-bit timer counter hn and the set value of the cmpn0 register match, the inttmhn signal is generated, 8-bit timer counter hn is cleared, and at the same time, the register that is compared with 8-bit timer counter hn changes from the cmpn0 register to the cmpn1 register. <5> when the count value of 8-bit timer counter hn an d the set value of the cmpn1 register match, the inttmhn signal is generated, 8-bit timer counter hn is cleared, and at the same time, the register that is compared with 8-bit timer counter hn changes from the cmpn1 register to the cmpn0 register. <6> the carrier clock is obtained through t he repetition of steps <4> and <5> above. <7> the inttm5n signal is synchronized with 8-bit timer hn and output as the inttm5hn signal. this signal becomes the data transfer signal of the nrzbn bit and the value of the nrzbn bit is transferred to the nrzn bit. <8> write the next value to the nrzbn bit in the interru pt servicing programming th at has been started by the inttm5hn interrupt or after timing has been checked by polling the interrupt request flag. write data to count the next time to the cr5n register. <9> when the nrzn bit becomes high level, the carri er clock is output from the tohn pin. <10> any carrier clock can be obtained through the repetiti on of the above steps. to stop the count operation, clear the tmhen bit to 0. chapter 10 8-bit timer h preliminary user?s manual u17702ej1v0ud 423 designating the set value of the cmpn0 register as (n ), the set value of the cm pn1 register as (m), and the count clock frequency as f cnt , the carrier clock output cycle and duty are as follows. carrier clock output cycle = (n + m + 2)/f cnt duty = high level width: carrier clock output width = (m + 1) : (n + m + 2) cautions 1. be sure to set the cmpn1 register when starting the timer count operation (tmhen bit = 1) after the timer count operation was stopped (tmh en bit = 0) (be sure to set again even if setting the same value to the cmpn1 register). 2. set the values of the cmpn0 and cmpn1 registers in the range of 01h to ffh. 3. in the carrier generator mode, thr ee operating clocks (signal selected by the tmhmdn.ckshn0 to tmhmdn.cks hn2 bits) are required for actual transfer of the new value to the register after the cmpn 1 register has been rewritten. 4. be sure to perform the tmcycn.rmcn bit se tting before the start of the count operation. 5. when using the carrier generator mode, set the 8-bit timer hn count clock frequency to six times the 8-bit timer/even t counter 5n count clo ck frequency or higher. chapter 10 8-bit timer h preliminary user?s manual u17702ej1v0ud 424 figure 10-8. carrier ge nerator mode (1/3) operation when the cmpn0 register = n, the cmpn1 register = n is set cmpn0 cmpn1 tmhen inttmhn carrier clock 00h n 00h n 00h n 00h n 00h n 00h n n n 8-bit timer 5n count clock tm5n count value tce5n tohn 0 0 1 1 0 0 1 1 0 0 inttm5n nrzbn nrzn carrier clock 00h 01h k 00h 01h l 00h 01h m 00h 01h 00h 01h n inttm5hn <1> <2> <3> <4> <5> <6> klm n <6> <7> 8-bit timer hn count clock 8-bit timer counter hn count value cr5n <1> when the tmhen bit = 0 and the tce5n bit = 0, the operation of 8-bit timer hn is stopped. <2> when the tmhen bit is set to 1, 8-bit timer hn starts counting. the carrier clock remains the default level. <3> when the count value of 8-bit timer counter hn and th e set value of the cmpn0 r egister match, the first inttmhn signal is generated, the carrier clock signal is inverted, and the register t hat is compared with 8-bit timer counter hn changes from the cm pn0 register to the cmpn1 register. 8-bit timer counter hn is cleared to 00h. <4> when the count value of 8-bit timer counter hn and t he set value of the cmpn1 register match, the inttmhn signal is generated, the carrier clock signal is invert ed, and the register that is compared with 8-bit timer counter hn changes from the cmpn1 register to the cmpn0 register. 8-bit timer counter hn is cleared to 00h. a carrier clock with a duty of 50% is generated through the repetition of steps <3> and <4>. <5> the inttm5n signal is synchronized with 8-bit timer hn and output as the inttm5hn signal. <6> the inttm5hn signal becomes the data transfer signal of the nrzbn bit, and the va lue of the nrzbn bit is transferred to the nrzn bit. <7> the tohn output is made low leve l by clearing the nrzn bit = 0. remark n = 0, 1 chapter 10 8-bit timer h preliminary user?s manual u17702ej1v0ud 425 figure 10-8. carrier ge nerator mode (2/3) operation when the cmpn0 register = n, the cmpn1 register = m is set n cmpn0 cmpn1 tmhen inttmhn carrier clock tm5n count value 00h n 00h 01h m 00h n 00h 01h m 00h 00h n m tce5n tohn 0 0 1 1 0 0 1 1 0 0 inttm5n nrzbn nrzn carrier clock 00h 01h k 00h 01h l 00h 01h m 00h 01h 00h 01h n inttm5hn klmn nrzbn <1> <2> <3> <4> <5> <6> <7> 8-bit timer 5n count clock 8-bit timer hn count clock 8-bit timer counter hn count value <1> when the tmhen bit = 0 and the tce5n bit = 0, the operation of 8-bit timer hn is stopped. <2> when the tmhen bit is set to 1, 8-bit timer hn starts counting. the carrier clock remains the default level at this time. <3> when the count value of 8-bit timer counter hn and th e set value of the cmpn0 r egister match, the first inttmhn signal is generated, the carrier clock signal is inverted, and the register t hat is compared with 8-bit timer counter hn changes from the cm pn0 register to the cmpn1 register. 8-bit timer counter hn is cleared to 00h. <4> when the count value of 8-bit timer counter hn and t he set value of the cmpn1 register match, the inttmhn signal is generated, the carrier clock signal is invert ed, and the register that is compared with 8-bit timer counter hn changes from the cmpn1 register to the cmpn0 register. 8-bit timer counter hn is cleared to 00h. a carrier clock with a fixed duty (other than 50%) is generated through the repetiti on of steps <3> and <4>. <5> the inttm5n signal is generated. this signal is synchronized with 8-bit timer hn and output as the inttm5hn signal. <6> the carrier is output from the rising edge of t he first carrier clock by setting the nrzn bit = 1. <7> by setting the nrzn bit = 0, the tohn output is also main tained high level while the carrier clock is high level, and does not change to low level (the high level width of the carrier waveform is guaranteed through steps <6> and <7>). remark n = 0, 1 chapter 10 8-bit timer h preliminary user?s manual u17702ej1v0ud 426 figure 10-8. carrier ge nerator mode (3/3) operation based on the cmp n1 register transitions 8-bit timer hn count clock cmpn0 tmhen inttmhn carrier clock 00h 01h n 00h 01h 01h m 00h n 00h l 00h <1> <3>' <4> <3> <2> cmpn1 <5> m n l m (l) 8-bit timer counter hn count value <1> when the tmhen bit is set to 1, counting starts. the carrier clock remains the default level at this time. <2> when the count value of the 8-bit timer counter hn matches the value of the cmpn0 register, the inttmhn signal is output, the carrier signal is inverted, and the 8-bi t timer counter is cleared to 00h. at the same time, the compare register whose value is to be compared with that of the 8-bit timer counter hn is changed from the cmpn0 register to the cmpn1 register. <3> the cmpn1 register is asynchronous to the count clock, and its value c an be changed while the 8-bit timer hn is operating. the new value (l) to which the value of t he register is to be changed is latched. when the count value of the 8-bit timer counter hn matches the val ue (m) of the cmpn1 register before the change, the cmpn1 register is changed (<3>?). however, it takes three count clo cks or more since the value of the cmpn1 register has been changed until the value is transferred to the register. even if a matc h signal is generated before the duration of three count clocks elapses, the new value is not transferred to the register. <4> when the count value of 8-bit timer counter hn and the value (m) of the cmpn1 re gister match, the inttmhn signal is output, the carrier signal is inverted, and 8-bit ti mer counter hn is cleared to 00h. at the same time, the compare register whose value is to be compared with that of the 8-bit timer counter hn is changed from the cmpn1 register to the cmpn0 register. <5> the timing at which the count value of 8-bit timer counter hn and the value of the cmpn1 register match again is the changed value (l). remark n = 0, 1 preliminary user?s manual u17702ej1v0ud 427 chapter 11 interval timer, watch timer the v850es/kj2 includes interval timer brg and a watch timer. interval timer brg can also be used as the source clock of the watch timer. the watch timer can also be used as interval timer wt. two interval timer channels and one watch timer channel can be used at the same time. 11.1 interval timer brg 11.1.1 functions interval timer brg has the following functions. ? interval timer brg: an interrupt request si gnal (intbrg) is generated at a specified interval. ? generation of count clock for watch timer: when the main clock is used as the count clock for the watch timer, a count clock (f brg ) is generated. 11.1.2 configuration the following shows the block diagram of interval timer brg. figure 11-1. block diagra m of interval timer brg f x f x /8 f x /4 f x /2 f x bgcs0 bgcs1 todis bgce 3-bit prescaler 8-bit counter clear match f bgcs count clock for watch timer intbrg 1/2 prsm register prscm register 2 internal bus f brg clock control output control selector remark f x : main clock oscillation frequency f bgcs : interval timer brg count clock frequency f brg : watch timer count clock frequency intbrg: interval timer brg interrupt request signal chapter 11 interval timer, watch timer preliminary user?s manual u17702ej1v0ud 428 (1) clock control the clock control controls supply/stop of the operation clock of interval timer brg. (2) 3-bit prescaler the 3-bit prescaler divides f x to generate f x /2, f x /4, and f x /8. (3) selector the selector selects the count clock (f bgcs ) for interval timer brg from f x , f x /2, f x /4, and f x /8. (4) 8-bit counter the 8-bit counter counts the count clock (f bgcs ). (5) output control the output control controls supply of the count clock (f brg ) for the watch timer. (6) prscm register the prscm register is an 8-bit compare re gister that sets the interval time. (7) prsm register the prsm register controls the oper ation of interval timer brg, the selector, and clock supply to the watch timer. chapter 11 interval timer, watch timer preliminary user?s manual u17702ej1v0ud 429 11.1.3 registers interval timer brg includes the following registers. (1) interval timer brg mode register (prsm) prsm controls the operation of interval timer brg, se lection of count clock, and clock supply to the watch timer. this register can be read or written in 8-bit or 1-bit units. after reset, prsm is cleared to 00h. 0 prsm 0 0 bgce 0 todis bgcs1 bgcs0 operation stopped, 8-bit counter cleared to 01h operate bgce 0 1 control of interval timer operation f x f x /2 f x /4 f x /8 5 mhz 200 ns 400 ns 800 ns 1.6 s 4 mhz 250 ns 500 ns 1 s 2 s bgcs1 0 0 1 1 bgcs0 0 1 0 1 selection of input clock (f bgcs ) note after reset: 00h r/w address: fffff8b0h clock for watch timer supplied clock for watch timer not supplied todis 0 1 control of clock supply for watch timer 10 mhz 100 ns 200 ns 400 ns 800 ns < > note set these bits so that the fo llowing conditions are satisfied. v dd = 4.0 to 5.5 v: f bgcs 10 mhz v dd = 2.7 to 4.0 v: f bgcs 5 mhz cautions 1. do not change the values of the todi s, bgcs1, and bgcs0 bits while interval timer brg is operating (bgce bit = 1). set the todis, bgcs1, and bgcs0 bits before setting (1) the bgce bit. 2. when the bgce bit is clea red (to 0), the 8-bit counter is cleared. chapter 11 interval timer, watch timer preliminary user?s manual u17702ej1v0ud 430 (2) interval timer brg compare register (prscm) prscm is an 8-bit compare register. this register can be read or written in 8-bit units. after reset, prscm is cleared to 00h. prscm7 prscm prscm6 prscm5 prscm4 prscm3 prscm2 prscm1 prscm0 after reset: 00h r/w address: fffff8b1h caution do not rewrite the prscm regi ster while interval timer brg is operating (prsm.bgce bit = 1). set the prscm register before setting (1) the bgce bit. chapter 11 interval timer, watch timer preliminary user?s manual u17702ej1v0ud 431 11.1.4 operation (1) operation of interval timer brg set the count clock by using the bg cs1 and bgcs0 bits of prsm and the 8-bit compare value by using the prscm register. when the prsm.bgce bit is set (1), interval timer brg starts operating. each time the count value of the 8-bit counter and the set value in the prscm register match, an interrupt request signal (intbrg) is generated. at the same time, the 8-bit counter is cleared to 00h and counting is continued. the interval time can be obtained from the following equation. interval time = 2 m n/f x remark m: division value (set values of bgcs1 and bgcs0 bits) = 0 to 3 n: set value in prscm register = 1 to 256 (when the set value in the prscm register is 00h, n = 256) f x : main clock oscillation frequency (2) count clock supply for watch timer set the count clock by using the bg cs1 and bgcs0 bits of prsm and the 8-bit compare value by using the prscm register, so that the count clock frequency (f brg ) of the watch timer is 32.768 khz. clear (0) the prsm.todis bit at the same time. when the prsm.bgce bit is set (1), f brg is supplied to the watch timer. f brg is obtained from the following equation. f brg = f x /(2 m+ 1 n) to set f brg to 32.768 khz, perform the following calculat ion to set the bgcs1 and bgcs0 bits and the prscm register. <1> set n = f x /65,536 (round off the decimal) to set m = 0. <2> if n is even, n = n/2 and m = m + 1 <3> repeat step <2> until n is even or m = 3 <4> set n to the prscm register and m to the bgcs1 and bgcs0 bits. example: when f x = 4.00 mhz <1> n = 4,000,000/65,536 = 61 (r ound off the decimal), m = 0 <2>, <3> since n is odd, the values remain as n = 61, m = 0 <4> the set value in the prscm register: 3 dh (61), the set values in the bgcs1 and bgcs0 bits: 00 remark m: divided value (set value in the bgcs1 and bgcs0 bits) = 0 to 3 n: set value in prscm register = 1 to 256 (when the set value in the prscm register is 00h, n = 256) f x : main clock oscillation frequency chapter 11 interval timer, watch timer preliminary user?s manual u17702ej1v0ud 432 11.2 watch timer 11.2.1 functions the watch timer has the following functions. ? watch timer: an interrupt request signal (intwt) is generated at time intervals of 0.5 or 0.25 seconds by using the main clock or subclock. ? interval timer: an interrupt request signal (i ntwti) is generated at the preset time interval. the watch timer and interval timer functions can be used at the same time. 11.2.2 configuration the following shows the block di agram of the watch timer. figure 11-2. block diagram of watch timer internal bus watch timer operation mode register (wtm) f brg f w /2 4 f w /2 5 f w /2 6 f w /2 7 f w /2 8 f w /2 10 f w /2 11 f w /2 9 f xt 11-bit prescaler clear clear intwt intwti wtm0 wtm1 wtm2 wtm3 wtm4 wtm5 wtm6 wtm7 5-bit counter f w 3 selector selector selector selector remark f brg : frequency of count clock from interval timer brg f xt : subclock frequency f w : watch timer clock frequency intwt: watch timer interrupt request signal intwti: interval timer interrupt request signal chapter 11 interval timer, watch timer preliminary user?s manual u17702ej1v0ud 433 (1) 11-bit prescaler the 11-bit prescaler generates a clock of f w /2 4 to f w /2 11 by dividing f w . (2) 5-bit counter the 5-bit counter generates the watch timer interru pt request signal (intwt) at intervals of 2 4 /f w , 2 5 /f w , 2 13 /f w , or 2 14 /f w by counting f w or f w /2 9 . (3) selectors the watch timer has the following four selectors. ? selector that selects the main clo ck (the clock from interval timer brg (f brg )) or the subclock (f xt ) as the clock for the watch timer. ? selector that selects f w or f w /2 9 as the count clock frequency of the 5-bit counter ? selector that selects 2 4 /f w or 2 13 /f w , or 2 5 /f w or 2 14 /f w as the intwt signal generation time interval. ? selector that selects the generation time interval of the interval timer wt inte rrupt request signal (intwti) from 2 4 /f w to 2 11 /f w . (4) 8-bit counter the 8-bit counter counts the count clock (f bgcs ). (5) wtm register the wtm register is an 8-bit register that controls the operation of the watch timer/interval timer wt and sets the interval of interrupt request signal generation. 11.2.3 registers the watch timer includes the following register. (1) watch timer operation mode register (wtm) this register enables or disables the count clock and operation of the watch ti mer, sets the interval time of the 11-bit prescaler, controls the operation of the 5-bit counter, and sets the timer of watch timer interrupt request signal (intwt) generation. the wtm register can be read or written in 8-bit or 1-bit units. after reset, wtm is cleared to 00h. chapter 11 interval timer, watch timer preliminary user?s manual u17702ej1v0ud 434 wtm7 2 4 /f w (488 s: f w = f xt ) 2 5 /f w (977 s: f w = f xt ) 2 6 /f w (1.95 ms: f w = f xt ) 2 7 /f w (3.91 ms: f w = f xt ) 2 8 /f w (7.81 ms: f w = f xt ) 2 9 /f w (15.6 ms: f w = f xt ) 2 10 /f w (31.3 ms: f w = f xt ) 2 11 /f w (62.5 ms: f w = f xt ) 2 4 /f w (488 s: f w = f brg ) 2 5 /f w (977 s: f w = f brg ) 2 6 /f w (1.95 ms: f w = f brg ) 2 7 /f w (3.91 ms: f w = f brg ) 2 8 /f w (7.81 ms: f w = f brg ) 2 9 /f w (15.6 ms: f w = f brg ) 2 10 /f w (31.3 ms: f w = f brg ) 2 11 /f w (62.5 ms: f w = f brg ) wtm7 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 wtm6 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 selection of interval timer interrupt (intwti) time wtm wtm6 wtm5 wtm4 wtm3 wtm2 wtm1 wtm0 wtm5 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 wtm4 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 after reset: 00h r/w address: fffff680h < > < > 2 14 /f w (0.5 s: f w = f xt ) 2 13 /f w (0.25 s: f w = f xt ) 2 5 /f w (977 s: f w = f xt ) 2 4 /f w (488 s: f w = f xt ) 2 14 /f w (0.5 s: f w = f brg ) 2 13 /f w (0.25 s: f w = f brg ) 2 5 /f w (977 s: f w = f brg ) 2 4 /f w (488 s: f w = f brg ) wtm7 0 0 0 0 1 1 1 1 selection of watch timer interrupt (intwt) time clear after operation stops start wtm1 0 1 control of 5-bit counter operation wtm3 0 0 1 1 0 0 1 1 wtm2 0 1 0 1 0 1 0 1 stop operation (clear both prescaler and 5-bit counter) enable operation wtm0 0 1 watch timer operation enable caution rewrite the wtm2 to wtm7 bits wh ile both the wtm0 and wtm1 bits are 0. remarks 1. f w : watch timer clock frequency 2. values in parentheses apply when f w = 32.768 khz chapter 11 interval timer, watch timer preliminary user?s manual u17702ej1v0ud 435 11.2.4 operation (1) operation as watch timer the watch timer generates an interrupt request at fixed time intervals. the watch timer operates using time intervals of 0.25 or 0.5 second s with the subclock (32.768 khz). the count operation starts when the wtm.wtm0 and wtm. wtm1 bits are set to 11. when these bits are cleared to 00, the 10-bit prescaler and 5-bit count er are cleared and the count operation stops. the 5-bit counter can be cleared to synchronize the time by clearing the wtm1 bit to 0 when the watch timer and interval timer wt operate simultaneously. at this ti me, an error of up to 15.6 ms may occur in the watch timer, but interval timer wt is not affected. (2) operation as interval timer the watch timer can also be used as an interval timer that repeatedly generates an interrupt request signal (intwti) at intervals specified by a count value set in advance. the interval time can be selected by the wtm.wtm4 to wtm.wtm7 bits. table 11-1. interval ti me of interval timer wtm7 wtm6 wtm5 wtm4 interval time 0 0 0 0 2 4 1/f w 488 s (operating at f w = f xt = 32.768 khz) 0 0 0 1 2 5 1/f w 977 s (operating at f w = f xt = 32.768 khz) 0 0 1 0 2 6 1/f w 1.95 ms (operating at f w = f xt = 32.768 khz) 0 0 1 1 2 7 1/f w 3.91 ms (operating at f w = f xt = 32.768 khz) 0 1 0 0 2 8 1/f w 7.81 ms (operating at f w = f xt = 32.768 khz) 0 1 0 1 2 9 1/f w 15.6 ms (operating at f w = f xt = 32.768 khz) 0 1 1 0 2 10 1/f w 31.3 ms (operating at f w = f xt = 32.768 khz) 0 1 1 1 2 11 1/f w 62.5 ms (operating at f w = f xt = 32.768 khz) 1 0 0 0 2 4 1/f w 488 s (operating at f w = f brg = 32.768 khz) 1 0 0 1 2 5 1/f w 977 s (operating at f w = f brg = 32.768 khz) 1 0 1 0 2 6 1/f w 1.95 ms (operating at f w = f brg = 32.768 khz) 1 0 1 1 2 7 1/f w 3.91 ms (operating at f w = f brg = 32.768 khz) 1 1 0 0 2 8 1/f w 7.81 ms (operating at f w = f brg = 32.768 khz) 1 1 0 1 2 9 1/f w 15.6 ms (operating at f w = f brg = 32.768 khz) 1 1 1 0 2 10 1/f w 31.3 ms (operating at f w = f brg = 32.768 khz) 1 1 1 1 2 11 1/f w 62.5 ms (operating at f w = f brg = 32.768 khz) remark f w : watch timer clock frequency chapter 11 interval timer, watch timer preliminary user?s manual u17702ej1v0ud 436 figure 11-3. operation timing of watch timer/interval timer start overflow overflow 0h interrupt time of watch timer (0.5 s) interrupt time of watch timer (0.5 s) interval time (t) interval time (t) nt nt 5-bit counter count clock f w or f w /2 9 watch timer interrupt intwt interval timer interrupt intwti remarks 1. assuming that the interrupt time of the watch timer is set to 0.5 seconds. 2. f w : watch timer clock frequency values in parentheses apply when count clock f w = 32.768 khz. n: number of interval timer wt operations 11.3 cautions (1) operation as watch timer some time is required before the first watch timer in terrupt request (intwt) is generated after operation is enabled (wtm.wtm1 and wtm.wtm0 bits = 11). figure 11-4. example of generation of watch timer interrupt request (intwt) (when interrupt period = 0.5 s) it takes 0.515625 (max.) seconds for the first intwt to be generated (2 9 1/32768 = 0.015625 (max.) s longer). intwt is then generated every 0.5 seconds. 0.5 s 0.5 s 0.515625 s wtm0, wtm1 intwt chapter 11 interval timer, watch timer preliminary user?s manual u17702ej1v0ud 437 (2) when watch timer and interval timer brg operate simultaneously when using the subclock as the count clock for the watch ti mer, the interval time of interval timer brg can be set to any value. changing the interval time does not a ffect the watch timer (before changing the interval time, stop operation). when using the main clock as the count clock for the watch timer, set the interval time of interval timer brg to approximately 65.536 khz. do not change this value. (3) when interval timer brg and inter val timer wt operate simultaneously when using the subclock as the count clock for interval ti mer wt, the interval times of interval timers brg and wt can be set to any values. they can also be cha nged later (before changing the value, stop operation). when using the main clock as the count clock for interval timer wt, the interval time of interval timer brg can be set to any value, but cannot be changed later (it can be changed only when interval timer wt stops operation). the interval time of interval timer wt can be set to 2 5 to 2 12 of the set value of interval timer brg. it can also be changed later. (4) when watch timer and interval timer wt operate simultaneously the interval time of interval timer wt can be set to a value between 488 s and 62.5 ms. it cannot be changed later. do not stop interval timer wt (clear (0) the wtm.wtm0 bit) while the watch timer is operating. if the wtm0 bit is set (1) after it had been cleared (0), the watch timer will have a discrepancy of up to 0.5 or 0.25 seconds. (5) when watch timer, interval timer brg, and interval time r wt operate simultaneously when using the subclock as the count clock for the watch timer, the interval times of interval timers brg and wt can be set to any values. the interval time of interval timer brg can be changed later (before changing the value, stop operation). when using the main clock as the count clock for the watch timer, set the interval time of interval timer brg to approximately 65.536 khz. it cannot be c hanged later. the interval time of interval timer wt can be set to a value between 488 s and 62.5 ms. it cannot be changed later. do not stop interval timer brg (clear (0) the prsm.bgce bit) or interval timer wt (clear (0) the wtm.wtm0 bit) while the watch timer is operating. preliminary user?s manual u17702ej1v0ud 438 chapter 12 watchdog timer functions 12.1 watchdog timer 1 12.1.1 functions watchdog timer 1 has the following operation modes. ? watchdog timer ? interval timer the following functions are realized fr om the above-listed operation modes. ? generation of non-maskable interrupt request si gnal (intwdt1) upon overflow of watchdog timer 1 note ? generation of system reset signal (wdtres1 ) upon overflow of watchdog timer 1 ? generation of maskable interrupt request signal (intwdtm1) upon overflow of interval timer note for non-maskable interrupt servicing due to non-mask able interrupt request signal (intwdt1, intwdt2), refer to 21.10 cautions . remark select whether to use watchdog timer 1 in the watchdog timer 1 mode or the interval timer mode with the wdtm1 register. chapter 12 watchdog timer functions preliminary user?s manual u17702ej1v0ud 439 figure 12-1. block diagra m of watchdog timer 1 wdtm14 wdtm13 run1 2 intwdtm1 wdtres1 3 wdcs1 wdcs0 wdcs2 f xw /2 21 f xw /2 15 f xw /2 16 f xw /2 17 f xw /2 18 f xw /2 19 f xw /2 14 f xw /2 13 intwdt1 f xw internal bus watchdog timer mode register 1 (wdtm1) watchdog timer clock selection register (wdcs) output controller prescaler clear selector remark intwdtm1: request signal for maskable interrupt through watchdog timer 1 overflow intwdt1: request signal for non-maskable inte rrupt through watchdog timer 1 overflow wdtres1: reset signal through watchdog timer 1 overflow f xw = f x : watchdog timer 1 clock frequency chapter 12 watchdog timer functions preliminary user?s manual u17702ej1v0ud 440 12.1.2 configuration watchdog timer 1 consists of the following hardware. table 12-1. configuration of watchdog timer 1 item configuration control register watchdog timer clock select ion register (wdcs) watchdog timer mode register 1 (wdtm1) 12.1.3 registers the registers that control watchdo g timer 1 are as follows. ? watchdog timer clock selection register (wdcs) ? watchdog timer mode register 1 (wdtm1) (1) watchdog timer clock selection register (wdcs) this register sets the overflow time of watchdog timer 1 and the interval timer. the wdcs register can be read or wri tten in 8-bit or 1-bit units. after reset, wdcs is cleared to 00h. 0 wdcs 0 0 0 0 wdcs2 wdcs1 wdcs0 2 13 /f xw 2 14 /f xw 2 15 /f xw 2 16 /f xw 2 17 /f xw 2 18 /f xw 2 19 /f xw 2 21 /f xw wdcs2 0 0 0 0 1 1 1 1 overflow time of watchdog timer 1/interval timer wdcs1 0 0 1 1 0 0 1 1 wdcs0 0 1 0 1 0 1 0 1 4 mhz 10 mhz 5 mhz 2.048 ms 4.096 ms 8.192 ms 16.38 ms 32.77 ms 65.54 ms 131.1 ms 524.3 ms 1.638 ms 3.277 ms 6.554 ms 13.11 ms 26.21 ms 52.43 ms 104.9 ms 419.4 ms 0.819 ms 1.638 ms 3.277 ms 6.554 ms 13.11 ms 26.2 ms 52.43 ms 209.7 ms f xw after reset: 00h r/w address: fffff6c1h remark f xw = f x : watchdog timer 1 clock frequency chapter 12 watchdog timer functions preliminary user?s manual u17702ej1v0ud 441 (2) watchdog timer mode register 1 (wdtm1) this register sets the watchdog timer 1 operati on mode and enables/disables count operations. this register is a special register that c an be written only in a special sequence (refer to 3.4.7 special registers ). the wdtm1 register can be read or written in 8-bit or 1-bit units. after reset, wdtm1 is cleared to 00h. caution when the main clock is stopped and the cpu is operating on the subclock, do not access the wdtm1 register. for details, refer to 3.4.8 (1) (b). run1 stop counting clear counter and start counting run1 0 1 selection of operation mode of watchdog timer 1 note 1 wdtm1 0 0 wdtm14 wdtm13 0 0 0 after reset: 00h r/w address: fffff6c2h interval timer mode (upon overflow, maskable interrupt intwdtm1 is generated.) watchdog timer mode 1 note 3 (upon overflow, non-maskable interrupt intwdt1 is generated.) watchdog timer mode 2 (upon overflow, reset operation wdtres1 is started.) wdtm14 0 0 1 1 wdtm13 0 1 0 1 selection of operation mode of watchdog timer 1 note 2 < > notes 1. once the run1 bit is set (to 1), it c annot be cleared (to 0) by software. therefore, when counting is start ed, it cannot be stopped except reset. 2. once the wdtm13 and wdtm14 bits are set (to 1), they cannot be cleared (to 0) by software and can be cleared only by reset. 3. for non-maskable interrupt servicing due to non -maskable interrupt request signal (intwdt1), refer to 21.10 cautions . chapter 12 watchdog timer functions preliminary user?s manual u17702ej1v0ud 442 12.1.4 operation (1) operation as watchdog timer 1 watchdog timer 1 operation to detect a program loop is selected by setting the wdtm1.wdtm14 bit to 1. the count clock (program loop detection time interv al) of watchdog timer 1 can be selected using the wdcs.wdcs0 to wdcs.wdcs2 bits. the count operation is started by setting the wdtm1.run1 bit to 1. when, after the count operation is st arted, the run1 bit is again set to 1 within the set program loop detection time interval, watchdog timer 1 is cleared and the count operation starts again. if the program loop detection time is exceeded without run1 bit being set to 1, reset signal (wdtres1) through the value of the wdtm1.wdtm13 bit or a non-maskable interrupt request signal (intwdt1) is generated. the count operation of watchdog timer 1 stops in t he stop mode and idle mode. set the run1 bit to 1 before the stop mode or idle mode is entered in order to clear watchdog timer 1. because watchdog timer 1 operates in the halt mode, make sure that an overflow will not occur during halt. cautions 1. when the subclock is selected for the cpu cl ock, the count operation of watchdog timer 1 is stopped (the value of watc hdog timer 1 is maintained). 2. for non-maskable interrupt servicing due to the intwdt1 signal, refer to 21.10 cautions. table 12-2. program loop detect ion time of watchdog timer 1 program loop detection time clock f xw = 4 mhz f xw = 5 mhz f xw = 10 mhz 2 13 /f xw 2.048 ms 1.638 ms 0.819 ms 2 14 /f xw 4.096 ms 3.277 ms 1.683 ms 2 15 /f xw 8.192 ms 6.554 ms 3.277 ms 2 16 /f xw 16.38 ms 13.11 ms 6.554 ms 2 17 /f xw 32.77 ms 26.21 ms 13.11 ms 2 18 /f xw 65.54 ms 52.43 ms 26.21 ms 2 19 /f xw 131.1 ms 104.9 ms 52.43 ms 2 21 /f xw 524.3 ms 419.4 ms 209.7 ms remark f xw = f x : watchdog timer 1 clock frequency chapter 12 watchdog timer functions preliminary user?s manual u17702ej1v0ud 443 (2) operation as interval timer watchdog timer 1 can be made to operate as an interval ti mer that repeatedly generates interrupts using the count value set in advance as the interval, by clearing the wdtm1.wdtm14 bit to 0. when watchdog timer 1 operates as an interval time r, the interrupt mask flag (wdtmk) and priority specification flags (wdtpr0 to wdtpr2) of the wdti c register are valid and maskable interrupt request signals (intwdtm1) can be generated. the default priority of the intwdtm1 signal is set to the highest level among the maskable interrupt request signals. the interval timer continues to operate in the halt mode, but it stops operating in the stop mode and the idle mode. cautions 1. once the wdtm14 bit is set to 1 (thereby selecting the watc hdog timer 1 mode), the interval timer mode is not entered as long as reset is not performed. 2. when the subclock is sel ected for the cpu clock, the count operation of the watchdog timer 1 stops (the value of the wa tchdog timer is maintained). table 12-3. interval ti me of interval timer interval time clock f xw = 4 mhz f xw = 5 mhz f xw = 10 mhz 2 13 /f xw 2.048 ms 1.638 ms 0.819 ms 2 14 /f xw 4.096 ms 3.277 ms 1.638 ms 2 15 /f xw 8.192 ms 6.554 ms 3.277 ms 2 16 /f xw 16.38 ms 13.11 ms 6.554 ms 2 17 /f xw 32.77 ms 26.21 ms 13.11 ms 2 18 /f xw 65.54 ms 52.43 ms 26.21 ms 2 19 /f xw 131.1 ms 104.9 ms 52.43 ms 2 21 /f xw 524.3 ms 419.4 ms 209.7 ms remark f xw = f x : watchdog timer 1 clock frequency chapter 12 watchdog timer functions preliminary user?s manual u17702ej1v0ud 444 12.2 watchdog timer 2 12.2.1 functions watchdog timer 2 has the following functions. ? default start watchdog timer note 1 reset mode: reset operation upon overflow of watchdog timer 2 (generation of wdtres2 signal) non-maskable interrupt request mode: nmi operation upon overflow of watchdog timer 2 (generation of intwdt2 signal) note 2 ? input selectable from main clock and subclock as the source clock notes 1. watchdog timer 2 automatically starts in t he reset mode following reset release. when watchdog timer 2 is not used, either stop its operation before reset is executed through this function, or clear once watchdog timer 2 and stop it within the next interval time. also, write to the wdtm2 register for verifi cation purposes only once, even if the default settings (reset mode, interval time: f xx /2 25 ) need not be changed. 2. for non-maskable interrupt servicing due to a non -maskable interrupt request signal (intwdt2), refer to 21.10 cautions . figure 12-2. block diagra m of watchdog timer 2 f xx /2 9 clock input controller output controller wdtres2 (internal reset signal) wdcs22 internal bus intwdt2 wdcs21 wdcs20 f xt wdcs23 wdcs24 0 wdm21 wdm20 selector 16-bit counter f xx /2 18 to f xx /2 25 or f xt /2 9 to f xt /2 16 watchdog timer enable register (wdte) watchdog timer mode register 2 (wdtm2) 3 3 2 clear remark f xx : main clock frequency f xt : subclock frequency intwdt2: non-maskable interrupt request signal through watchdog timer 2 wdtres2: watchdog timer 2 reset signal chapter 12 watchdog timer functions preliminary user?s manual u17702ej1v0ud 445 12.2.2 configuration watchdog timer 2 consists of the following hardware. table 12-4. configuration of watchdog timer 2 item configuration control register watchdog timer mode register 2 (wdtm2) watchdog timer enable register (wdte) 12.2.3 registers (1) watchdog timer mode register 2 (wdtm2) this register sets the overflow time and operation clock of watchdog timer 2. the wdtm2 register can be read or writt en in 8-bit units. this register c an be read any number of times, but it can be written only once following reset release. after reset, wdtm2 is set to 67h. caution when the main clock is stopped and the cpu is operating on the subclock, do not access the wdtm2 register. for details, refer to 3.4.8 (1) (b). 0 wdtm2 wdm21 wdm20 wdcs24 wdcs23 wdcs22 wdcs21 wdcs20 after reset: 67h r/w address: fffff6d0h stops operation non-maskable interrupt request mode (generation of intwdt2) reset mode (generation of wdtres2) wdm21 0 0 1 wdm20 0 1 ? selection of operation mode of watchdog timer 2 cautions 1. to stop the operation of watchdog ti mer 2, write ?1fh? to the wdtm2 register. 2. for details about bits wdcs0 to wdcs4, refer to table 12-5 watchdog timer 2 clock selection. 3. if the wdtm2 register is written twice afte r a reset, an overflow signal is forcibly output. 4. to intentionally generate an overflow signa l, write data to the wdtm2 register only twice, or write a value other than ?ach? to the wdte register only once. chapter 12 watchdog timer functions preliminary user?s manual u17702ej1v0ud 446 table 12-5. watchdog timer 2 clock selection wdcs24 wdcs23 wdcs22 wdcs21 wdcs20 selected clock f xx = 20 mhz f xx = 16 mhz f xx = 10 mhz 0 0 0 0 0 2 18 /f xx 13.1 ms 16.4 ms 26.2 ms 0 0 0 0 1 2 19 /f xx 26.2 ms 32.8 ms 52.4 ms 0 0 0 1 0 2 20 /f xx 52.4 ms 65.5 ms 104.9 ms 0 0 0 1 1 2 21 /f xx 104.9 ms 131.1 ms 209.7 ms 0 0 1 0 0 2 22 /f xx 209.7 ms 262.1 ms 419.4 ms 0 0 1 0 1 2 23 /f xx 419.4 ms 524.3 ms 838.9 ms 0 0 1 1 0 2 24 /f xx 838.9 ms 1048.6 ms 1677.7 ms 0 0 1 1 1 2 25 /f xx 1677.7 ms 2097.2 ms 3355.4 ms 0 1 0 0 0 2 9 /f xt 15.625 ms (f xt = 32.768 khz) 0 1 0 0 1 2 10 /f xt 31.25 ms (f xt = 32.768 khz) 0 1 0 1 0 2 11 /f xt 62.5 ms (f xt = 32.768 khz) 0 1 0 1 1 2 12 /f xt 125 ms (f xt = 32.768 khz) 0 1 1 0 0 2 13 /f xt 250 ms (f xt = 32.768 khz) 0 1 1 0 1 2 14 /f xt 500 ms (f xt = 32.768 khz) 0 1 1 1 0 2 15 /f xt 1000 ms (f xt = 32.768 khz) 0 1 1 1 1 2 16 /f xt 2000 ms (f xt = 32.768 khz) 1 operation stopped (2) watchdog timer enable register (wdte) the counter of watchdog timer 2 is cl eared and counting restarted by writin g ?ach? to the wdte register. the wdte register can be read or written in 8-bit units. after reset, wdte is set to 9ah. wdte after reset: 9ah r/w address: fffff6d1h cautions 1. when a value other th an ?ach? is written to the wdte register, an overflow signal is forcibly output. 2. when a 1-bit memory manipulation instru ction is executed for the wdte register, an overflow signal is forcibly output. 3. the read value of the wdte register is a lways ?9ah? (value that differs from written value ?ach?). 4. to intentionally generate an overflow signal, write a value other than ?ach? to the wdte register only once, or write data to the wdtm2 register only twice. chapter 12 watchdog timer functions preliminary user?s manual u17702ej1v0ud 447 12.2.4 operation watchdog timer 2 automatically starts in t he reset mode following reset release. the wdtm2 register can be written to only once following reset through byte access. to use watchdog timer 2, write the operation mode and the interval time to the wdtm 2 register using 8-bit memory manipulation instructions. after this is done, the operation of watchdog timer 2 cannot be stopped. the watchdog timer 2 program loop detection time in terval can be selected by the wdtm2.wdcs24 to wdtm2.wdcs20 bits. writing ach to the wdte register clears the counter of watchdog timer 2 and starts the count operation again. after the count operat ion starts, write ach to the wdte r egister within the set program loop detection time interval. if the program loop detection time is exceeded without a ch being written to the wdte register, a reset signal (wdtres2) or non-maskable interrupt request signal (i ntwdt2) is generated depending on the set value of the wdtm2.wdm21 and wdtm2.wdm20 bits. to not use watchdog timer 2, writ e 1fh to the wdtm2 register. for non-maskable interrupt servicing when the non -maskable interrupt request mode is set, refer to 21.10 cautions . if the main clock is selected as the source clock of wa tchdog timer 2, the watchdog timer stops operation in the idle/stop mode. therefore, clear wa tchdog timer 2 by writing ach to the wdte register before the idle/stop mode is set. because watchdog timer 2 operates in the halt mode or w hen the subclock is selected as its source clock in the idle/stop mode, exercise care that the ti mer does not overflow in the halt mode. preliminary user?s manual u17702ej1v0ud 448 chapter 13 real-time output function (rto) 13.1 function the real-time output function (rto) transfers preset data to the rtbln and rtbhn registers, and then transfers this data with hardware to an external device via the r eal-time output latches, upon occurr ence of a timer interrupt. the pins through which the data is output to an external device constitute a port called a real-time output port. because rto can output signal without jitter, it is suitable for controlling a stepping motor. in the v850es/kj2, two 6-bit real-time output port channels are provided. the real-time output port can be se t in the port mode or real-time output port mode in 1-bit units. the block diagram of rto is shown below. figure 13-1. block diagram of rto real-time buffer register nh (rtbhn) real-time output latch nh selector inttm000 (inttm020 note ) inttm50 inttm51 real-time output latch nl rtpoen rtpegn byten extrn real-time output port control register n (rtpcn) transfer trigger (h) transfer trigger (l) rtpmn5 rtpmn4 rtpmn3 rtpmn2 rtpmn1 rtpmn0 real-time output port mode register n (rtpmn) 4 2 2 4 internal bus real-time buffer register nl (rtbln) rtpoutn4, rtpoutn5 rtpoutn0 to rtpoutn3 note when n = 0, inttm000 when n = 1, inttm020 chapter 13 real-time output function (rto) preliminary user?s manual u17702ej1v0ud 449 13.2 configuration rto consists of the following hardware. table 13-1. configuration of rto item configuration registers real-time output buffe r register n (rtbln, rtbhn) control registers real-time output port mode register n (rtpmn) real-time output port control register n (rtpcn) (1) real-time output buffer register n (rtbln, rtbhn) rtbln and rtbhn are 4-bit registers t hat hold output data in advance. these registers are mapped to independent addresses in the peripheral i/o register area. they can be read or written in 8-bit or 1-bit units. if an operation mode of 4 bits 1 channel or 2 bits 1 channel is specified (rtpcn.byten bit = 0), data can be individually set to the rtbln and rtbhn registers. the data of both these r egisters can be read at once by specifying the address of ei ther of these registers. if an operation mode of 6 bits 1 channel is specified (byten bit = 1), 8-bit data can be set to both the rtbln and rtbhn registers by writing the da ta to either of these registers. moreover, the data of both these registers can be read at once by specifying t he address of either of these registers. table 13-2 shows the operation when the rt bln and rtbhn register s are manipulated. 0 rtbln rtbhn 0 rtbhn5 rtbhn4 rtbln3 rtbln2 rtbln1 rtbln0 after reset: 00h r/w address: rtbl0 fffff6e0h, rtbl1 fffff6f0 rtbh0 fffff6e2h, rtbh1 fffff6f2 cautions 1. when writing to bits 6 and 7 of the rtbhn register, always write 0. 2. when the main clock is stopped and the cpu is operating on the subclock, do not access the rtbln and rtbhn registers. for details, refer to 3.4.8 (1) (b). remark n = 0, 1 chapter 13 real-time output function (rto) preliminary user?s manual u17702ej1v0ud 450 table 13-2. operation during manipulation of rtbln and rtbhn registers read write note operation mode register to be manipulated higher 4 bits lower 4 bits higher 4 bits lower 4 bits rtbln rtbhn rtbln invalid rtbln 4 bits 1 channel, 2 bits 1 channel rtbhn rtbhn rtbln rtbhn invalid rtbln rtbhn rtbln rtbhn rtbln 6 bits 1 channel rtbhn rtbhn rtbln rtbhn rtbln note after setting the real-time output port, set output data to the rtbln and rtbhn registers by the time a real- time output trigger is generated. 13.3 registers rto is controlled using the foll owing two types of registers. ? real-time output port mode register n (rtpmn) ? real-time output port control register n (rtpcn) (1) real-time output port mode register n (rtpmn) this register selects the real-time output port mode or port mode in 1-bit units. the rtpmn register can be read or written in 8-bit or 1-bit units. after reset, rtpmn is cleared to 00h. 0 rtpmnm 0 1 real-time output disabled real-time output enabled control of real-time output port (m = 0 to 5) rtpmn (n = 0, 1) 0 rtpmn5 rtpmn4 rtpmn3 rtpmn2 rtpmn1 rtpmn0 after reset: 00h r/w address: rtpm0 fffff6e4h, rtpm1 fffff6f4h cautions 1. to reflect real-time output signa ls (rtpoutn0 to rtpoutn5) to the pins (rtpn0 to rtpn5), set them to th e real-time output port with the pmc5, pmc6, pfc5, and pfc6 registers. 2. by enabling real-time output opera tion (rtpcn.rtpoen bit = 1), the bits specified as real-time outpu t enabled perform real-time output, and the bits specified as real-time out put disabled output 0. 3. if real-time output is disabled (r tpoen bit = 0), real-time output signals (rtpoutn0 to rtpoutn5) all output 0, regardless of the rtpmn register setting. chapter 13 real-time output function (rto) preliminary user?s manual u17702ej1v0ud 451 (2) real-time output port control register n (rtpcn) rtpcn are registers used to set the operation mode and output trigger of the real-time output port. the relationship between the operation mo de and output trigger of the real -time output port is as shown in tables 13-3 and 13-4. the rtpcn register can be read or written in 8-bit or 1-bit units. after reset, rtpcn is cleared to 00h. rtpoen disables operation note 2 enables operation rtpoen 0 1 control of real-time output operation rtpcn (n = 0, 1) rtpegn byten extrn note 1 00 0 0 falling edge note 3 rising edge rtpegn 0 1 valid edge of inttm000 (n = 0), inttm020 (n = 1) signal 4 bits 1 channel, 2 bits 1 channel 6 bits 1 channel byten 0 1 specification of channel configuration for real-time output after reset: 00h r/w address: rtpc0 fffff6e5h, rtpc1 fffff6f5h < > notes 1. for the extrn bit, refer to tables 13-3 and 13-4 . 2. when real-time output operation is dis abled (rtpoen bit = 0), real-time output signals (rtpoutn0 to rtpoutn5) all output 0. 3. the inttm000 and inttm020 signals are output for 1 clock of the count clock selected with the respective timers. caution perform the settings for the rtpegn, byten, and extrn bits only when the rtpoen bit = 0. table 13-3. operation modes and output triggers of real-time output port (n = 0) byte0 extr0 operation mode rtbh0 (rtp 04, rtp05) rtbl0 (rtp00 to rtp03) 0 inttm51 inttm50 0 1 4 bits 1 channel, 2 bits 1 channel inttm50 inttm000 0 inttm50 1 1 6 bits 1 channel inttm000 table 13-4. operation modes and output triggers of real-time output port (n = 1) byte1 extr1 operation mode rtbh1 (rtp 14, rtp15) rtbl1 (rtp10 to rtp13) 0 inttm50 inttm51 0 1 4 bits 1 channel, 2 bits 1 channel inttm51 inttm020 0 inttm51 1 1 6 bits 1 channel inttm020 chapter 13 real-time output function (rto) preliminary user?s manual u17702ej1v0ud 452 13.4 operation if the real-time output operation is enabled by setting the rtpcn.rtpoen bi t to 1, the data of the rtbhn and rtbln registers is transferred to the real-time output latch in synchronizati on with the generation of the selected transfer trigger (set by the rtpcn.extrn and rtpcn.byten bits). of the trans ferred data, only the data of the bits specified as real-time output enabled by the rtpmn register is output from bi ts rtpoutn0 to rtpo utn5. the bits specified as real-time output disabled by the rtpmn register output 0. if the real-time output operatio n is disabled by clearing the rtpoen bi t to 0, the rtpoutn0 to rtpoutn5 signals output 0 regardless of the setti ng of the rtpmn register. figure 13-2. example of operation timing of rto0 (when extr0 bit = 0, byte0 bit = 0) abababab d01 d02 d03 d04 d11 d12 d13 d14 d11 d12 d13 d14 d01 d02 d03 d04 inttm51 (internal) inttm50 (internal) cpu operation rtbh0 rtbl0 rt output latch 0 (h) rt output latch 0 (l) a: software processing by inttm51 interrupt request signal (write to rtbh0 register) b: software processing by inttm50 interrupt request signal (write to rtbl0 register) remark for the operation during standby, refer to chapter 23 standby function . chapter 13 real-time output function (rto) preliminary user?s manual u17702ej1v0ud 453 13.5 usage (1) disable real-time output. clear the rtpcn.rtpoen bit to 0. (2) perform initializa tion as follows. ? specify the real-time output port m ode or port mode in 1-bit units. set the rtpmn register. ? channel configuration: select the trigger and valid edge. set the rtpcn.extrn, rtpcn.byt en, and rtpcn.rtpegn bits. ? set the initial values to the rtbhn and rtbln registers note 1 . (3) enable real-time output. set the rtpoen bit to 1. (4) set the next output value to the rtbhn and rtbln registers by the time the selected transfer trigger is generated note 2 . (5) set the next real-time output value to the rtbhn and rtbln regi sters through interrupt servicing corresponding to the selected trigger. notes 1. if write to the rtbhn and rtbln registers is per formed when the rtpoen bit = 0, that value is transferred to real-time output latches nh and nl, respectively. 2. even if write is performed to t he rtbhn and rtbln registers when th e rtpoen bit = 1, data transfer to real-time output latches nh and nl is not performed. caution to reflect the real-time out put signals (rtpoutn0 to rtpoutn5 ) to the pins, set the real-time output ports (rtpn0 to rtpn5) with the pm c5, pmc6, pfc5, and pfc6 registers. 13.6 cautions (1) prevent the following conflicts by software. ? conflict between real-time output disable/enable s witching (rtpoen bit) and selected real-time output trigger ? conflict between write to the rtbhn and rtbln regist ers in the real-time output enabled status and the selected real-time output trigger. (2) before performing initialization, disable real-time output (rtpoen bit = 0). (3) once real-time output has been disabled (rtpoen bit = 0), be sure to initialize the rtbhn and rtbln registers before enabling real-time output again (rtpoen bit = 0 1). chapter 13 real-time output function (rto) preliminary user?s manual u17702ej1v0ud 454 13.7 security function a circuit that sets the pin outputs to high impedance as a security functi on for when malfunctions of a stepping motor controlled by rto occur is provided on chip. it fo rcibly resets the pins allocated to rtp00 to rtp05 via external interrupt intp0 pin edge detection, and the pins a llocated to rtp10 to rtp15 via intp1 pin edge detection, placing them in the high-impedance state. the ports (p50 to 55, p60 to 65 pins ) placed in high impedance by intp0 note 1 and intp1 note 1 pins are initialized note 2 , so settings for these ports must be performed again. notes 1. regardless of the port settings, p50 to 55 and p60 to 65 pins are all placed in high impedance via intpn. 2. the bits that are initialized are all the bits co rresponding to p50 to 55 and p60 to 65 pins of the following registers. ? p5, p6l registers ? pm5, pm6l registers ? pmc5, pmc6l registers ? pu5, pu6l registers ? pfc5 register ? pf5 register the block diagram of the security function is shown below. figure 13-3. block diagra m of security function edge detection intc intpn rtostn rtpoutn0 to rtpoutn5 rtpn0 to rtpn5 ev dd r 6 remark n = 0, 1 this function is set with the pllc tl.rtost1 and pllctl.rtost0 bits. chapter 13 real-time output function (rto) preliminary user?s manual u17702ej1v0ud 455 (1) pll control register (pllctl) the pllctl register is an 8-bit register that controls the rto security function and pll. this register can be read or writt en in 8-bit or 1-bit units. after reset, pllctl is set to 01h. 0 pllctl 0 0 0 rtost1 rtost0 selpll note pllon note intpn pin is not used as trigger for security function intpn pin is used as trigger for security function rtostn 0 1 control of rtpn0 to rtpn5 security function after reset: 01h r/w address: fffff806h < > < > < > < > note for details on the selpll and pllon bits, refer to chapter 6 clock generation function . cautions 1. before outputting a value to th e real-time output ports (rtpn0 to rtpn5), select the intpn pin interrupt edge de tection and then set the rtost0 and rtost1 bits. 2. to set again the ports (p50 to p55, p60 to p65 pins) as real-time output ports after placing them in high impedance via the intpn pin, first cancel the security function. [procedure to set ports again] <1> cancel the security function and enable port setting by clearing the rtostn bit to 0. <2> set the rtostn bit to 1 (only if required) <3> set again as real-time output port. 3. be sure to clear bits 4 to 7 to 0. remark n = 0, 1 preliminary user?s manual u17702ej1v0ud 456 chapter 14 a/d converter 14.1 overview the a/d converter converts analog input signals into digital values and has a 16-channel (ani0 to ani15) configuration. the a/d converter has the following functions. operating voltage (av ref0 ): 2.7 to 5.5 v successive approximation method 10-bit a/d converter analog input pin: 16 trigger mode: ? software trigger mode ? timer trigger mode (inttm010) ? external trigger mode (adtrg pin) operation mode ? select mode ? scan mode a/d conversion time: ? normal mode: 14 to 100 s @ 4.0 v av ref0 5.5 v 17 to 100 s @ 2.7 v av ref0 < 4.0 v ? high-speed mode: 3 to 100 s @ 4.5 v av ref0 5.5 v 4.8 to 100 s @ 4.0 v av ref0 < 4.5 v 6 to 100 s @ 2.85 v av ref0 < 4.0 v 14 to 100 s @ 2.7 v av ref0 < 2.85 v power fail detection function caution when using the a/d converter, operate with av ref0 at the same potential as v dd and ev dd . 14.2 functions (1) 10-bit resolution a/d conversion 1 analog input channel is selected from the ani0 to ani15 pins, and an a/d conversion operation with resolution of 10 bits is repeatedly executed. every ti me a/d conversion is completed, an interrupt request signal (intad) is generated. (2) power fail detection function this is a function to detect low voltage in a battery. the results of a/d conversi on (the value in the adcrh register) and the pft register are compared, and in tad signal is generated only when the comparison conditions match. chapter 14 a/d converter preliminary user?s manual u17702ej1v0ud 457 14.3 configuration the a/d converter consists of the following hardware. figure 14-1. block diag ram of a/d converter ani0 ani1 ani2 ani3 ani4 ani11 ani12 ani13 ani14 ani15 ani5 ani6 ani7 ani8 ani9 ani10 av ref0 av ss intad adcs bit 4 ads3 ads2 ads1 ads0 ega1 ega0 trg adtmd fr0 adhs1 adhs0 adcs2 adcs admd fr2 fr1 sample & hold circuit av ss voltage comparator controller edge detector adtrg inttm010 adcr/adcrh register pft register ads register adm register pfen pfcm pfm register internal bus sar register comparator tap selector selector selector table 14-1. registers of a/ d converter used by software item configuration registers a/d conversion result register (adcr) a/d conversion result register h (adcrh): only higher 8 bits can be read power fail comparison threshold register (pft) a/d converter mode register (adm) analog input channel specification register (ads) power fail comparison mode register (pfm) chapter 14 a/d converter preliminary user?s manual u17702ej1v0ud 458 (1) ani0 to ani15 pins these are analog input pins for the 16 channels of the a/ d converter. they are used to input analog signals to be converted into digital signals. pins other than thos e selected as analog input by the ads register can be used as input ports. (2) sample & hold circuit the sample & hold circuit samples the analog input si gnals selected by the input circuit and sends the sampled data to the voltage comparator. this ci rcuit holds the sampled analog input voltage during a/d conversion. (3) series resistor string the series resistor string is connected between av ref0 and av ss and generates a voltage for comparison with the analog input signal. (4) voltage comparator the voltage comparator com pares the value that is sampled and hel d with the output voltage of the series resistor string. (5) successive approximation register (sar) this register compares the sampled analog voltage value with the voltage value from the series resistor string, and converts the comparison result starti ng from the most significant bit (msb). when the least significant bit (lsb) has been converted to a digital value (end of a/d conversion), the contents of the sar register are transfe rred to the adcr register. the sar register cannot be read or written directly. (6) a/d conversion result register (adcr) , a/d conversion result register h (adcrh) each time a/d conversion ends, the conversion results are loaded from the successive approximation register and the results of a/d conversion are held in the higher 10 bits of this regist er (the lower 6 bits are fixed to 0). (7) controller the controller compares the a/d c onversion results (the value of the adcrh register) with the value of the pft register when a/d conversion ends or the power fail detection function is used. it generates intad signal only when the comparison conditions match. (8) av ref0 pin this is the analog power supply pin/reference voltage input pin of the a/d converter. always use the same potential as the v dd pin even when not using the a/d converter. the signals input to the ani0 to ani15 pins are c onverted into digital signals based on the voltage applied across av ref0 and av ss . (9) av ss pin this is the ground potential pin of the a/d converter. always use the same potential as the v ss pin even when not using the a/d converter. chapter 14 a/d converter preliminary user?s manual u17702ej1v0ud 459 (10) a/d converter mode register (adm) this register sets the conversion time of the analog input to be converted to a digital signal and the conversion operation start/stop. (11) analog input channel sp ecification register (ads) this register specifies the input port for the analog voltage to be converted to a digital signal. (12) power fail comparis on mode register (pfm) this register sets the power fail detection mode. (13) power fail comparison threshold register (pft) this register sets the threshold to be compared with the adcr register. 14.4 registers the a/d converter is controlle d by the following registers. ? a/d converter mode register (adm) ? analog input channel specification register (ads) ? power fail comparison mode register (pfm) ? power fail comparison threshold register (pft) ? a/d conversion result register, a/d c onversion result register h (adcr, adcrh) chapter 14 a/d converter preliminary user?s manual u17702ej1v0ud 460 (1) a/d converter mode register (adm) this register sets the conversion time of the analog input signal to be convert ed into a digital signal as well as conversion start and stop. the adm register can be read or wr itten in 8-bit or 1-bit units. reset sets this register to 00h. adcs adcs 0 1 conversion operation stopped conversion operation enabled control of a/d conversion operation adm admd fr2 note 1 fr1 note 1 fr0 note 1 adhs1 note 1 adhs0 note 1 adcs2 admd 0 1 select mode scan mode control of operation mode adhs1 0 1 normal mode high-speed mode (valid only when av ref0 4.5 v) selection of 5 v a/d conversion time mode (av ref0 4.5 v) adhs0 0 1 normal mode high-speed mode (valid only when av ref0 2.7 or 2.85 v) selection of 3 v a/d conversion time mode (av ref0 2.7 or 2.85 v) after reset: 00h r/w address: fffff200h adcs2 0 1 reference voltage generator operation stopped reference voltage generator operation enabled control of reference voltage generator for boosting note 2 < > < > notes 1. for details of the fr2 to fr0 bits and the a/d conversion, refer to table 14-2 a/d conversion time . 2. the operation of the reference vo ltage generator for boosting is controlled by the adcs bit and it takes 1 s (high-speed mode) or 14 s (normal mode) after operation is started until it is stabilized. therefore, the adcs2 bit is set to 1 (a /d conversion is started) at least 1 s (high-speed mode) or 14 s (normal mode) after if the adcs2 bit was set to 1 (reference voltage generator for boosting is on), the first conversion result is valid. cautions 1. changing bits fr2 to fr0, adhs1, a nd adhs0 while the adcs bit = 1 is prohibited (write access to the adm register is enabled and re writing of bits fr2 to fr0, adhs1, and adhs0 is prohibited). 2. setting adhs1 and adhs0 bits to 11 is prohibited. 3. do not access the adm regi ster when the main clock is stopped and the subclock is operating. for details, refer to 3.4.8 (1) (b) access to special on-chip peripheral i/o register. chapter 14 a/d converter preliminary user?s manual u17702ej1v0ud 461 table 14-2. a/d conversion time a/d conversion time ( s) adhs1 adhs0 fr2 fr1 fr0 20 mhz@ av ref0 4.5 v 16 mhz@ av ref0 4.0 v 8 mhz@ av ref0 2.85 v 8 mhz@ av ref0 2.7 v conversion time mode 0 0 0 0 0 288/f xx 14.4 18.0 36.0 36.0 0 0 0 0 1 240/f xx setting prohibited 15.0 30.0 30.0 0 0 0 1 0 192/f xx setting prohibited setting prohibited 24.0 24.0 normal mode av ref0 2.7 v 0 0 0 1 1 setting prohibited 0 0 1 0 0 144/f xx setting prohibited setting prohibited 18.0 18.0 0 0 1 0 1 120/f xx setting prohibited setting prohibited setting prohibited setting prohibited 0 0 1 1 0 96/f xx setting prohibited setting prohibited setting prohibited setting prohibited normal mode av ref0 2.7 v 0 0 1 1 1 setting prohibited 0 1 0 0 0 96/f xx 4.8 6.0 12.0 setting prohibited 0 1 0 0 1 72/f xx setting prohibited setting prohibited 9.0 setting prohibited 0 1 0 1 0 48/f xx setting prohibited setting prohibited 6.0 setting prohibited 0 1 0 1 1 24/f xx setting prohibited setting prohibited setting prohibited setting prohibited high-speed mode av ref0 2.85 v 0 1 1 0 0 224/f xx 11.2 14.0 28.0 28.0 0 1 1 0 1 168/f xx setting prohibited 10.5 21.0 21.0 0 1 1 1 0 112/f xx setting prohibited setting prohibited setting prohibited setting prohibited 0 1 1 1 1 56/f xx setting prohibited setting prohibited setting prohibited setting prohibited high-speed mode av ref0 2.7 v 1 0 0 0 0 72/f xx 3.6 setting prohibited setting prohibited setting prohibited 1 0 0 0 1 54/f xx setting prohibited setting prohibited setting prohibited setting prohibited 1 0 0 1 0 36/f xx setting prohibited setting prohibited setting prohibited setting prohibited 1 0 0 1 1 18/f xx setting prohibited setting prohibited setting prohibited setting prohibited high-speed mode av ref0 4.5 v 1 0 1 setting prohibited 1 1 setting prohibited remark f xx : main clock frequency chapter 14 a/d converter preliminary user?s manual u17702ej1v0ud 462 (a) controlling reference volt age generator for boosting when the adcs2 bit = 0, power to the a/d converter drops. the converter requires a setup time of 1 s (high-speed mode) or 14 s (normal mode) or more after the adcs2 bit has been set to 1. therefore, the result of a/ d conversion becomes valid from the first result by setting the adcs bit to 1 at least 1 s (high-speed mode) or 14 s (normal mode) after the adcs2 bit has been set to 1. table 14-3. setting of adcs bit and adcs2 bit adcs adcs2 a/d co nversion operation 0 0 stopped status (dc power consumption path does not exist) 0 1 conversion standby mode (only the refer ence voltage generator for boosting consumes power) 1 0 conversion mode (reference voltage generator stops operation note 1 ) 1 1 conversion mode (reference voltage generator is operating note 2 ) notes 1. if the adcs and adcs2 bits are changed from 00b to 10b, the reference voltage generator for boosting automatically turns on. if the adcs bit is cleared to 0 while the adcs2 bit is 0, the voltage generator automatically turns off. in the software trigger mode (ads.trg bit = 0), use of the first a/d conversion result is prohibited. in the hardware trigger mode (trg bit = 1), use t he a/d conversion result on ly if a/d conversion is started after the lapse of the o scillation stabilization time of t he reference voltage generator for boosting. 2. if the adcs and adcs2 bits are changed from 00b to 11b, the reference voltage generator for boosting automatically turns on. if the adcs bit is cleared to 0 while the adcs2 bit is 1, the voltage generator stays on. in the software trigger mode (trg bit = 0), use of the first a/d conversion result is prohibited. in the hardware trigger mode (trg bit = 1), use t he a/d conversion result on ly if a/d conversion is started after the lapse of the o scillation stabilization time of t he reference voltage generator for boosting. figure 14-2. operation sequence comparator control conversion operation conversion standby conversion operation conversion stop adcs adcs2 note reference voltage generator for boosting: operating note 1 s (high-speed mode) or 14 s (normal mode) or more are required for the operation of the reference voltage generator for boosting between when the adcs2 bit is set (1) and when the adcs bit is set (1). chapter 14 a/d converter preliminary user?s manual u17702ej1v0ud 463 (2) analog input channel specification register (ads) this register specifies the analog vo ltage input port for a/d conversion. the ads register can be read or wr itten in 8-bit or 1-bit units. reset sets this register to 00h. (1/2) ega1 note 1 ads ega0 note 1 trg adtmd note 2 ads3 ads2 ads1 ads0 no edge detection falling edge rising edge both rising and falling edges ega1 note 1 0 0 1 1 ega0 note 1 0 1 0 1 specification of external trigger signal (adtrg) edge after reset: 00h r/w address: fffff201h trg 0 1 software trigger mode hardware trigger mode trigger mode selection adtmd note 2 0 1 external trigger (adtrg pin input) timer trigger (inttm010 signal generated) specification of hardware trigger mode notes 1. the ega1 and ega0 bits are valid only when t he hardware trigger mode (trg bit = 1) and external trigger mode (adtrg pin input: adtmd bit = 1) are selected. 2. the adtmd bit is valid only when the hardware trigger mode (trg bit = 1) is selected. caution do not access the ads regist er when the main clock is stoppe d and the subclock is operating. for details, refer to 3.4.8 (1) (b) access to special on-chip peripheral i/o register. chapter 14 a/d converter preliminary user?s manual u17702ej1v0ud 464 (2/2) ani0 ani1 ani2 ani3 ani4 ani5 ani6 ani7 ani8 ani9 ani10 ani11 ani12 ani13 ani14 ani15 ani0 ani0, ani1 ani0 to ani2 ani0 to ani3 ani0 to ani4 ani0 to ani5 ani0 to ani6 ani0 to ani7 ani0 to ani8 ani0 to ani9 ani0 to ani10 ani0 to ani11 ani0 to ani12 ani0 to ani13 ani0 to ani14 ani0 to ani15 ads3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 ads2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 ads1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 ads0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 specification of analog input channel select mode scan mode (3) a/d conversion result register, a/d conversion result register h (adcr, adcrh) the adcr and adcrh registers stor e the a/d conversion results. these registers are read-only in 16-bit or 8-bit units. however, specify the adcr register for 16-bit access, and the adcrh register for 8-bit access. in the adcr r egister, the 10 bits of conversion results are read in the higher 10 bits and 0 is read in the lower 6 bits. in the adcrh register, the higher 8 bits of the conversion results are read. reset makes these registers undefined. after reset: undefined r address: fffff204h adcr ad9 ad8 ad7 ad6 ad0 0 0 0 0 0 0 ad1 ad2 ad3 ad4 ad5 ad9 adcrh ad8 ad7 ad6 ad5 ad4 ad3 ad2 76 54 32 1 0 after reset: undefined r address: fffff205h caution do not access the adcr and adcrh registers when the main clock is stopped and the subclock is operating. for details, refer to 3.4.8 (1) (b) access to special on-chip peripheral i/o register. chapter 14 a/d converter preliminary user?s manual u17702ej1v0ud 465 the following shows the relationship between the analog i nput voltage input to the analog input pins (ani0 to ani15) and a/d conversion results (adcr register). sar = int ( 1024 + 0.5) adcr note = sar 64 or, (sar ? 0.5) v in < (sar + 0.5) int ( ): function that returns the in teger part of the value in parentheses v in : analog input voltage av ref0 : voltage of av ref0 pin adcr: value in the adcr register note the lower 6 bits of the a dcr register are fixed to 0. the following shows the relationship between the ana log input voltage and a/ d conversion results. figure 14-3. relationship between analog input voltage and a/d conversion results 1023 1022 1021 ffc0h ff80h ff40h 3 2 1 0 00c0h 0080h 0040h 0000h input voltage/av ref0 1 2048 1 1024 3 2048 2 1024 5 2048 3 1024 2043 2048 1022 1024 2045 2048 1023 1024 2047 2048 1 a/d conversion results sar adcr v in av ref0 av ref0 1024 av ref0 1024 chapter 14 a/d converter preliminary user?s manual u17702ej1v0ud 466 (4) power fail comparison mode register (pfm) this register sets the power fail detection mode. the pfm register compares the value in the p ft register with the val ue of the adcrh register. the pfm register can be read or wr itten in 8-bit or 1-bit units. reset sets this register to 00h. pfen pfen 0 1 power fail comparison disabled power fail comparison enabled selection of power fail comparison enable/disable pfm pfcm 0 0 0 0 0 0 pfcm 0 1 interrupt request signal (intad) generated when adcr pft interrupt request signal (intad) generated when adcr < pft selection of power fail comparison mode after reset: 00h r/w address: fffff202h < > < > caution do not access the pfm re gister when the main clock is stopped and the subclock is operating. for details, refer to 3.4.8 (1) (b) access to special on -chip peripheral i/o register. (5) power fail comparison th reshold register (pft) the pft register sets the comparison value in the power fail detection mode. the 8-bit data set in the pft register is co mpared with the value of the adcrh register. the pft register can be read or written in 8-bit units. reset sets this register to 00h. pft after reset: 00h r/w address: fffff203h 76 54 321 0 caution do not access the pft regi ster when the main clock is stopped and the subclock is operating. for details, refer to 3.4.8 (1) (b) access to special on -chip peripheral i/o register. chapter 14 a/d converter preliminary user?s manual u17702ej1v0ud 467 14.5 operation 14.5.1 basic operation <1> select the channel whose analog signal is to be c onverted into a digital signal using the ads register. set the adm.adhs1 or adm.adhs0 bit. <2> set the adm.adcs2 bit to 1 and wait 1 s (high-speed mode) or 14 s (normal mode) or longer. <3> set the adm.adcs bit to 1 to start a/d conversion. (steps <4> to <10> are executed by hardware.) <4> the sample & hold circuit samples the voltage input to the selected analog input channel. <5> after sampling for a specific time, the sample & hold circuit enters the hold stat us and holds the input analog voltage until it has been converted into a digital signal. <6> set bit 9 of the successive approximation register (sar) to 1. the tap selector sets the voltage tap of the series resistor string to (1/2) av ref0 . <7> the voltage comparator compares t he voltage difference between the voltage tap of the series resistor string and the analog input voltage. if the ana log input voltage is greater than (1/2) av ref0 , the msb of the sar register remains set to 1. if the analog input voltage is less than (1/2) av ref0 , the msb is cleared to 0. <8> next, bit 8 of the sar register is automatically se t to 1 and the next comparison starts. depending on the previously determined value of bit 9, the voltage tap of the series resistor string is selected as follows. ? bit 9 = 1: (3/4) av ref0 ? bit 9 = 0: (1/4) av ref0 the analog input voltage is compared with one of th ese voltage taps and bit 8 of the sar register is manipulated as follows depending on the result of the comparison. analog input voltage voltage tap: bit 8 = 1 analog input voltage voltage tap: bit 8 = 0 <9> the above steps are repeated until bit 0 of the sar register has been manipulated. <10> when comparison of all 10 bits of the sar register ha s been completed, the valid digital value remains in the sar register, and the value of the sar register is transferred and latched to the adcr register. at the same time, an a/d conversion end interrupt request signal (intad) is generated. <11> repeat steps <4> to <10> until the adcs bit is cleared to 0. for another a/d conversion, start at <3>. however, when operating the a/d converter with the adcs2 bit cleared to 0, start at <2>. chapter 14 a/d converter preliminary user?s manual u17702ej1v0ud 468 14.5.2 trigger modes the v850es/kj2 has the following three trigger modes that set the a/d conversion start timing. these trigger modes are set by the ads register. ? software trigger mode ? external trigger mode (hardware trigger mode) ? timer trigger mode (hardware trigger mode) (1) software trigger mode this mode is used to start a/d conversion by setting t he adm.adcs bit to 1 while the ads.trg bit is 0. conversion is repeatedly performed as long as the a dcs bit is not cleared to 0 after completion of a/d conversion. if the adm, ads, pfm, or pft register is written during conversion, a/d conver sion is aborted and started again from the beginning. (2) external trigger mode (hardware trigger mode) this is the status in which the ads.trg bit is set to 1 and ads.adtmd bit is cleared to 0. this mode is used to start a/d conversion by detecting an external tr igger (adtrg) after the adcs bit has been set to 1. the a/d converter waits for the external trigge r (adtrg) after the adcs bit is set to 1. the valid edge of the signal input to the adtrg pin is specified by using the ads. ega1 and ads.ega0 bits. when the specified valid edge is det ected, a/d conversion is started. when a/d conversion is completed, the a/d converte r waits for the external trigger (adtrg) again. if a valid edge is input to the adtrg pin during a/d conversion, a/d conversion is aborted and started again from the beginning. if the adm, ads, pfm, or pft regi ster is written during conversion, a/d conversion is aborted and the a/d converter waits for an external trigger (adtrg). (3) timer trigger mode (hardware trigger mode) this mode is used to start a/d conversion by detecti ng a timer trigger (inttm010) after the adcs bit has been set to 1 with the tgr bit = 1 and adtmd bit = 1. the a/d converter waits for the timer trigger (inttm010) after the adcs bit is set to 1. when the inttm010 signal is generated, a/d conversion is started. when a/d conversion is completed, the a/d converte r waits for the timer trigger (inttm010) again. if the inttm010 signal is generated duri ng a/d conversion, a/d conversion is aborted and started again from the beginning. if the adm, ads, pfm, or pft regi ster is written during conversion, a/d conversion is aborted and the a/d converter waits for a timer trigger (inttm010). chapter 14 a/d converter preliminary user?s manual u17702ej1v0ud 469 14.5.3 operation modes the following two operation modes are available. t hese operation modes are set by the adm register. ? select mode ? scan mode (1) select mode one input analog signal specified by the ads register while the adm.ad md bit = 0 is converted. when conversion is complete, the result of c onversion is stored in the adcr register. at the same time, the a/d conversion end interrupt r equest signal (intad) is generat ed. however, the intad signal may or may not be generated depending on setting of the pfm and pft registers. for details, refer to 14.5.4 power fail detection function . if anything is written to the adm, ads, pfm, and pft r egisters during conversion, a/ d conversion is aborted. in the software trigger mode, a/d conv ersion is started from the beginni ng again. in the hardware trigger mode, the a/d converter waits for a trigger. if the trigger is detected during conversion in hardwar e trigger mode, a/d conver sion is aborted and started again from the beginning. figure 14-4. example of select mode operat ion timing (ads.ads3 to ads.ads0 bits = 0001b) ani1 a/d conversion data 1 (ani1) data 2 (ani1) data 1 data 2 data 1 (ani1) data 2 (ani1) adcr intad conversion start set adcs bit = 1 conversion start set adcs bit = 1 conversion end conversion end chapter 14 a/d converter preliminary user?s manual u17702ej1v0ud 470 (2) scan mode in this mode, the analog signals specified by the ad s register and input from the ani0 pin while the adm.admd bit = 1 are sequentially selected and converted. when conversion of one analog input signal is complete, t he conversion result is st ored in the adcr register and, at the same time, the a/d conversion end interrupt request signal (intad) is generated. the a/d conversion results of all t he analog input signals are stored in t he adcr register. it is therefore recommended to save the contents of the adcr regist er to ram once a/d conversion of one analog input signal has been completed. in the hardware trigger mode (ads.trg bit = 1), the a/ d converter waits for a trigger after it has completed a/d conversion of the analog signals specified by the ads register and input from the ani0 pin. if anything is written to the adm, ads, pfm, and pft r egisters during conversion, a/ d conversion is aborted. in the software trigger mode, a/d conv ersion is started from the beginni ng again. in the hardware trigger mode, the a/d converter waits for a trigger. conversion starts again from the ani0 pin. if the trigger is detected during conversion in hardwar e trigger mode, a/d conver sion is aborted and started again from the beginning (ani0 pin). chapter 14 a/d converter preliminary user?s manual u17702ej1v0ud 471 figure 14-5. example of scan mode operati on timing (ads.ads3 to ads.ads0 bits = 0011b) (a) timing example a/d conversion data 1 (ani0) data 2 (ani1) data 3 (ani2) data 4 (ani3) data 1 (ani0) data 2 (ani1) data 3 (ani2) data 4 (ani3) adcr intad conversion start set adcs bit = 1 conversion end ani3 ani0 ani1 ani2 data 1 data 2 data 3 data 4 data 6 data 5 data 7 (b) block diagram a/d converter adcr register analog input pin ani0 ani1 ani2 ani3 ani4 ani5 ani13 ani14 ani15 . . . . adcr chapter 14 a/d converter preliminary user?s manual u17702ej1v0ud 472 14.5.4 power fail detection function the conversion end interrupt request si gnal (intad) can be controlled as fo llows using the pfm and pft registers. ? if the pfm.pfen bit = 0, the intad signal is generated each time conversion ends. ? if the pfen bit = 1 and the pfm.pfcm bi t = 0, the conversion result (adcrh register) and the value of the pft register are compared when conversion ends, and the intad signal is generated only if adcrh pft. ? if the pfen and pfcm bits = 1, the conversion result and the value of t he pft register are compared when conversion ends, and the intad signal is generated only if adcrh < pft. ? because, when the pfen bit = 1, the conversion result is overwritt en after the intad signal has been generated, unless the conversion result is read by the time the next conversion ends, in some cases it may appear as if the actual operation differs from the operation described above (refer to figure 14-6 ). figure 14-6. power fail detection function (pfcm bit = 0) conversion operation adcrh pft intad ani0 80h 80h 7fh 80h ani0 ani0 ani0 note note if reading is not performed during this interval, the conv ersion result changes to the next conversion result. chapter 14 a/d converter preliminary user?s manual u17702ej1v0ud 473 14.5.5 setting method the following describes how to set registers. (1) when using the a/d converter for a/d conversion <1> set (1) the adm.adcs2 bit. <2> select the channel and conversion time by setting the ads.ads3 to ads.ads0 bits and the adm.adhs1, adm.adhs0, and adm.fr2 to adm.fr0 bits. <3> set (1) the adm.adcs bit. <4> transfer the a/d conversion data to the adcr register. <5> an interrupt request signal (intad) is generated. chapter 14 a/d converter preliminary user?s manual u17702ej1v0ud 474 14.6 cautions (1) power consumpti on in standby mode the operation of the a/d converter st ops in the standby mode. at this time, the power consumption can be reduced by stopping the conversion operation (the adm.adcs bit = 0). figure 14-7 shows an example of how to reduce the power consumpti on in the standby mode. figure 14-7. example of how to redu ce power consumption in standby mode adcs series resistor string av ref0 p-ch av ss (2) input range of ani0 to ani15 pins use the a/d converter with the ani0 to ani15 pin input voltages within the specified range. if a voltage of av ref0 or higher or av ss or lower (even if within the absolute maxi mum ratings) is input to these pins, the conversion value of the channel is undefined. also, this may affect the conversion value of other channels. (3) conflicting operations (a) conflict between writing to t he adcr register and reading from adcr register upon the end of conversion reading the adcr register takes precedence. after the register has been read, a new conversion result is written to the adcr register. (b) conflict between writing to the adcr register and writing to the adm register or writing to the ads register upon the end of conversion writing to the adm register or ads register takes precedence. the adcr regist er is not written, and neither is the conversion end interr upt request signal (intad) generated. chapter 14 a/d converter preliminary user?s manual u17702ej1v0ud 475 (4) measures against noise to keep a resolution of 10 bits, be aware of noise on the av ref0 and ani0 to ani15 pins. the higher the output impedance of the analog input sour ce, the greater the effect of noise. therefore, it is recommended to connect external capacitors as shown in figure 14-8 to reduce noise. figure 14-8. handling of analog input pins av ref0 ani0 to ani15 av ss v ss if noise of av ref0 or higher or av ss or lower could be generated, clamp with a diode with a small v f (0.3 v or lower). reference voltage input c 0.1 f (5) ani0/p70 to ani15/p715 pins the analog input pins (ani0 to ani15) function alternately as input port pins (p70 to p715). when performing a/d conversion by selecting any of the ani0 to ani15 pins, do not execute an input instruction to port 7 during conversion. th is may decrease the conversion resolution. if digital pulses are applied to the pin adjacent to the pin subject to a/d conversi on, the value of the a/d conversion may differ from the expected value because of coupling noise. therefore, do not apply pulses to the pin adjacent to the pin subject to a/d conversion. (6) input impedance of av ref0 pin a series resistor string of tens of k ? is connected between the av ref0 pin and av ss pin. therefore, if the output im pedance of the reference voltage source is high, this will result in a series connection to the series resistor string between the av ref0 pin and av ss pin, resulting in a large reference voltage error. chapter 14 a/d converter preliminary user?s manual u17702ej1v0ud 476 (7) interrupt request flag (adic.adif bit) even when the ads register is changed, the adif bit is not cleared (0). therefore, if the analog input pin is changed during a/d conversion, the adif bit may be set (1) because a/d conversion of the previous analog input pin ends immediately before the ads register is rewritten. in a such case, note that if the adif bit is r ead immediately after the ads register ha s been rewritten, the adif bit is set (1) even though a/d conversion of the analog in put pin after the change has not been completed. when stopping a/d conversion once and resuming it, clea r the adif bit (0) before resuming a/d conversion. figure 14-9. a/d conversion end in terrupt request occurrence timing anin anin anin anim anim anin anim anim a/d conversion adcr intad ads rewrite (anin conversion start) ads rewrite (anim conversion start) anim conversion is not complete even though adif is set. remark n = 0 to 15 m = 0 to 15 (8) conversion results immediat ely after a/d conversion start if the adm.adcs bit is set to 1 within 1 s (high-speed mode) or 14 s (normal mode) after the adm.adcs2 bit has been set to 1, or if the adcs bit is set to 1 with the adcs2 bit cleared to 0, the converted value immediately after the a/d conversion operation has st arted may not satisfy the rating. take appropriate measures such as polling the a/d conversion end inte rrupt request signal (intad) and discarding the first conversion result. (9) reading a/d conversion result register (adcr) when the adm or ads register has been written, the contents of the adcr register may become undefined. when the conversion operation is complete, read the co nversion results before writing to the adm or ads register. a correct conversion result may not be able to be read at a timing other than the above. accessing the adcr and adcrh registers is prohibit ed when the cpu operates with the subclock and the main clock oscillation (f x ) is stopped. for details, refer to 3.4.8 (1) (b) access to speci al on-chip peripheral i/o register . chapter 14 a/d converter preliminary user?s manual u17702ej1v0ud 477 (10) a/d converter sampling time a nd a/d conversion start delay time the a/d converter sampling time differs depending on the se t value of the adm register. a delay time exists until actual sampling is started after a/d converter operation is enabled. when using a set in which the a/d conversion time must be strictly observed, care is required for the contents shown in figure 14-10 and table 14-4. figure 14-10. timing of a/d converter sampling and a/d conversion start delay adcs wait period conversion time conversion time register write response time/trigger response time sampling time sampling timing intad adcs bit 1 or ads register rewrite sampling time chapter 14 a/d converter preliminary user?s manual u17702ej1v0ud 478 table 14-4. a/d converter conversion time register write response time note trigger response time note adhs1 adhs0 fr2 fr1 fr0 conversion time sampling time min. max. min. max. 0 0 0 0 0 288/f xx 176/f xx 11/f xx 12/f xx 7/f xx 8/f xx 0 0 0 0 1 240/f xx 176/f xx 11/f xx 12/f xx 7/f xx 8/f xx 0 0 0 1 0 192/f xx 132/f xx 10/f xx 11/f xx 6/f xx 7/f xx 0 0 1 0 0 144/f xx 88/f xx 9/f xx 10/f xx 5/f xx 6/f xx 0 0 1 0 1 120/f xx 88/f xx 9/f xx 10/f xx 5/f xx 6/f xx 0 0 1 1 0 96/f xx 48/f xx 11/f xx 12/f xx 7/f xx 8/f xx 0 1 0 0 0 96/f xx 48/f xx 11/f xx 12/f xx 7/f xx 8/f xx 0 1 0 0 1 72/f xx 36/f xx 10/f xx 11/f xx 6/f xx 7/f xx 0 1 0 1 0 48/f xx 24/f xx 9/f xx 10/f xx 5/f xx 6/f xx 0 1 0 1 1 24/f xx 12/f xx 8/f xx 9/f xx 4/f xx 5/f xx 0 1 1 0 0 224/f xx 176/f xx 11/f xx 12/f xx 7/f xx 8/f xx 0 1 1 0 1 168/f xx 132/f xx 10/f xx 11/f xx 6/f xx 7/f xx 0 1 1 1 0 112/f xx 88/f xx 9/f xx 10/f xx 5/f xx 6/f xx 0 1 1 1 1 56/f xx 44/f xx 8/f xx 9/f xx 4/f xx 5/f xx 1 0 0 0 0 72/f xx 24/f xx 11/f xx 12/f xx 7/f xx 8/f xx 1 0 0 0 1 54/f xx 18/f xx 10/f xx 11/f xx 6/f xx 7/f xx 1 0 0 1 0 36/f xx 12/f xx 9/f xx 10/f xx 5/f xx 6/f xx 1 0 0 1 1 18/f xx 6/f xx 8/f xx 9/f xx 4/f xx 5/f xx other than above setting prohibited ? ? ? ? ? note each response time is the time after the wa it period. for the wait function, refer to 3.4.8 (1) (b) access to special on-chip peripheral i/o register . remark f xx : main clock frequency chapter 14 a/d converter preliminary user?s manual u17702ej1v0ud 479 (11) internal equivalent circuit the following shows the equivalent circuit of the analog input block. figure 14-11. internal equi valent circuit of anin pin anin c out c in r in av ref0 r in c out c in 4.5 v 3 k ? 8 pf 15 pf 2.7 v 60 k ? 8 pf 15 pf remarks 1. the above values are reference values. 2. n = 0 to 15 (12) variation of a/d conversion results the results of the a/d conversion may vary depending on the fluctuation of the supply voltage, or may be affected by noise. to reduce the variation, take coun teractive measures with the program such as averaging the a/d conversion results. (13) a/d conversion result hysteresis characteristics the successive approximation type a/d co nverter holds the analog input voltage in the internal sample & hold capacitor and then performs a/d conversion. after t he a/d conversion has finished, the analog input voltage remains in the internal sample & hold capacitor. as a result, the following phenomena may occur. ? when the same channel is used for a/d conversions, if th e voltage is higher or lo wer than the previous a/d conversion, then hysteresis characteristics may appear where the conversion resu lt is affected by the previous value. thus, even if t he conversion is performed at the same potential, the result may vary. ? when switching the analog input cha nnel, hysteresis characteristics may appear where the conversion result is affected by the previous channel value. this is because one a/d converter is used for the a/d conversions. thus, even if the conversion is perfo rmed at the same potential, the result may vary. therefore, to obtain more accurate conversion result, perform a/d conversion twice successively for the same channel, and discard the first conversion result. chapter 14 a/d converter preliminary user?s manual u17702ej1v0ud 480 14.7 how to read a/d converter characteristics table here, special terms unique to the a/d converter are explained. (1) resolution this is the minimum analog input voltag e that can be identified. that is , the percentage of the analog input voltage per bit of digital output is called 1 lsb (least si gnificant bit). the percent age of 1 lsb with respect to the full scale is expressed by %fsr (full scale range). %fsr indicates the ratio of analog input voltage that can be converted as a percentage, and is always r epresented by the following formula regardless of the resolution. 1 %fsr = (max. value of analog in put voltage that can be converted ? min. value of analog input voltage that can be converted)/100 = (av ref0 ? 0)/100 = av ref0 /100 1 lsb is as follows when the resolution is 10 bits. 1 lsb = 1/2 10 = 1/1024 = 0.098 %fsr accuracy has no relation to resolution, but is determined by overall error. (2) overall error this shows the maximum error value between the actual measured value and the theoretical value. zero-scale error, full-scale error, linearity error and erro rs that are combinations of these express the overall error. note that the quantization error is not included in the overall erro r in the characteristics table. figure 14-12. overall error ideal line 0 ?? 0 1 ?? 1 digital output overall error analog input av ref0 0 chapter 14 a/d converter preliminary user?s manual u17702ej1v0ud 481 (3) quantization error when analog values are converted to digital values, a 1/2 lsb error naturally occurs. in an a/d converter, an analog input voltage in a range of 1/2 lsb is converted to the same digital code, so a quantization error cannot be avoided. note that the quantization error is not included in the over all error, zero-scale error, full-scale error, integral linearity error, and differential linearity error in the characteristics table. figure 14-13. quan tization error 0 ?? 0 1 ?? 1 digital output quantization error 1/2 lsb 1/2 lsb analog input 0 av ref0 (4) zero-scale error this shows the difference between the actual meas urement value of the analog input voltage and the theoretical value (1/2 lsb) when the digital output changes from 0??000 to 0??001. figure 14-14. zero-scale error 111 011 010 001 zero-scale error ideal line 000 01 2 3 av ref0 digital output (lower 3 bits) analog input (lsb) -1 100 chapter 14 a/d converter preliminary user?s manual u17702ej1v0ud 482 (5) full-scale error this shows the difference between the actual meas urement value of the analog input voltage and the theoretical value (full scale ? 3/2 lsb) when the digital output changes from 1??110 to 1??111. figure 14-15. full-scale error 100 011 010 000 0 av ref0 av ref0 ?1 av ref0 ?2 av ref0 ?3 digital output (lower 3 bits) analog input (lsb) full-scale error 111 (6) differential linearity error while the ideal width of code output is 1 lsb, this indicates the difference between the actual measurement value and the ideal value. this indicates the basic characteristics of the a/d conversion when the voltage applied to the analog input pins of the same channel is consistently increased bit by bit from av ss to av ref0 . when the input voltage is increased or decreased, or when two or more channels are used, refer to 14.7 (2) overall error . figure 14-16. differential linearity error 0 av ref0 digital output analog input differential linearity error 1 ?? 1 0 ?? 0 ideal 1 lsb width chapter 14 a/d converter preliminary user?s manual u17702ej1v0ud 483 (7) integral linearity error this shows the degree to which the conversion characterist ics deviate from the ideal linear relationship. it expresses the maximum value of the difference between the actual measur ement value and the ideal straight line when the zero-scale error and full-scale error are 0. figure 14-17. integral linearity error 0 av ref0 digital output analog input integral linearity error ideal line 1 ?? 1 0 ?? 0 (8) conversion time this expresses the time from when the analog input vo ltage was applied to the time when the digital output was obtained. the sampling time is included in the conv ersion time in the characteristics table. (9) sampling time this is the time the analog switch is turned on for the analog voltage to be sampled by the sample & hold circuit. figure 14-18. sampling time sampling time conversion time preliminary user?s manual u17702ej1v0ud 484 chapter 15 d/a converter 15.1 functions in the v850es/kj2, two channels of d/a converter (dac0, dac1) are provided. the d/a converter has the following functions. { 8-bit resolution 2 channels { r-2r ladder string method { conversion time: 20 s (max.) (av ref1 = 2.7 to 5.5 v) { analog output voltage: av ref1 m/256 (m = 0 to 255; value set to dacsn register) { operation modes: normal mo de, real-time output mode remark n = 0, 1 chapter 15 d/a converter preliminary user?s manual u17702ej1v0ud 485 15.2 configuration the d/a converter configurat ion is shown below. figure 15-1. block diag ram of d/a converter dacs0 selector selector dacs1 ano0 ano1 dace0 dace1 dacs0 register write dam.damd0 bit inttmh0 signal dacs1 register write dam.damd1 bit inttmh1 signal av ref1 av ss caution dac0 and dac1 share the av ref1 and av ss pins. the av ss pin is also shared by the a/d converter. the d/a converter consists of the following hardware. table 15-1. configuration of d/a converter item configuration control register d/a converter mode register (dam) d/a conversion value setting regi sters 0 and 1 (dacs0, dacs1) chapter 15 d/a converter preliminary user?s manual u17702ej1v0ud 486 15.3 registers the registers that control the d/ a converter are as follows. ? d/a converter mode register (dam) ? d/a conversion value setting registers 0 and 1 (dacs0, dacs1) (1) d/a converter mode register (dam) this register controls the oper ation of the d/a converter. the dam register can be read or wri tten in 8-bit or 1-bit units. after reset, dam is cleared to 00h. 0 normal mode real-time output mode note damdn 0 1 selection of d/a converter operation mode (n = 0, 1) dam 0 0 0 damd1 dace1 damd0 dace0 after reset: 00h r/w address: fffff284h disable operation enable operation dacen 0 1 d/a converter operation enable/disable control (n = 0, 1) < > < > note the output trigger in the real-time output mode (damdn bit = 1) is as follows. ? when n = 0: inttmh0 signal (refer to chapter 10 8-bit timer h ) ? when n = 1: inttmh1 signal (refer to chapter 10 8-bit timer h ) (2) d/a conversion value setting re gisters 0 and 1 (dacs0, dacs1) these registers set the analog voltage va lue output to the ano0 and ano1 pins. these registers can be read or written in 8-bit units. after reset, dacs0 and dacs1 are cleared to 00h. dan7 dacsn (n = 0, 1) dan6 dan5 dan4 dan3 dan2 dan1 dan0 after reset: 00h r/w address: dacs0 fffff280h, dacs1 fffff282h caution in the real-time output mo de (dam.damdn bit = 1), set th e dacs0 and dacs1 registers before the inttmh0 and inttmh1 signals are generated. d/a conver sion starts when the inttmh0 and inttmh1 signals are generated. chapter 15 d/a converter preliminary user?s manual u17702ej1v0ud 487 15.4 operation 15.4.1 operation in normal mode d/a conversion is performed using a write operat ion to the dacsn register as the trigger. the setting method is described below. <1> clear the dam.damdn bit to 0 (normal mode). <2> set the analog voltage value to be output to the anon pin to the dacsn register. steps <1> and <2> above constitute the initial settings. <3> set the dam.dacen bit to 1 (d/a conversion enable). d/a converted analog voltage value is output from the anon pin when this setting is performed. <4> to change the analog voltage value, write to the dacsn register. the analog voltage value immediately before set is held until the next write oper ation is performed. remarks 1. for the alternate-function pin settings, refer to table 4-19 settings when port pins are used for alternate functions . 2. n = 0, 1 15.4.2 operation in real-time output mode d/a conversion is performed using the interrupt request si gnals (inttmh0, inttmh1) of 8-bit timers h0 and h1 as the trigger. the setting method is described below. <1> set the dam.damdn bit to 1 (real-time output mode). <2> set the analog voltage value to be output to the anon pin to the dacsn register. <3> set the dam.dacen bit to 1 (d/a conversion enable). steps <1> to <3> above constitute the initial settings. <4> operate 8-bit timers h0 and h1. <5> d/a converted analog voltage val ue is output from the anon pin when the inttmh0 and inttmh1 signals are generated. set the next output analog voltage value to the da csn register, before the next inttmh0 and inttmh1 signals are generated. <6> after that, the value set in the dacsn register is output from the anon pin every time the inttmh0 are inttmh1 signals are generated. remarks 1. the output values of the ano0 and ano1 pins up to <5> above are undefined. 2. for the output values of the ano0 and ano1 pi ns in the idle, halt, and stop modes, refer to chapter 23 standby function . 3. n = 0, 1 chapter 15 d/a converter preliminary user?s manual u17702ej1v0ud 488 15.4.3 cautions observe the following cautions when using the d/a converter. ? when using the d/a converter, set the port pins to the input mode (pm10, pm11 bits = 11) ? when using the d/a converter, readi ng of the port is prohibited. ? when using the d/a converter, use both p10 and p11 as d/a outputs. using one of the port 1 for d/a output an d the other as a port is prohibited. ? in the real-time output mode, do not change the set value of the dacsn r egister while the trigger signal is output. ? make sure that av ref1 v dd and av ref1 = 2.7 to 5.5 v. the operation is not guaranteed if ranges other than the above are used. ? because the output impedanc e of the d/a converter is high, a current cannot be supplied from the anon pin. when connecting a resistor of 2 m ? or lower, take appropriate measures such as inserting a jfet input type operational amplifier between the resistor and the anon pin. remark n = 0, 1 figure 15-2. example of external pin connection + ? anon av ref0 av ref1 av ss jfet input type operational amplifier output ev dd 0.1 f 10 f 0.1 f 10 f ? caution the figure shown here is only re ference. use it a fter fully evaluating. preliminary user?s manual u17702ej1v0ud 489 chapter 16 asynchronous serial interface (uart) in the v850es/kj2, three channels of asynchron ous serial interface (uart) are provided. 16.1 uart2 pin the v850es/kj2 has two pairs of rxd2 and txd2 pins for uart2, as shown below. pin name pin no. alternate-function pin 22 p40/si00 rxd2 59 p80/sda1 23 p41/so00 txd2 60 p81/scl1 when using uart2, do not use pins 22 and 59, or pins 23 and 60 at the same time. use pins 22 and 23, or 59 and 60 in pairs. chapter 16 asynchronous serial interface (uart) preliminary user?s manual u17702ej1v0ud 490 16.1.1 selecting uart2 or csi00 mode uart2 and csi00 of the v850es/kj2 shar e pins, and therefore these interfaces cannot be used at the same time. use of uart2 needs to be set in advance by us ing the pmc4 and pfc4 registers (refer to 4.3.4 port 4 ). cautions 1. uart2 or csi00 transm ission/reception operations are not guaranteed if the mode is changed during transmission or r eception. be sure to disable the operation of the unit that is not used. 2. when using pins 22 and 23 as the rxd2 and txd2 pins of uart2, do not set pins 59 and 60 as the rxd2 and txd2 pins. figure 16-1. selecting mode of uart2 or csi00 7 0 pmc4 6 0 5 0 4 0 3 0 2 pmc42 1 pmc41 0 pmc40 7 0 pfc4 6 0 5 0 4 0 3 0 2 pfc42 1 pfc41 0 pfc40 after reset: 00h r/w address: fffff448h after reset: 00h r/w address: fffff478h pfc4n pmc4n operation mode 0 0 port i/o mode 0 1 csi00 mode 1 0 port i/o mode 1 1 uart2 mode remark n = 0, 1 chapter 16 asynchronous serial interface (uart) preliminary user?s manual u17702ej1v0ud 491 16.1.2 selecting uart2 or i 2 c1 mode uart2 and i 2 c1 of the v850es/kj2 share pins; therefore, these interf aces cannot be used at the same time. use of uart2 needs to be set in advance by us ing the pmc8 and pfc8 registers (refer to 4.3.8 port 8 ). cautions 1. uart2 or i 2 c1 transmission/reception operations are not guaranteed if the mode is changed during transmission or reception. be sure to disable the operation of the unit that is not used. 2. when using pins 59 and 60 as the rxd2 and txd2 pins of uart2, do not set pins 22 and 23 as the rxd2 and txd2 pins. figure 16-2. selecting mode of uart2 or i 2 c1 7 0 pmc8 6 0 5 0 4 0 3 0 2 0 1 pmc81 0 pmc80 7 0 pfc8 6 0 5 0 4 0 3 0 2 0 1 pfc81 0 pfc80 after reset: 00h r/w address: fffff450h after reset: 00h r/w address: fffff470h pfc8n pmc8n operation mode 0 0 port i/o mode 0 1 uart2 mode 1 0 port i/o mode 1 1 i 2 c1 mode remark n = 0, 1 chapter 16 asynchronous serial interface (uart) preliminary user?s manual u17702ej1v0ud 492 16.2 features ? maximum transfer speed: 312.5 kbps ? full-duplex communications on-chip rxbn register on-chip txbn register ? two-pin configuration note txdn: transmit data output pin rxdn: receive data input pin ? reception error detection functions ? parity error ? framing error ? overrun error ? interrupt sources: 3 types ? reception error interrupt request signal (intsren): interrupt is generated according to the logical or of the three types of reception errors ? reception completion interrupt request signal (int srn): interrupt is generated when receive data is transferred from the receive shift register to the rxbn register after serial transfer is completed during a reception enabled state ? transmission completion interrupt request signal (intstn): interrupt is generated when the serial transmission of transmit data (8 or 7 bits) from the transmit shift register is completed ? character length: 7 or 8 bits ? parity functions: odd, even, 0, or none ? transmission stop bits: 1 or 2 bits ? on-chip dedicated baud rate generator note the asck0 pin (external clock i nput) is available only for uart0. chapter 16 asynchronous serial interface (uart) preliminary user?s manual u17702ej1v0ud 493 16.3 configuration table 16-1. configuration of uartn item configuration registers receive buffer register n (rxbn) transmit buffer register n (txbn) receive shift register transmit shift register asynchronous serial interface mode register n (asimm) asynchronous serial interface status register n (asisn) asynchronous serial interface tran smit status register n (asifn) other reception control parity check addition of transmissi on control parity remark n = 0 to 2 figure 16-3 shows the configuration of uartn. (1) asynchronous serial interfa ce mode register n (asimn) the asimn register is an 8-bit register for specifying the operation of uartn. (2) asynchronous serial interfa ce status register n (asisn) the asisn register consists of a set of flags that indicate the erro r contents when a reception error occurs. the various reception error flags are set (1) when a reception error occurs and are cleared (0) when the asisn register is read. (3) asynchronous serial interface tran smit status register n (asifn) the asifn register is an 8-bit regist er that indicates the status when a transmit operation is performed. this register consists of a transmit buffer data flag, which indicates the hol d status of the t xbn register data, and the transmit shift register data flag, which indicates whether transmission is in progress. (4) reception control parity check the receive operation is controlled according to the c ontents set in the asimn register. a check for parity errors is also performed during a re ceive operation, and if an error is detected, a value corresponding to the error contents is set in the asisn register. (5) receive shift register this is a shift register that converts the serial data t hat was input to the rxdn pin to parallel data. one byte of data is received, and if a stop bi t is detected, the receive data is transferred to the rxbn register. this register cannot be directly manipulated. (6) receive buffer register n (rxbn) the rxbn register is an 8-bit buffer register for holdi ng receive data. when 7 characters are received, 0 is stored in the msb. during a reception enabled state, re ceive data is transferred from the re ceive shift register to the rxbn register, synchronized with the end of t he shift-in processing of one frame. also, the reception completion interrupt request signal (intsrn) is generated by t he transfer of data to the rxbn register. chapter 16 asynchronous serial interface (uart) preliminary user?s manual u17702ej1v0ud 494 (7) transmit shift register this is a shift register that converts the parallel data that was transferred from the txbn register to serial data. when one byte of data is transferred fr om the txbn register, the shift regi ster data is output from the txdn pin. the transmission completion interrupt request signal (int stn) is generated synchronized with the completion of transmission of one frame. this register cannot be directly manipulated. (8) transmit buffer register n (txbn) the txbn register is an 8-bit buffer for transmit data. a transmit operation is star ted by writing transmit data to the txbn register. (9) addition of transmission control parity a transmit operation is controlled by adding a start bit, par ity bit, or stop bit to the data that is written to the txbn register, according to the contents that were set in the asimn register. figure 16-3. block diagram of uartn parity framing overrun internal bus asynchronous serial interface mode register n (asimn) receive buffer register n (rxbn) receive shift register reception control parity check transmit buffer register n (txbn) transmit shift register addition of transmission control parity baud rate generator n intsren intsrn intstn rxdn txdn remark for the configuration of the baud rate generator, refer to figure 16-14 . chapter 16 asynchronous serial interface (uart) preliminary user?s manual u17702ej1v0ud 495 16.4 registers (1) asynchronous serial interfa ce mode register n (asimn) the asimn register is an 8-bit register t hat controls the uartn transfer operation. this register can be read or written in 8-bit or 1-bit units. reset sets this register to 01h. cautions 1. when using uartn, be sure to set th e external pins related to uartn functions to the control made before setting the cksrn and brgcn registers, and then set the uarten bit to 1. then set the other bits. 2. set the uarten and rxen bits to 1 while a high level is input to the rxdn pin. if these bits are set to 1 while a low level is input to the rxdn pin, reception will be started. (1/2) <7> uarten asimn (n = 0 to 2) <6> txen <5> rxen 4 psn1 3 psn0 2 cln 1 sln 0 isrmn after reset: 01h r/w address: asim0 fffffa00h, asim1 fffffa10h, asim2 fffffa20h uarten control of operating clock 0 stop clock supply to uartn. 1 supply clock to uartn. ? if the uarten bit is cleared to 0, uartn is asynchronously reset note . ? if the uarten bit = 0, uartn is reset. to operate uartn, first set the uarten bit to 1. ? if the uarten bit is cleared from 1 to 0, all the register s of uartn are initialized. to set the uarten bit to 1 again, be sure to re-set the registers of uartn. the output of the txdn pin goes high when transmission is disabled, regardless of the setting of the uarten bit. txen transmission enable/disable 0 disable transmission 1 enable transmission ? set the txen bit to 1 after setting the uarten bit to 1 at startup. clear the uarten bit to 0 after clearing the txen bit to 0 to stop. ? to initialize the transmission unit, clear (0) the txen bi t, and after letting 2 clock cycles (base clock) elapse, set (1) the txen bit again. if the txen bit is not set again, initialization may not be successful. (for details about the base clock, refer to 16.7.1 (1) base clock .) note the asisn, asifn, and rxbn registers are reset. chapter 16 asynchronous serial interface (uart) preliminary user?s manual u17702ej1v0ud 496 (2/2) rxen reception enable/disable 0 disable reception note 1 enable reception ? set the rxen bit to 1 after setting the uarten bit to 1 at startup. clear the uarten bit to 0 after clearing the rxen bit to 0 to stop. ? to initialize the reception unit status, clear (0) the r xen bit, and after letting 2 clock cycles (base clock) elapse, set (1) the rxen bit again. if the rxen bit is not set agai n, initialization may not be successful. (for details about the base clock, refer to 16.7.1 (1) base clock .) psn1 psn0 transmit operation receive operation 0 0 don?t output parity bit receive with no parity 0 1 output 0 parity receive as 0 parity 1 0 output odd parity judge as odd parity 1 1 output even parity judge as even parity ? to overwrite the psn1 and psn0 bits, fi rst clear (0) the txen and rxen bits. ? if ?0 parity? is selected for reception, no parity judgment is performed. therefore, no error interrupt is generated because the asisn.pen bit is not set. cln specification of character length of 1 frame of transmit/receive data 0 7 bits 1 8 bits ? to overwrite the cln bit, first clear (0) the txen and rxen bits. sln specification of stop bit length of transmit data 0 1 bit 1 2 bits ? to overwrite the sln bit, first clear (0) the txen bit. ? since reception is always done with a stop bit length of 1, the sln bit setting does not affect receive operations. isrmn enable/disable of generation of reception completi on interrupt request signals when an error occurs 0 generate a reception error interrupt request signal (intsren) as an interrupt when an error occurs. in this case, no reception completion interr upt request signal (intsrn) is generated. 1 generate a reception completion interrupt request si gnal (intsrn) as an interrupt when an error occurs. in this case, no reception error interrupt request signal (intsren) is generated. ? to overwrite the isrmn bit, first clear (0) the rxen bit. note when reception is disabled, the receive shift r egister does not detect a start bit. no shift-in processing or transfer processing to the rxbn regist er is performed, and t he contents of the rxbn register are retained. when reception is enabled, the receive shift operat ion starts, synchronized with the detection of the start bit, and when the reception of one frame is completed, the contents of the receive shift register are transferred to the rxbn register. a reception completion interrupt request signal (intsrn) is also generated in synchronizati on with the transfer to the rxbn register. chapter 16 asynchronous serial interface (uart) preliminary user?s manual u17702ej1v0ud 497 (2) asynchronous serial interfa ce status register n (asisn) the asisn register, which consists of 3 error flag bits (pen, fen and oven), indicates the error status when uartn reception is complete. the asisn register is cleared to 00h by a read operation. when a recept ion error occurs, the rxbn register should be read and the error flag should be cl eared after the asisn register is read. this register is read-only in 8-bit units. reset sets this register to 00h. cautions 1. when the asimn.uarten bit or asimn. rxen bit is cleared to 0, or when the asisn register is read, the pen, fen, and oven bits are cleared (0). 2. operation using a bit manipula tion instruction is prohibited. 3. when the main clock is stopped and th e cpu is operating on the subclock, do not access the asisn register. for details, refer to 3.4.8 (1) (b). 7 0 asisn (n = 0 to 2) 6 0 5 0 4 0 3 0 2 pen 1 fen 0 oven after reset: 00h r address: asis0 fffffa03h, asis1 fffffa13h, asis2 fffffa23h pen status flag indicating a parity error 0 when the uarten or rxen bit is cleared to 0, or after the asisn register has been read 1 when reception was completed, the receive data parity did not match the parity bit ? the operation of the pen bit differs according to the settings of the asimn.psn1 and asimn.psn0 bits. fen status flag indicating framing error 0 when the uarten or rxen bit is cleared to 0, or after the asisn register has been read 1 when reception was completed, no stop bit was detected ? for receive data stop bits, only the first bit is checked regardless of the stop bit length. oven status flag indicating an overrun error 0 when the uarten or rxen bit is cleared to 0, or after the asisn register has been read. 1 uartn completed the next receive operation bef ore reading receive data of the rxbn register. ? when an overrun error occurs, the next receive data value is not written to the rxbn register and the data is discarded. chapter 16 asynchronous serial interface (uart) preliminary user?s manual u17702ej1v0ud 498 (3) asynchronous serial interface tran smit status register n (asifn) the asifn register, which consists of 2 status flag bits, indicates the status during transmission. by writing the next data to the txbn register after data is transferred from the txbn register to the transmit shift register, transmit operations can be performed conti nuously without suspension even during an interrupt interval. when transmission is performed continuously, data should be written afte r referencing the txbfn bit to prevent writing to the txbn register by mistake. this register is read-only in 8-bit or 1-bit units. reset sets this register to 00h. 7 0 asifn (n = 0 to 2) 6 0 5 0 4 0 3 0 2 0 <1> txbfn <0> txsfn after reset: 00h r address: asif0 fffffa05h, asif1 fffffa15h, asif2 fffffa25h txbfn transmission buffer data flag 0 data to be transferred next to txbn register does not exist (when the asimn.uarten or asimn.txen bit is cleared to 0, or when data has been transf erred to the transmis sion shift register) 1 data to be transferred next exists in txbn register (d ata exists in txbn register when the txbn register has been written to) ? when transmission is performed continuousl y, data should be written to the txbn register after confirming that this flag is 0. if writing to txbn register is performed when this flag is 1, transmit data cannot be guaranteed. txsfn transmit shift register data flag (indi cates the transmission status of uartn) 0 initial status or a waiting transmi ssion (when the uarten or txen bit is cleared to 0, or when following transmission completion, the next data transfer fr om the txbn register is not performed) 1 transmission in progress (when data has been transferred from the txbn register) ? when the transmission unit is initializ ed, initialization should be executed a fter confirming that this flag is 0 following the occurrence of a transmission completion inte rrupt request signal (intstn). if initialization is performed when this flag is 1, transmit data cannot be guaranteed. chapter 16 asynchronous serial interface (uart) preliminary user?s manual u17702ej1v0ud 499 (4) receive buffer register n (rxbn) the rxbn register is an 8-bit buffer register for stor ing parallel data that had been converted by the receive shift register. when reception is enabled (asimn.rxen bit = 1), receive da ta is transferred from the receive shift register to the rxbn register, synchronized with the completion of th e shift-in processing of one frame. also, a reception completion interrupt request signal (intsrn) is gener ated by the transfer to the rxbn register. for information about the timing for generat ing this interrupt request, refer to 16.6.4 receive operation . if reception is disabled (asimn.rxen bit = 0), the contents of the rxbn register are retained, and no processing is performed for transferring data to the r xbn register even when the shift-in processing of one frame is completed. also, the intsrn signal is not generated. when 7 bits is specified for the data length, bits 6 to 0 of the rxbn register are transferred for the receive data and the msb (bit 7) is always 0. however, if an overrun error (asisn.oven bit = 1) occurs, the receive data at that time is not trans ferred to the rxbn register. the rxbn register becomes ffh when a reset is input or asimn.uarten bit = 0. this register is read-only in 8-bit units. 7 rxbn7 rxbn (n = 0 to 2) 6 rxbn6 5 rxbn5 4 rxbn4 3 rxbn3 2 rxbn2 1 rxbn1 0 rxbn0 after reset: ffh r address: rxb0 fffffa02h, rxb1 fffffa12h, rxb2 fffffa22h chapter 16 asynchronous serial interface (uart) preliminary user?s manual u17702ej1v0ud 500 (5) transmit buffer register n (txbn) the txbn register is an 8-bit buffe r register for setting transmit data. when transmission is enabled (asimn.txen bit = 1), the tr ansmit operation is started by writing data to txbn register. when transmission is disabled (txen bit = 0), even if dat a is written to txbn register, the value is ignored. the txbn register data is transferr ed to the transmit shift register, and a transmission completion interrupt request signal (intstn) is generated, synchronized wit h the completion of the transmission of one frame from the transmit shift register. for information about t he timing for generating this interrupt request, refer to 16.6.2 transmit operation . when asifn.txbfn bit = 1, writing must not be performed to txbn register. this register can be read or written in 8-bit units. reset sets this register to ffh. 7 txbn7 txbn (n = 0 to 2) 6 txbn6 5 txbn5 4 txbn4 3 txbn3 2 txbn2 1 txbn1 0 txbn0 after reset: ffh r/w address: txb0 fffffa04h, txb1 fffffa14h, txb2 fffffa24h chapter 16 asynchronous serial interface (uart) preliminary user?s manual u17702ej1v0ud 501 16.5 interrupt requests the following three types of interrupt re quest signals are generated from uartn. ? reception error interrupt request signal (intsren) ? reception completion interrupt request signal (intsrn) ? transmission completion interrupt request signal (intstn) the default priorities among these three types of interrupt request signals are, from high to low, reception error interrupt, reception completion interrup t, and transmission completion interrupt. table 16-2. generated interrupt re quest signals and default priorities interrupt request signal priority reception error interrupt request signal (intsren) 1 reception completion interrupt request signal (intsrn) 2 transmission completion interrupt request signal (intstn) 3 (1) reception error interrupt request signal (intsren) when reception is enabled, the intsren signal is generated according to the logical or of the three types of reception errors explained for the asisn register. whether the intsren signal or the intsrn signal is generated when an error occurs can be specified according to the asimn.isrmn bit. when reception is disabled, the intsren signal is not generated. (2) reception completion interr upt request signal (intsrn) when reception is enabled, the intsrn signal is generated when data is shifted in to the receive shift register and transferred to the rxbn register. the intsrn signal can be generated in place of the intsren signal according to the asimn.isrmn bit even when a reception error has occurred. when reception is disabled, the intsrn signal is not generated. (3) transmission completion inte rrupt request signal (intstn) the intstn signal is generated when one frame of transmit data containing 7-bit or 8-bit characters is shifted out from the transmit shift register. chapter 16 asynchronous serial interface (uart) preliminary user?s manual u17702ej1v0ud 502 16.6 operation 16.6.1 data format full-duplex serial data transmission and reception can be performed. the transmit/receive data format consists of one data fr ame containing a start bit, character bits, a parity bit, and stop bits as shown in figure 16-4. the character bit length within one data frame, the type of parity, and the stop bit length are specified according to the asimn register. also, data is transferred lsb first. figure 16-4. format of uartn transmit/receive data 1 data frame start bit d0 d1 d2 d3 d4 d5 d6 d7 parity bit stop bits character bits ? start bit 1 bit ? character bits 7 bits or 8 bits ? parity bit even parity, odd parity, 0 parity, or no parity ? stop bits 1 bit or 2 bits chapter 16 asynchronous serial interface (uart) preliminary user?s manual u17702ej1v0ud 503 16.6.2 transmit operation when the asimn.uarten bit is set to 1, a hi gh level is output from the txdn pin. then, when the asimn.txen bit is set to 1, transmission is enabled, and the transmit operat ion is started by writing transmit data to the txbn register. (1) transmission enabled state this state is set by the txen bit. ? txen bit = 1: transmission enabled state ? txen bit = 0: transmission disabled state since uartn does not have a cts (tr ansmission enabled signal) input pin, a port should be used to confirm whether the destination is in a reception enabled state. (2) starting a transmit operation in the transmission enabled state, a trans mit operation is started by writing tr ansmit data to the txbn register. when a transmit operation is star ted, the data in the txbn register is tr ansferred to the transmit shift register. then, the transmit shift register out puts data to the txdn pin (the transmit data is transferred sequentially starting with the start bit). the start bit, parity bit, and stop bits are added automatically. (3) transmission interrupt when the transmit shift register bec omes empty, a transmission completion interrupt request signal (intstn) is generated. the timing for generating the intstn signa l differs according to the specification of the stop bit length. the intstn signal is generated at the same time that the last stop bit is output. if the data to be transmitted next has not been written to the txbn register, the transmit operation is suspended. caution normally, when the transmit shift register becomes empty, the intstn signal is generated. however, the intstn signal is not generated if the transmit shift register becomes empty due to reset. chapter 16 asynchronous serial interface (uart) preliminary user?s manual u17702ej1v0ud 504 figure 16-5. uartn transmission completion interrupt timing start stop d0 d1 d2 d6 d7 parity parity txdn (output) intstn (output) start d0 d1 d2 d6 d7 txdn (output) intstn (output) (a) stop bit length: 1 (b) stop bit length: 2 stop chapter 16 asynchronous serial interface (uart) preliminary user?s manual u17702ej1v0ud 505 16.6.3 continuous transmission operation uartn can write the next transmit data to the txbn register at the timing t hat the transmit shift register starts the shift operation. this enables an efficient transmission rate to be realized by continuously transmitting data even during the transmission completion interrupt service after th e transmission of one data frame. in addition, reading the asifn.txsfn bit after the occurrence of a transmission co mpletion interrupt request si gnal (intstn) enables the txbn register to be efficiently written twice (2 byte s) without waiting for the tr ansmission of 1 data frame. when continuous transmission is perform ed, data should be written after referenc ing the asifn register to confirm the transmission status and whether or not da ta can be written to the txbn register. caution the values of the asif.txbfn and asif .txsfn bits change 10 11 01 in continuous transmission. therefore, do not confirm the status based on the combination of the txbfn and txsfn bits. read only the txbfn bit during continuous transmission. txbfn whether or not writing to txbn register is enabled 0 writing is enabled 1 writing is not enabled caution when transmission is perfo rmed continuously, write the first tr ansmit data (first byte) to the txbn register and confirm that the txbfn bit is 0, and then write the next transmit data (second byte) to txbn register. if writing to the txbn register is performed when the txbfn bit is 1, transmit data cannot be guaranteed. the communication status can be confir med by referring to the txsfn bit. txsfn transmission status 0 transmission is completed. 1 under transmission. cautions 1. when initializing the transmission unit wh en continuous transmissi on is completed, confirm that the txsfn bit is 0 afte r the occurrence of the transmission completion interrupt, and then execute initialization. if in itialization is performed when the txsfn bit is 1, transmit data cannot be guaranteed. 2. while transmission is being performed contin uously, an overrun error may occur if the next transmission is completed befo re the intstn interrupt servicing following the transmission of 1 data frame is executed. an overrun error can be detected by embedding a program that can count the number of transmit data and referenc ing txsfn bit. chapter 16 asynchronous serial interface (uart) preliminary user?s manual u17702ej1v0ud 506 figure 16-6. continuous transmission processing flow set registers interrupt occurrence wait for interrupt required number of transfers performed? write transmit data to txbn register write second byte transmit data to txbn register write transmit data to txbn register when reading asifn register, txbfn = 0? when reading asifn register, txsfn = 1? when reading asifn register, txsfn = 0? no no no no yes yes yes yes end of transmission processing chapter 16 asynchronous serial interface (uart) preliminary user?s manual u17702ej1v0ud 507 (1) starting procedure the procedure to start continuous transmission is shown below. figure 16-7. continuous tr ansmission starting procedure txdn (output) data (1) data (2) <5> <1> <2> <4> intstn (output) txbn register ffh ffh data (1) data (2) data (3) data (1) data (2) data (3) <3> asifn register (txbfn, txsfn bits) 00 11 note 11 01 01 11 01 11 txsn register start bit stop bit stop bit start bit 10 note refer to 16.8 cautions (2) . asifn register transmission starting procedure internal operation txbfn txsfn ? set transmission mode <1> start transmission unit 0 0 ? write data (1) 1 0 <2> generate start bit ? read asifn register (confirm that txbfn bit = 0) start data (1) transmission 1 0 0 0 1 note 1 1 1 ? write data (2) < chapter 16 asynchronous serial interface (uart) preliminary user?s manual u17702ej1v0ud 508 (2) ending procedure the procedure for ending continuous transmission is shown below. figure 16-8. continuous transmission end procedure txdn (output) data (m ? 1) data (m) <11> <7> <6> <8> <10> intstn (output) txbn register data (m ? 1) data (m ? 1) data (m) ffh data (m) <9> asifn register (txbfn, txsfn bits) uarten bit or txen bit 11 01 11 01 00 txsn register start bit start bit stop bit stop bit asifn register transmission end procedure internal operation txbfn txsfn <6> transmission of data (m ? 2) is in progress 1 1 <7> intstn interrupt occurs ? read asifn register (confirm that txbfn bit = 0) 0 0 1 1 ? write data (m) <8> generate start bit start data (m ? 1) transmission < chapter 16 asynchronous serial interface (uart) preliminary user?s manual u17702ej1v0ud 509 16.6.4 receive operation the awaiting reception state is set by setting the asimn.uar ten bit to 1 and then setting the asimn.rxen bit to 1. to start the receive operatio n, start sampling at the fallin g edge when the falling of the rxdn pin is detected. if the rxdn pin is low level at a start bit sampling point, the st art bit is recognized. when the receive operation begins, serial data is stored sequentially in the receive shift regi ster according to the baud rate that was set. a reception completion interrupt request signal (intsrn) is generated each time the reception of one frame of data is completed. normally, the receive data is transferred from the rxbn register to memory by th is interrupt servicing. (1) reception enabled state the receive operation is set to the reception enabled state by setting the rxen bit to 1. ? rxen bit = 1: reception enabled state ? rxen bit = 0: reception disabled state in receive disabled state, the reception hardware stands by in the initial stat e. at this time, the contents of the rxbn register are retained, and no reception completion interrupt or reception error interrupt is generated. (2) starting a receive operation a receive operation is started by the detection of a start bit. the rxdn pin is sampled using the serial clock from baud rate generator n (brgn). (3) reception completion interrupt when the rxen bit = 1 and the reception of one frame of data is completed (the stop bit is detected), the intsrn signal is generated and the receive data within t he receive shift register is transferred to the rxbn register at the same time. also, if an overrun error (asisn.oven bit = 1) occurs, t he receive data at that time is not transferred to the rxbn register, and either the intsrn signal or a re ception error interrupt request signal (intsren) is generated according to the asimn.isrmn bit setting. even if a parity error (asisn.pen bit = 1) or framing error (asisn.fen bit = 1) occurs during a reception operation, the receive operation contin ues until stop bit is received, and after reception is completed, either the intsrn signal or the intsren signal is generated according to the isrmn bit setting (the receive data within the receive shift register is transferred to the rxbn register). if the rxen bit is cleared (0) during a receive operation, the receive operation is immediately stopped. the contents of the rxbn register and the asisn register at this time do not change, and the intsrn signal or the intsren signal is not generated. the intsrn signal or the intsren signal is not gener ated when the rxen bit = 0 (reception is disabled). chapter 16 asynchronous serial interface (uart) preliminary user?s manual u17702ej1v0ud 510 figure 16-9. uartn reception completion inte rrupt timing start d0 d1 d2 d6 d7 rxdn (input) intsrn (output) rxbn register parity stop cautions 1. be sure to read th e rxbn register even when a recept ion error occurs. if the rxbn register is not read, an overrun error wil l occur at the next data reception and the reception error status will continue infinitely. 2. reception is always performed assuming a stop bit length of 1. a second stop bit is ignored. 16.6.5 reception error the three types of errors that can occur during a receive operation are a parity error, framing error, and overrun error. as a result of data reception, the various flags of the asisn register ar e set (1), and a reception error interrupt request signal (intsren) or a reception completion interrupt request signal (intsrn) is generated at the same time. the asimn.isrmn bit specifies whether the intsren signal or the intsrn signal is generated. the type of error that occurred during reception can be de tected by reading the conten ts of the asisn register during the intsren or intsrn interrupt servicing. the contents of the asisn r egister are cleared (0) by reading the asisn register. table 16-3. reception error causes error flag reception error cause pen parity error the parity specificat ion during transmission did not match the parity of the reception data fen framing error no stop bit was detected oven overrun error the reception of the next data was completed before data was read from the rxbn register chapter 16 asynchronous serial interface (uart) preliminary user?s manual u17702ej1v0ud 511 (1) separation of reception e rror interrupt request signal a reception error interrupt request signal can be separ ated from the intsrn signal and generated as the intsren signal by clearing the isrmn bit to 0. figure 16-10. when reception error inte rrupt request signal is separated from intsrn signal (isrmn bit = 0) (a) no error occurs during reception (b) an e rror occurs during reception intsrn signal (reception completion interrupt) intsren signal (reception error interrupt) intsrn signal (reception completion interrupt) intsren signal (reception error interrupt) intsrn does not occur figure 16-11. when reception error in terrupt request signal is included in intsrn signal (isrmn bit = 1) (a) no error occurs during reception (b) an erro r occurs during reception intsrn signal (reception completion interrupt) intsren signal (reception error interrupt) intsrn signal (reception completion interrupt) intsren signal (reception error interrupt) intsren does not occur chapter 16 asynchronous serial interface (uart) preliminary user?s manual u17702ej1v0ud 512 16.6.6 parity types and corresponding operation a parity bit is used to detect a bit error in communication da ta. normally, the same type of parity bit is used on the transmission and reception sides. (1) even parity (i) during transmission the parity bit is controlled so t hat the number of bits with the valu e ?1? within the transmit data including the parity bit is even. the parity bit value is as follows. ? if the number of bits with the value ?1? within the transmit data is odd: 1 ? if the number of bits with the value ?1? within the transmit data is even: 0 (ii) during reception the number of bits with the value ?1? within the receive data includi ng the parity bit is counted, and a parity error is generated if this number is odd. (2) odd parity (i) during transmission in contrast to even parity, the parity bit is controlled so that the number of bits with the value ?1? within the transmit data including the parity bit is odd. the parity bit value is as follows. ? if the number of bits with the value ?1? within the transmit data is odd: 0 ? if the number of bits with the value ?1? within the transmit data is even: 1 (ii) during reception the number of bits with the value ?1? within the receive data includi ng the parity bit is counted, and a parity error is generated if this number is even. (3) 0 parity during transmission the parity bit is set to ?0? regardless of the transmit data. during reception, no parity bit check is performed. therefore, no parity error is generated regardless of whether the parity bit is ?0? or ?1?. (4) no parity no parity bit is added to the transmit data. during reception, the receive operation is performed as if there were no par ity bit. since there is no parity bit, no parity error is generated. chapter 16 asynchronous serial interface (uart) preliminary user?s manual u17702ej1v0ud 513 16.6.7 receive data noise filter the rxdn signal is sampled at the risi ng edge of the prescaler output base clock (f uclk ). if the same sampling value is obtained twice, the ma tch detector output changes, and this output is sampled as input data. therefore, data not exceeding one clock width is judged to be noise and is not delivered to the internal circuit (refer to figure 16-13 ). refer to 16.7.1 (1) base clock regarding the base clock. also, since the circuit is configured as shown in figure 16-12, internal processing during a receive operation is delayed by up to 2 clocks accordin g to the external signal status. figure 16-12. noise filter circuit rxdn q base clock in ld_en q in internal signal a internal signal b match detector f uclk figure 16-13. timing of rx dn signal judg ed as noise internal signal a base clock rxdn (input) internal signal b match mismatch (judged as noise) mismatch (judged as noise) match chapter 16 asynchronous serial interface (uart) preliminary user?s manual u17702ej1v0ud 514 16.7 dedicated baud rate generator n (brgn) a dedicated baud rate generator, which consists of a s ource clock selector and an 8-bit programmable counter, generates serial clocks during transmission/reception by uartn. the dedicated baud ra te generator output can be selected as the serial clock for each channel. separate 8-bit counters exist fo r transmission and for reception. 16.7.1 baud rate generator n (brgn) configuration figure 16-14. configuration of baud rate generator n (brgn) f xx /2 f xx /4 f xx /8 f xx /16 f xx /32 f xx /64 f xx /128 f xx /256 f xx /512 f xx /1,024 asck0 note 2 f uclk note 1 selector uarten 8-bit counter match detector baud rate brgcn: mdln7 to mdln0 1/2 uarten and txen bits (or rxen bit) cksrn: tpsn3 to tpsn0 f xx notes 1. set f uclk so as to satisfy the following conditions. ? v dd = regc = 4.5 to 5.5 v: f uclk 12 mhz ? v dd = 4.0 to 5.5 v, regc = 10 f: f uclk 6 mhz ? v dd = regc = 2.7 to 4.5 v: f uclk 6 mhz 2. asck0 pin input can be used only by uart0. remark f xx : main clock frequency f uclk : base clock (1) base clock when the asimn.uarten bit = 1, the clock selected a ccording to the cksrn.tpsn3 to cksrn.tpsn0 bits is supplied to the transmission/reception uni t. this clock is called the base clock (f uclk ). when the uarten bit = 0, f uclk is fixed to low level. chapter 16 asynchronous serial interface (uart) preliminary user?s manual u17702ej1v0ud 515 16.7.2 serial clock generation a serial clock can be generated according to the settings of the cksrn and brgcn registers. the base clock to the 8-bit counter is select ed by the cksrn.tpsn3 to cksrn.tpsn0 bits. the 8-bit counter divisor value can be set by the brgcn.mdln7 to brgcn.mdln0 bits. (1) clock select register n (cksrn) the cksrn register is an 8-bit regist er for selecting the basic block us ing the tpsn3 to tpsn0 bits. the clock selected by the tpsn3 to t psn0 bits becomes the base clock (f uclk ) of the transmission/reception module. this register can be read or written in 8-bit units. reset sets this register to 00h. caution clear the asimn.uarten bit to 0 before rewriti ng the tpsn3 to tpsn0 bits. 7 0 cksrn (n = 0 to 2) 6 0 5 0 4 0 3 tpsn3 2 tpsn2 1 tpsn1 0 tpsn0 after reset: 00h r/w address: cksr0 fffffa06h, cksr1 fffffa16h, cksr2 fffffa26h tpsn3 tpsn2 tpsn1 tpsn0 base clock (f uclk ) note 1 0 0 0 0 f xx 0 0 0 1 f xx /2 0 0 1 0 f xx /4 0 0 1 1 f xx /8 0 1 0 0 f xx /16 0 1 0 1 f xx /32 0 1 1 0 f xx /64 0 1 1 1 f xx /128 1 0 0 0 f xx /256 1 0 0 1 f xx /512 1 0 1 0 f xx /1,024 1 0 1 1 external clock note 2 (asck0 pin) other than above setting prohibited notes 1. set f uclk so as to satisfy the following conditions. ? regc = v dd = 4.5 to 5.5 v: f uclk 12 mhz ? regc = 10 f, v dd = 4.0 to 5.5 v: f uclk 6 mhz ? regc = v dd = 2.7 to 4.5 v: f uclk 6 mhz 2. asck0 pin input clock can be used only by uart0. setting of uart1 and uart2 is prohibited. remark f xx : main clock frequency chapter 16 asynchronous serial interface (uart) preliminary user?s manual u17702ej1v0ud 516 (2) baud rate generator c ontrol register n (brgcn) the brgcn register is an 8-bit regist er that controls the baud rate (serial transfer speed) of uartn. this register can be read or written in 8-bit units. reset sets this register to ffh. caution if the mdln7 to mdln0 bits are to be o verwritten, the asimn.txen and asimn.rxen bits should be cleared to 0 first. 7 mdln7 brgcn (n = 0 to 2) 6 mdln6 5 mdln5 4 mdln4 3 mdln3 2 mdln2 1 mdln1 0 mdln0 after reset: ffh r/w address: brgc0 fffffa07h, brgc1 fffffa17h, brgc2 fffffa27h mdln7 mdln6 mdln5 mdln4 mdln3 mdln2 mdln1 mdln0 set value (k) serial clock 0 0 0 0 0 ? setting prohibited 0 0 0 0 1 0 0 0 8 f uclk /8 0 0 0 0 1 0 0 1 9 f uclk /9 0 0 0 0 1 0 1 0 10 f uclk /10 1 1 1 1 1 0 1 0 250 f uclk /250 1 1 1 1 1 0 1 1 251 f uclk /251 1 1 1 1 1 1 0 0 252 f uclk /252 1 1 1 1 1 1 0 1 253 f uclk /253 1 1 1 1 1 1 1 0 254 f uclk /254 1 1 1 1 1 1 1 1 255 f uclk /255 remarks 1. f uclk : frequency [hz] of base clock selected by cksr0.tpsn3 to cksr0.tpsn0 bits 2. k: value set by mdln7 to mdln0 bits (k = 8, 9, 10, ..., 255) 3. the baud rate is the output clock fo r the 8-bit counter divided by 2. 4. : don?t care chapter 16 asynchronous serial interface (uart) preliminary user?s manual u17702ej1v0ud 517 (3) baud rate the baud rate is the value obtained by the following formula. baud rate [bps] = f uclk = frequency [hz] of base clock selected by cksrn.tpsn3 to cksrn.tpsn0 bits. k = value set by brgcn.mdln7 to brgcn. mdln0 bits (k = 8, 9, 10, ..., 255) (4) baud rate error the baud rate error is obtained by the following formula. error (%) = ? 1 100 [%] cautions 1. make sure that the baud rate erro r during transmission does not exceed the allowable error of the reception destination. 2. make sure that the baud rate error durin g reception is within the allowable baud rate range during reception, which is described in 16.7.4 allowable baud rate range during reception. example: base clock frequency = 10 mhz = 10,000,000 hz setting of brgcn.mdln7 to brgcn.mdln0 bits = 00100001b (k = 33) target baud rate = 153,600 bps baud rate = 10,000,000/(2 33) = 151,515 [bps] error = (151,515/153,600 ? 1) 100 = ? 1.357 [%] f uclk 2 k actual baud rate (baud rate with error) target baud rate (normal baud rate) chapter 16 asynchronous serial interface (uart) preliminary user?s manual u17702ej1v0ud 518 16.7.3 baud rate setting example table 16-4. baud rate generator setting data f xx = 20 mhz f xx = 16 mhz f xx = 10 mhz baud rate (bps) f uclk k err f uclk k err f uclk k err 300 f xx /512 41h (65) 0.16 f xx /1024 1ah (26) 0.16 f xx /256 41h (65) 0.16 600 f xx /256 41h (65) 0.16 f xx /1024 0dh (13) 0.16 f xx /128 41h (65) 0.16 1200 f xx /128 41h (65) 0.16 f xx /512 0dh (13) 0.16 f xx /64 41h (65) 0.16 2400 f xx /64 41h (65) 0.16 f xx /256 0dh (13) 0.16 f xx /32 41h (65) 0.16 4800 f xx /32 41h (65) 0.16 f xx /128 0dh (13) 0.16 f xx /16 41h (65) 0.16 9600 f xx /16 41h (65) 0.16 f xx /64 0dh (13) 0.16 f xx /8 41h (65) 0.16 10400 f xx /64 0fh (15) 0.16 f xx /64 0ch (12) 0.16 f xx /32 0fh (15) 0.16 19200 f xx /8 41h (65) 0.16 f xx /32 0dh (13) 0.16 f xx /4 41h (65) 0.16 24000 f xx /32 0dh (13) 0.16 f xx /2 a7h (167) ? 0.20 f xx /16 0dh (13) 0.16 31250 f xx /32 0ah (10) 0.00 f xx /32 08h (8) 0.00 f xx /16 0ah (10) 0 33600 f xx /2 95h (149) ? 0.13 f xx /2 77h (119) 0.04 f xx 95h (149) ? 0.13 38400 f xx /4 41h (65) 0.16 f xx /16 0dh (13) 0.16 f xx /2 41h (65) 0.16 48000 f xx /16 0dh (13) 0.16 f xx /2 53h (83) 0.40 f xx /8 0dh (13) 0.16 56000 f xx /2 59h (89) 0.32 f xx /2 47h (71) 0.60 f xx 59h (89) 0.32 62500 f xx /16 0ah (10) 0.00 f xx /16 08h (8) 0.00 f xx /8 0ah (10) 0.00 76800 f xx /2 41h (65) 0.16 f xx /8 0dh (13) 0.16 f xx 41h (65) 0.16 115200 f xx /2 2bh (43) 0.94 f xx /2 23h (35) ? 0.79 f xx 2bh (43) 0.94 153600 f xx /2 21h (33) ? 1.36 f xx /4 0dh (13) 0.16 f xx 21h (33) ? 1.36 312500 f xx /4 08h (8) 0 f xx /2 0dh (13) ? 1.54 f xx /2 08h (8) 0.00 caution the allowable fre quency of the base clock (f uclk ) is as follows. ? regc = v dd = 4.5 to 5.5 v: f uclk 12 mhz ? regc = 10 f, v dd = 4.0 to 5.5 v: f uclk 6 mhz ? regc = v dd = 2.7 to 4.5 v: f uclk 6 mhz remark f xx : main clock frequency f uclk : base clock frequency k: set values of brgcn.mdln7 to brgcn.mdln0 bits err: baud rate error [%] n = 0 to 2 chapter 16 asynchronous serial interface (uart) preliminary user?s manual u17702ej1v0ud 519 16.7.4 allowable baud ra te range during reception the degree to which a discrepancy from the transmission des tination?s baud rate is allowed during reception is shown below. caution the equations described belo w should be used to set the ba ud rate error during reception so that it always is within the allowable error range. figure 16-15. allowable baud rate range during reception fl 1 data frame (11 fl) flmin flmax uartn transfer rate latch timing start bit bit 0 bit 1 bit 7 parity bit minimum allowable transfer rate maximum allowable transfer rate stop bit start bit bit 0 bit 1 bit 7 parity bit stop bit start bit bit 0 bit 1 bit 7 parity bit stop bit as shown in figure 16-15, after the start bit is detect ed, the receive data latch timing is determined according to the counter that was set by the brgc n register. if all data up to the final data (stop bit) is in time for this latch timing, the data can be received normally. if this is applied to 11-bit reception, the following is theoretically true. fl = (brate) ?1 brate: uartn baud rate k: brgcn register set value fl: 1-bit data length when the latch timing margin is 2 base clocks, the minimum allowable transfer rate (flmin) is as follows. fl k 2 2 k 21 fl k 2 2 k fl 11 min fl + = ? ? = chapter 16 asynchronous serial interface (uart) preliminary user?s manual u17702ej1v0ud 520 therefore, the transfer destination?s maximum re ceivable baud rate (brmax) is as follows. brmax = (flmin/11) ? 1 = brate similarly, the maximum allowable transfer rate (flmax) can be obtained as follows. fl k 2 2 k 21 fl k 2 2 k fl 11 max fl 11 10 ? = + ? = 11 fl k 20 2 k 21 max fl ? = therefore, the transfer destination?s minimum receivable baud rate (brmin) is as follows. brmin = (flmax/11) ? 1 = brate the allowable baud rate error of uartn and the trans fer destination can be obtained as follows from the expressions described above for computing the minimum and maximum baud rate values. table 16-5. maximum and mini mum allowable baud rate error division ratio (k) maximum allowable baud rate error minimum allowable baud rate error 8 +3.53% ?3.61% 20 +4.26% ?4.31% 50 +4.56% ?4.58% 100 +4.66% ?4.67% 255 +4.72% ?4.73% remarks 1. the reception precision depends on the number of bits in one frame, the base clock frequency, and the division ratio (k). the higher the base clock frequency and the larger the division ratio (k), the higher the precision. 2. k: brgcn register set value 22k 21k + 2 20k 21k ? 2 chapter 16 asynchronous serial interface (uart) preliminary user?s manual u17702ej1v0ud 521 16.7.5 transfer rate duri ng continuous transmission during continuous transmission, the transfer rate from a stop bit to the next start bit is extended two clocks of the base clock longer than normal. however, on the reception si de, the transfer result is not affected since the timing is initialized by the detection of the start bit. figure 16-16. transfer rate during continuous transmission start bit bit 0 bit 1 bit 7 parity bit stop bit fl 1 data frame bit 0 fl fl fl fl fl fl flstp start bit of second byte start bit representing the 1-bit data length by fl, the stop bit length by flstp, and the base clock frequency by f uclk yields the following equation. flstp = fl + 2/f uclk therefore, the transfer rate during continuous transmission is as follows (when the stop bit length = 1). transfer rate = 11 fl + (2/f uclk ) 16.8 cautions cautions to be observed when using uartn are shown below. (1) when the supply of clocks to uart n is stopped (for example, in idle or stop mode), operation stops with each register retaining the value it had immediately before t he supply of clocks was st opped. the txdn pin output also holds and outputs the value it had imm ediately before the supply of clocks was stopped. however, operation is not gua ranteed after the supply of clocks is rest arted. therefore, after the supply of clocks is restarted, the circuits should be initialized by clearing the asimn.uarten, asimn.rxen, and asimn.txen bits to 000. (2) uartn has a 2-stage buffer configurat ion consisting of the txbn regist er and the transmission shift register, and has status flags (asifn.txbfn and as ifn.txsfn bits) that indicate t he status of each buffer. if the txbfn and txsfn bits are read in contin uous transmission, the value changes 10 11 01. for the timing to write the next data to the txbn register, read only the txbfn bit durin g continuous transmission. preliminary user?s manual u17702ej1v0ud 522 chapter 17 clocked serial interface 0 (csi0) in the v850es/kj2, three channels of clocked serial interface 0 (csi0) are provided. 17.1 features ? maximum transfer speed: 5 mbps ? master mode/slave mode selectable ? transmission data length: 8 bits or 16 bits can be set ? msb/lsb-first selectable for transfer data ? eight clock signals can be selected (7 master clocks and 1 slave clock) ? 3-wire type so0n: serial transmit data output si0n: serial receive data input sck0n: serial clock i/o ? interrupt sources: 1 type ? transmission/reception completion inte rrupt request signal (intcsi0n) ? transmission/reception mode or reception-only mode selectable ? two transmission buffer registers (sotbfn/sotbfln, sotbn/sotbln) and two reception buffer registers (sirbn/sirbln, sirben/sirbeln) are provided on chip ? single transfer mode/continuous transfer mode selectable remark n = 0 to 2 chapter 17 clocked serial interface 0 (csi0) preliminary user?s manual u17702ej1v0ud 523 17.2 configuration csi0n is controlled via the csim0n register. (1) clocked serial interface mode register 0n (csim0n) the csim0n register is an 8-bit register t hat specifies the operation of csi0n. (2) clocked serial interface clock selection register n (csicn) the csicn register is an 8-bit register that co ntrols the csi0n serial transfer operation. (3) serial i/o shift register 0n (sio0n) the sio0n register is a 16-bit shift register th at converts parallel data into serial data. the sio0n register is used for bot h transmission and reception. data is shifted in (reception) and shifted ou t (transmission) from the msb or lsb side. the actual transmission/reception operations ar e started up by accessing the buffer register. (4) serial i/o shift register 0nl (sio0nl) the sio0nl register is an 8-bit shift register that converts parallel data into serial data. the sio0nl register is used for both transmission and reception. data is shifted in (reception) and shifted ou t (transmission) from the msb or lsb side. the actual transmission/reception operations ar e started up by access of the buffer register . (5) clocked serial interface recei ve buffer register n (sirbn) the sirbn register is a 16-bit buffer r egister that stores receive data. (6) clocked serial interface recei ve buffer register nl (sirbnl) the sirbnl register is an 8-bit buffer r egister that stores receive data. (7) clocked serial interface read-only r eceive buffer register n (sirben) the sirben register is a 16-bit buffer register that stores receive data. the sirben register is the same as the sirbn register. it is used to read the contents of the sirbn register. (8) clocked serial interface read-only r eceive buffer register nl (sirbenl) the sirbenl register is an 8-bit buffer register that stores receive data. the sirbenl register is the same as the sirbnl register. it is used to read the contents of the sirbnl register. (9) clocked serial interface transm it buffer register n (sotbn) the sotbn register is a 16-bit buffer r egister that stores transmit data. (10) clocked serial interface transm it buffer register nl (sotblnl) the sotbnl register is an 8-bit buffer register that stores transmit data. (11) clocked serial interface initial tr ansmit buffer register n (sotbfn) the sotbfn register is a 16-bit buffer register that st ores the initial transmit data in the continuous transfer mode. chapter 17 clocked serial interface 0 (csi0) preliminary user?s manual u17702ej1v0ud 524 (12) clocked serial interface initial tran smit buffer register nl (sotbfnl) the sotbfnl register is an 8-bit buffe r register that stores initial tran smit data in the continuous transfer mode. (13) selector the selector selects the serial clock to be used. (14) serial clock controller controls the serial clock supply to the shift register. also controls the clock out put to the sck0n pin when the internal clock is used. (15) serial clock counter counts the serial clock output or i nput during transmission/reception, and checks whether 8-bit or 16-bit data transmission/reception has been performed. (16) interrupt controller controls the interrupt request timing. remark n = 0 to 2 chapter 17 clocked serial interface 0 (csi0) preliminary user?s manual u17702ej1v0ud 525 figure 17-1. block diagram of clocked serial interface selector transmission control so selection so latch transmit buffer register (sotbn/sotbnl) receive buffer register (sirbn/sirbnl) shift register (sion/sio0nl) initial transmit buffer register (sotbfn/sotbfnl) interrupt controller clock start/stop control & clock phase control serial clock controller sck0n intcsi0n so0n si0n control signal transmission data control f xx /2 6 f xx /2 5 f xx /2 4 f xx /2 3 f xx /2 2 f xx /2 to50, to51 sck0n remarks 1. n = 0 to 2 2. f xx : main clock chapter 17 clocked serial interface 0 (csi0) preliminary user?s manual u17702ej1v0ud 526 17.3 registers (1) clocked serial interface mode register 0n (csim0n) the csim0n register controls the csi0n operation. this register can be read or written in 8-bit or 1-bit units (however, csotn bit is read-only). after reset, csim0n is cleared to 00h. caution overwriting the csim0n.trmdn, csim 0n.ccln, csim0n.dirn, csim0n.csitn, and csim0n.auton bits can be done only when the cs otn bit = 0. if these bits are overwritten at any other time, the operation cannot be guaranteed. chapter 17 clocked serial interface 0 (csi0) preliminary user?s manual u17702ej1v0ud 527 <7> csi0en csim0n (n = 0 to 2) <6> trmdn 5 ccln <4> dirn 3 csitn 2 auton 1 0 <0> csotn after reset: 00h r/w address: csim00 fffffd00h, csim01 fffffd10h, csim02 fffffd20h csi0en csi0n operation enable/disable 0 disable csi0n operation. 1 enable csi0n operation. the internal csi0n circuit can be reset note asynchronously by clearing the csi0en bit to 0. for the sck0n and so0n pin output status when the csi0en bit = 0, refer to 17.5 output pins . trmdn specification of transmission/reception mode 0 receive-only mode 1 transmission/reception mode when the trmdn bit = 0, reception is performed and the so0n pi n outputs a low level. data reception is started by reading the sirbn register. when the trmdn bit = 1, transmissi on/reception is started by writing data to the sotbn register. ccln specification of data length 0 8 bits 1 16 bits dirn specification of transfer direction mode (msb/lsb) 0 first bit of transfer data is msb 1 first bit of transfer data is lsb csitn control of delay of interrupt request signal 0 no delay 1 delay mode (interrupt request signal is delay ed 1/2 cycle compared to the serial clock) the delay mode (csitn bit = 1) is valid only in the master mode (csicn.cks0n2 to csicn.csk0n0 bits are not 111b). in the slave mode (cks0n2 to cks0n0 bits are 111b), do not set the delay mode. auton specification of single trans fer mode or continuous transfer mode 0 single transfer mode 1 continuous mode csotn communication status flag 0 communication stopped 1 communication in progress the csotn bit is cleared (0) by writing 0 to the csi0en bit. note the csotn bit and the sirbn, sirbnl, sirbe, sirbenl, sion , and sionl registers are reset. chapter 17 clocked serial interface 0 (csi0) preliminary user?s manual u17702ej1v0ud 528 (2) clocked serial interface clock selection register n (csicn) the csicn register is an 8-bit register t hat controls the csi0n transfer operation. this register can be read or written in 8-bit or 1-bit units. after reset, csicn is cleared to 00h. caution the csicn register can be overwri tten only when the csim0n.csi0en bit = 0. 7 0 csicn (n = 0 to 2) 6 0 5 0 4 ckpn 3 dapn 2 cks0n2 1 cks0n1 0 cks0n0 after reset: 00h r/w address: csic0 fffffd01h, csic1 fffffd11h, csic2 fffffd21h ckpn dapn specification of timing of transmitting/receiving data to/from sck0n 0 0 (type 1) do7 do6 do5 do4 do3 do2 do1 do0 di7 so0n (output) sck0n (i/o) si0n (input) di6 di5 di4 di3 di2 di1 di0 0 1 (type 2) do7 do6 do5 do4 do3 do2 do1 do0 di7 di6 di5 di4 di3 di2 di1 di0 so0n (output) sck0n (i/o) si0n (input) 1 0 (type 3) do7 do6 do5 do4 do3 do2 do1 do0 di7 di6 di5 di4 di3 di2 di1 di0 so0n (output) sck0n (i/o) si0n (input) 1 1 (type 4) do7 do6 do5 do4 do3 do2 do1 do0 di7 di6 di5 di4 di3 di2 di1 di0 so0n (output) sck0n (i/o) si0n (input) cks0n2 cks0n1 cks0n0 serial clock note 1 mode 0 0 0 f xx /2 master mode 0 0 1 f xx /2 2 master mode 0 1 0 f xx /2 3 master mode 0 1 1 f xx /2 4 master mode 1 0 0 f xx /2 5 master mode 1 0 1 f xx /2 6 master mode 1 1 0 clock generated by to50, to51 note 2 master mode 1 1 1 external clock (sck0n pin) slave mode notes 1. set the serial clock so as to satisfy the following conditions. ? regc = v dd = 4.0 to 5.5 v: serial clock 5 mhz ? regc = 10 f, v dd = 4.0 to 5.5 v: serial clock 2.5 mhz ? regc = v dd = 2.7 to 4.0 v: serial clock 2.5 mhz 2. csi00: to50 csi01, csi02: to51 remark f xx : main clock frequency chapter 17 clocked serial interface 0 (csi0) preliminary user?s manual u17702ej1v0ud 529 (3) clocked serial interface receive buffe r registers n, nl (sirbn, sirbnl) the sirbn register is a 16-bit buffer r egister that stores receive data. when the receive-only mode is set (csim0n.trmdn bit = 0), the reception operati on is started by reading data from the sirbn register. this register is read-only in 16-bit units. when the lowe r 8 bits are used as the sirbnl register, this register is read-only in 8-bit units. in addition to reset input, this register can also be initialized by clearing (0) the csim0n.csi0en bit. cautions 1. read the sirbn regist er only when a 16-bit data length has been set (csim0n.ccln bit = 1). read the sirbnl register only when an 8-bi t data length has been set (ccln bit = 0). 2. when the single transfer mode has been set (csim0n.aut on bit = 0), perform a read operation only in the idle state (csim0n.csotn bit = 0). if the sirbn or sirbnl register is read during data transfer, th e data cannot be guaranteed. (a) sirbn register 14 sirbn 14 13 sirbn 13 12 sirbn 12 2 sirbn 2 3 sirbn 3 4 sirbn 4 5 sirbn 5 6 sirbn 6 7 sirbn 7 8 sirbn 8 9 sirbn 9 10 sirbn 10 11 sirbn 11 15 sirbn 15 1 sirbn 1 0 sirbn 0 sirbn (n = 0 to 2) after reset: 0000h r address: sirb0 fffffd02h, sirb1 fffffd12h, sirb2 fffffd22h (b) sirbnl register 7 sirbn7 sirbnl (n = 0 to 2) 6 sirbn6 5 sirbn5 4 sirbn4 3 sirbn3 2 sirbn2 1 sirbn1 0 sirbn0 after reset: 00h r address: sirb0l fffffd02h, sirb1l fffffd12h, sirb2l fffffd22h chapter 17 clocked serial interface 0 (csi0) preliminary user?s manual u17702ej1v0ud 530 (4) clocked serial interface read-only receive buffer registers n, nl (sirben, sirbenl) the sirben register is a 16-bit buffer register that stores receive data. the sirben register is the same as the sirbn register. even if the sirben register is read, the next operation will not start. the sirben register is used to read the conten ts of the sirbn register when the serial reception is not continued. this register is read-only in 16-bit units. however, when the lower 8 bits are used as the sirbenl register, the register is read-only in 8-bit units. in addition to reset input, this register can also be initialized by clearing (0) the csim0n.csi0en bit. cautions 1. the receive operation is not started even if data is read from the sirben and sirbenl registers. 2. the sirben register can be read only if a 16-bit data length has been set (csim0n.ccln bit = 1). the sirbenl register can be read only if an 8-bit data length has been set (ccln bit = 0). (a) sirben register 14 sirben 14 13 sirben 13 12 sirben 12 2 sirben 2 3 sirben 3 4 sirben 4 5 sirben 5 6 sirben 6 7 sirben 7 8 sirben 8 9 sirben 9 10 sirben 10 11 sirben 11 15 sirben 15 1 sirben 1 0 sirben 0 sirben (n = 0 to 2) after reset: 0000h r address: sirbe0 fffffd06h, sirbe1 fffffd16h, sirbe2 fffffd26h (b) sirbenl register 7 sirben7 sirbenl (n = 0 to 2) 6 sirben6 5 sirben5 4 sirben4 3 sirben3 2 sirben2 1 sirben1 0 sirben0 after reset: 00h r address: sirbe0l fffffd06h, sirbe1l fffffd16h, sirbe2l fffffd26h chapter 17 clocked serial interface 0 (csi0) preliminary user?s manual u17702ej1v0ud 531 (5) clocked serial interface transmit bu ffer registers n, nl (sotbn, sotbnl) the sotbn register is a 16-bit buffer r egister that stores transmit data. when the transmission/reception mode is set (csim0n.trmd n bit = 1), the transmission operation is started by writing data to the sotbn register. this register can be read or written in 16-bit units. however, when the lower 8 bi ts are used as the sotbnl register, the register is read-only in 8-bit units. after reset, this regi ster is initialized. cautions 1. access the sotbn register only when a 16-bit data length has been set (csim0n.ccln bit = 1). access the sotbnl register only when an 8-bi t data length has been set (ccln bit = 0). 2. when the single transfer mode is set (csim0n.auton bit = 0) , perform access only in the idle state (csim0n.csotn bit = 0). if the sotbn and sotbnl registers are accessed during data transfer, the da ta cannot be guaranteed. (a) sotbn register 14 sotbn 14 13 sotbn 13 12 sotbn 12 2 sotbn 2 3 sotbn 3 4 sotbn 4 5 sotbn 5 6 sotbn 6 7 sotbn 7 8 sotbn 8 9 sotbn 9 10 sotbn 10 11 sotbn 11 15 sotbn 15 1 sotbn 1 0 sotbn 0 sotbn (n = 0 to 2) after reset: 0000h r/w address: sotb0 fffffd04h, sotb1 fffffd14h, sotb2 fffffd24h (b) sotbnl register 7 sotbn7 sotbnl (n = 0 to 2) 6 sotbn6 5 sotbn5 4 sotbn4 3 sotbn3 2 sotbn2 1 sotbn1 0 sotbn0 after reset: 00h r/w address: sotb0l fffffd04h, sotb1l fffffd14h, sotb2l fffffd24h chapter 17 clocked serial interface 0 (csi0) preliminary user?s manual u17702ej1v0ud 532 (6) clocked serial interface initial transmit buffer registers n, nl (sotbfn, sotbfnl) the sotbfn register is a 16-bit buffer register that st ores initial transmission data in the continuous transfer mode. the transmission operation is not started even if data is writt en to the sotbfn register. this register can be read or written in 16-bit units. however, when the lower 8 bits are used as the sotbfnl register, the register can be read or written in 8-bit units. after reset, this regi ster is initialized. caution access the sotbfn register and sotbfnl regi ster only when a 16-bit data length has been set (csim0n.ccln bit = 1), and only when an 8- bit data length has been set (ccln bit = 0), respectively, and only in the idle state (csim0n.csotn bit = 0). if the sotbfn and sotbfnl registers are accessed during data transfer, the data cannot be guaranteed. (a) sotbfn register 14 sotbfn 14 13 sotbfn 13 12 sotbfn 12 2 sotbfn 2 3 sotbfn 3 4 sotbfn 4 5 sotbfn 5 6 sotbfn 6 7 sotbfn 7 8 sotbfn 8 9 sotbfn 9 10 sotbfn 10 11 sotbfn 11 15 sotbfn 15 1 sotbfn 1 0 sotbfn 0 sotbfn (n = 0 to 2) after reset: 0000h r/w address: sotbf0 fffffd08h, sotbf1 fffffd18h, sotbf2 fffffd28h (b) sotbfnl register 7 sotbfn7 sotbfnl (n = 0 to 2) 6 sotbfn6 5 sotbfn5 4 sotbfn4 3 sotbfn3 2 sotbfn2 1 sotbfn1 0 sotbfn0 after reset: 00h r/w address: sotbf0l fffffd08h, sotbf1l fffffd18h, sotbf2l fffffd28h chapter 17 clocked serial interface 0 (csi0) preliminary user?s manual u17702ej1v0ud 533 (7) serial i/o shift registers n, nl (sio0n, sio0nl) the sio0n register is a 16-bit shift register th at converts parallel data into serial data. the transfer operation is not started even if the s io0n register is read. this register is read-only in 16-bit units. however, when the lower 8 bi ts are used as the sio0nl register, the register is read-only in 8-bit units. in addition to reset input, this register can also be initialized by clearing (0) the csim0n.csi0en bit. caution read the sio0n register and sio0nl re gister only when a 16-bi t data length has been set (csim0n.ccln bit = 1), and only when an 8-bit data length has been set (ccln bit = 0), respectively, and only in the idle state (csim0n.csotn bit = 0). if the sio0n and sio0nl registers are read during data tran sfer, the data cannot be guaranteed. (a) sio0n register 14 sion14 13 sion13 12 sion12 2 sion2 3 sion3 4 sion4 5 sion5 6 sion6 7 sion7 8 sion8 9 sion9 10 sion10 11 sion11 15 sion15 1 sion1 0 sion0 sio0n (n = 0 to 2) after reset: 0000h r address: sio00 fffffd0ah, sio01 fffffd1ah, sio02 fffffd2ah (b) sio0nl register 7 sion7 sio0nl (n = 0 to 2) 6 sion6 5 sion5 4 sion4 3 sion3 2 sion2 1 sion1 0 sion0 after reset: 00h r address: sio00l fffffd0ah, sio01l fffffd1ah, sio02l fffffd2ah chapter 17 clocked serial interface 0 (csi0) preliminary user?s manual u17702ej1v0ud 534 receive-only mode ? reading starts reception ? storing up to the (n ? 2)th data (other than the last two) when reception is complete, read the received data from this register. repeat this operation until the (n ? 2)th data has been received. (supplement) do not read the (n ? 1)th data from this register. if read, a reception operation starts and continuous transfer cannot be completed. storing the (n ? 1)th received data note 2 read the (n ? 1)th received data from this register when the (n ? 1)th or nth (last) data has been received. storing the nth (last) received data note 2 when the nth (last) data has been received, read the nth (last) data. ? not used ? not used continuous transfer note 1 transmission/reception mode storing up to the (n ? 1)th received data (other than the last) note 2 when reception is complete, read the received data from this register. repeat this operation until the (n ? 1)th data has been received. ? not used storing the nth (last) received data note 2 when the nth (last) transmission/reception is complete, read the nth (last) data. ? starting transmission/reception when written ? storing the data to be transmitted second and subsequently when transmission/reception is complete, write the data to be transmitted next to this register to start the next transmission/reception. storing the data to be transmitted first note 2 before starting transmission/reception (writing to sotbn), write the data to be transmitted first. receive-only mode ? reading starts reception ? storing received data ? first, read dummy data and start transfer. ? to perform reception of the next data after reception is complete, read the received data from this register. storing the data received last note 2 if reception of the next data will not be performed after reception is complete, read the received data from this register. ? not used ? not used ? not used single transfer transmission/reception mode storing received data note 2 when transmission and reception are complete, read the received data from this register. ? not used. ? not used. ? starting transmission/reception when written ? storing the data to be transmitted ? when transmission/reception is complete, write the data to be transmitted next. ? not used function use method function use method function use method function use method function use method r/w read read read write write table 17-1. use of each buffer register register name sirbn (sirbnl) sirben (sirbenl) sio0n (sio0nl) sotbn (sotbnl) sotbfn (sotbfnl) notes 1. it is assumed that the number of data to be transmitted is n. 2. neither reading nor writing will start communication. remark in the 16-bit mode, the registers not enclose d in parentheses are used; in the 8-bit mode, the registers in parentheses are us ed. chapter 17 clocked serial interface 0 (csi0) preliminary user?s manual u17702ej1v0ud 535 17.4 operation 17.4.1 transmission/reception completion interrupt request signal (intcsi0n) the intcsi0n signal is set (1) upon comple tion of data transmission/reception. writing to the csim0n register clears (0) the intcsi0n signal. caution the delay mode (csim0n.csi tn bit = 1) is valid only in th e master mode (csicn.cks0n2 to csicn.cks0n0 bits are not 111b). the delay m ode cannot be set when the slave mode is set (cks0n2 to cks0n0 bits = 111b). chapter 17 clocked serial interface 0 (csi0) preliminary user?s manual u17702ej1v0ud 536 figure 17-2. timing chart of intcsi0n signal output in delay mode (a) transmit/receive type 1 di7 di6 di5 di4 di3 di2 di1 di0 do7 do6 do5 do4 do3 do2 do1 do0 input clock sck0n (i/o) si0n (input) so0n (output) reg_r/w intcsi0n signal csotn bit delay (b) transmit/receive type 4 di7 di6 di5 di4 di3 di2 di1 di0 do7 do6 do5 do4 do3 do2 do1 do0 input clock sck0n (i/o) si0n (input) so0n (output) reg_r/w intcsi0n signal csotn bit delay remarks 1. reg_r/w: internal signal. this signal indica tes that the sirbn/sirb nl register read or the sotbn/sotbnl register write was performed. 2. n = 0 to 2 chapter 17 clocked serial interface 0 (csi0) preliminary user?s manual u17702ej1v0ud 537 17.4.2 single transfer mode (1) usage in the receive-only mode (csim0n.trmdn bit = 0), co mmunication is started by reading the sirbn/sirbnl register. in the transmission/reception mode (trmdn bit = 1) , communication is started by writing to the sotbn/sotbnl register. in the slave mode, the operation must be en abled beforehand (csim0n.csi0en bit = 1). when communication is started, t he value of the csim0n.csotn bit becomes 1 (transmission execution status). upon communication completion, the transmission/recepti on completion interrupt request signal (intcsi0n) is generated, and the csotn bit is cleared (0). t he next data communication request is then waited for. caution when the csotn bit = 1, do not manipulate the csi0n register. remark n = 0 to 2 chapter 17 clocked serial interface 0 (csi0) preliminary user?s manual u17702ej1v0ud 538 figure 17-3. timing chart in single transfer mode (1/2) (a) in transmission/recepti on mode, data length: 8 bits , transfer direction: msb first, no interrupt delay, single transfer mode, when aah is received and 55h is transmitted, transmit/receive type 1 01010101 10101010 (55h) (aah) aah aah abh 56h adh 5ah b5h 6ah d5h sck0n (i/o) so0n (output) si0n (input) reg_r/w sotbnl register sio0nl register sirbnl register csotn bit intcsi0n signal 55h (transmit data) write 55h to sotbnl register remarks 1. reg_r/w: internal signal. this signal indica tes that the sirbn/sirb nl register read or the sotbn/sotbnl register write was performed. 2. for the transmit/receive types, refer to 17.3 (2) clocked serial interface clock selection register n (csicn) . 3. n = 0 to 2 chapter 17 clocked serial interface 0 (csi0) preliminary user?s manual u17702ej1v0ud 539 figure 17-3. timing chart in single transfer mode (2/2) (b) in transmission/reception mode, da ta length: 8 bits, transfer directi on: msb first, no interrupt delay, single transfer mode, when aah is received and 55h is transmitted, transmit/receive type 2 01010101 10101010 aah aah abh 56h adh 5ah b5h 6ah d5h sck0n (i/o) so0n (output) si0n (input) reg_r/w sotbnl register sio0nl register sirbnl register csotn bit intcsi0n signal (55h) (aah) 55h (transmit data) write 55h to sotbnl register remarks 1. reg_r/w: internal signal. this signal indica tes that the sirbn/sirb nl register read or the sotbn/sotbnl register write was performed. 2. for the transmit/receive types, refer to 17.3 (2) clocked serial interface clock selection register n (csicn) . 3. n = 0 to 2 chapter 17 clocked serial interface 0 (csi0) preliminary user?s manual u17702ej1v0ud 540 17.4.3 continuous transfer mode (1) usage (receive-only: 8-bit data length) <1> set the continuous transfer mode (csim0n. auton bit = 1) and the receive-only mode (csim0n.trmdn bit = 0). <2> read the sirbnl register (start transfer with dummy read). <3> when the transmission/reception completion interr upt request signal (intcs i0n) has been generated, read the sirbnl register note (reserve next transfer). <4> repeat step <3> (n ? 2) times. (n: number of transfer data) ignore the interrupt trigger ed by reception of the (n ? 1)th data (at this time, the sirbenl register can be read). <5> following generation of the last intcsi0n sign al, read the sirbenl r egister and the sio0nl register note . note when transferring n number of data, receive data is loaded by reading the sirbnl register from the first data to the (n ? 2)th data. the (n ? 1)th data is loaded by readi ng the sirbenl register, and the nth (last) data is loaded by readi ng the sio0nl register (refer to table 17-1 use of each buffer register ). chapter 17 clocked serial interface 0 (csi0) preliminary user?s manual u17702ej1v0ud 541 figure 17-4. continuous transf er (receive-only) timing chart ? transmit/receive type 1, 8-bit data length din-1 sck0n (i/o) si0n (input) so0n (output) l sio0nl register sirbnl register reg-rd csotn bit intcsi0n signal rq_clr trans_rq din-2 din-1 sirbn (dummy) sirbn (1) sirbn (d2) sirbn (d3) sirben (d4) sio0n (d5) <3> <5> <3> <3> <4> period during which next transfer can be reserved <2> <1> din-2 din-3 din-4 din-5 din-5 din-3 din-4 remarks 1. reg_rd: internal signal. this signal indica tes that the sirbnl register has been read. rq_clr: internal signal. transfer request clear signal. trans_rq: internal signal. transfer request signal. 2. n = 0 to 2 in the case of the continuous transfer mode, two transfer requests are set at the star t of the first transfer. following the intcsi0n signal, transfer is continued if the sirbnl register can be read within the next transfer reservation period. if the sirbnl register cannot be read, transfer ends and the sirbnl register does not receive the new value of the sio0nl register. the last data can be obtained by reading the sio0nl register following completion of the transfer. chapter 17 clocked serial interface 0 (csi0) preliminary user?s manual u17702ej1v0ud 542 (2) usage (transmission/reception: 8-bit data length) <1> set the continuous transfer mode (csim0n.au ton bit = 1) and the transmission/reception mode (csim0n.trmdn bit = 1). <2> write the first data to the sotbfnl register. <3> write the 2nd data to the sotb nl register (start transfer). <4> when the transmission/reception completion interr upt request signal (intcs i0n) has been generated, write the next data to the sotbnl regi ster (reserve next transfer). re ad the sirbnl register to load the receive data. <5> repeat step <4> as long as data to be sent remains. <6> when the intcsi0n signal is generated, r ead the sirbnl register to load the (n ? 1)th receive data (n: number of transfer data). <7> following the last intcsi0n signal, read the sio0nl register to load the nth (last) receive data. chapter 17 clocked serial interface 0 (csi0) preliminary user?s manual u17702ej1v0ud 543 figure 17-5. continuous transfer (transmission/reception) timing chart ? transmit/receive type 1, 8-bit data length dout-1 dout-1 sck0n (i/o) so0n (output) si0n (input) sotbfnl register sotbnl register sio0nl register sirbnl register reg_wr reg_rd csotn bit intcsi0n signal rq_clr trans_rq dout-2 dout-3 dout-4 dout-5 dout-2 dout-3 dout-4 dout-5 din-1 din-1 sotbfn (d1) sotbn (d2) sotbn (d3) sotbn (d4) sotbn (d5) sirbn (d1) sirbn (d2) < 5 >< 7 >< 8 > < 4 > < 5 > < 4 > < 6 > period during which next transfer can be reserved < 5 > < 4 > < 3 > < 2 > < 1 > sirbn (d3) sirbn (d4) sion (d5) din-2 din-3 din-4 din-5 din-2 din-3 din-4 din-5 remarks 1. reg_wr: internal signal. this signal indicate s that the sotbnl regist er has been written. reg_rd: internal signal. this signal indica tes that the sirbnl register has been read. rq_clr: internal signal. transfer request clear signal. trans_rq: internal signal. transfer request signal. 2. n = 0 to 2 in the case of the continuous transfe r mode, two transfer requests are set at the start of the first transfer. following the intcsi0n signal, transfer is continued if the sotbnl register can be written within the next transfer reservation period. if the sotbnl register cannot be written, transfer ends and the sirbnl register does not receive the new value of the sio0nl register. the last receive data can be obtained by reading the sio0nl register follo wing completion of the transfer. chapter 17 clocked serial interface 0 (csi0) preliminary user?s manual u17702ej1v0ud 544 (3) next transfer reservation period in the continuous transfer mode, the next transfer mu st be prepared with the period shown in figure 17-6. figure 17-6. timing chart of next transfer reservation period (1/2) (a) when data length: 8 bits, transmit/receive type 1 sck0n (i/o) intcsi0n signal reservation period: 7 sck0n cycles (b) when data length: 16 bi ts, transmit/receive type 1 sck0n (i/o) intcsi0n signal reservation period: 15 sck0n cycles remark n = 0 to 2 chapter 17 clocked serial interface 0 (csi0) preliminary user?s manual u17702ej1v0ud 545 figure 17-6. timing chart of next transfer reservation period (2/2) (c) when data length: 8 bi ts, transmit/receive type 2 sck0n (i/o) intcsi0n signal reservation period: 6.5 sck0n cycles (d) when data length: 16 bi ts, transmit/receive type 2 sck0n (i/o) intcsi0n signal reservation period: 14.5 sck0n cycles remark n = 0 to 2 chapter 17 clocked serial interface 0 (csi0) preliminary user?s manual u17702ej1v0ud 546 (4) cautions to continue continuous transfers, it is necessary to either read the sirb n register or write to the sotbn register during the transfer reservation period. if access is performed to the sirbn register or the so tbn register when the transfer reservation period is over, the following occurs. (i) in case of conflict between transfer request clear and register access since transfer request clear has higher priority, the nex t transfer request is ignored. therefore, transfer is interrupted, and normal data transfer cannot be performed. figure 17-7. transfer request clear and register access conflict sck0n (i/o) intcsi0n signal rq_clr reg_r/w transfer reservation period remarks 1. rq_clr: internal signal. transfer request clear signal. reg_r/w: internal signal. this signal indica tes that the sirbn/sirb nl register read or the sotbn/sotbnl register write was performed. 2. n = 0 to 2 chapter 17 clocked serial interface 0 (csi0) preliminary user?s manual u17702ej1v0ud 547 (ii) in case of conflict between tr ansmission/reception completion inte rrupt request sign al (intcsi0n) generation and register access since continuous transfer has stopped once, ex ecuted as a new continuous transfer. in the slave mode, a bit phase erro r transfer error results (refer to figure 17-8 ). in the transmission/reception mode, the value of the so tbfn register is retransmitted, and illegal data is sent. figure 17-8. interrupt request and register ac cess conflict sck0n (i/o) intcsi0n signal rq_clr reg_r/w transfer reservation period 01 234 remarks 1. rq_clr: internal signal. transfer request clear signal. reg_r/w: internal signal. this signal indica tes that the sirbn/sirb nl register read or the sotbn/sotbnl register write was performed. 2. n = 0 to 2 chapter 17 clocked serial interface 0 (csi0) preliminary user?s manual u17702ej1v0ud 548 17.5 output pins the following describes the output pins. for the setting of each pin, refer to table 4-19 settings when port pins are used for alternate functions . (1) sck0n pin when the csi0n operation is disabled (csim0n.csi0en bi t = 0), the sck0n pin output status is as follows. table 17-2. sck0n pin output status ckpn cks0n2 cks0n1 cks0n0 sck0n pin output 0 don?t care don?t care don?t care fixed to high level 1 1 1 high impedance 1 other than above fixed to low level remark n = 0 to 2 (2) so0n pin when the csi0n operation is disabled (csi0en bit = 0), the so0n pin output status is as follows. table 17-3. so0n pin output status trmdn dapn auton ccln dirn so0n pin output 0 don?t care don?t care don?t care don?t care fixed to low level 0 don?t care don?t care don?t care so latch value (low level) 0 sotbn7 bit value 0 1 sotbn0 bit value 0 sotbn15 bit value 0 1 1 sotbn0 bit value 0 sotbfn7 bit value 0 1 sotbfn0 bit value 0 sotbfn15 bit value 1 1 1 1 1 sotbfn0 bit value remark n = 0 to 2 preliminary user?s manual u17702ej1v0ud 549 chapter 18 clocked serial interface a (csia) with automatic transmit /receive function in the v850es/kj2, two channels of clocked serial interfac e a (csia) with automatic transmit/receive function are provided. 18.1 functions csian has the following two modes. ? 3-wire serial i/o mode ? 3-wire serial i/o mode with automatic transmit/receive function (1) 3-wire serial i/o mode this mode is used to transfer 8-bit data using three lines : a serial clock pin (sckan) and two serial data pins (sian and soan). in addition, whether 8-bit data is transferred msb or lsb first can be specified, so this interface can be connected to any device. (2) 3-wire serial i/o mode with auto matic transmit/receive function this mode is used to transfer 8-bit data using three lines : a serial clock pin (sckan) and two serial data pins (sian and soan). in addition, whether 8-bit data is transferred msb or lsb first can be specified, so this interface can be connected to any device. data can be transferred to/from a display driver etc. without using software since a 32-byte buffer ram is incorporated for automatic transfer. ? maximum transfer speed: 2 mbps (in master mode) ? master mode/slave mode selectable ? transfer data length: 8 bits ? msb/lsb-first selectable for transfer data ? automatic transmit/receive function: number of transfer bytes c an be specified between 1 and 32 transfer interval can be specified (0 to 63 clocks) single transfer/repeat transfer selectable ? on-chip dedicated baud rate generator (6/8/16/32 divisions) ? 3-wire soan: serial data output sian: seri al data input sckan: serial clock i/o ? transmission/reception completion interrupt request signal: intcsian ? internal 32-byte buffer ram (us ed in 3-wire serial i/o mode with aut omatic transmit/receive function) remark n = 0, 1 chapter 18 clocked serial interface a (csia) with automatic transmit/receive function preliminary user?s manual u17702ej1v0ud 550 18.2 configuration csian consists of the following hardware. table 18-1. configuration of csian item configuration register serial i/o shi ft register an (sioan) automatic data transfer address count register n (adtcn) csian buffer ram (csianbm, csianbml, csianbmh) (m = 0 to f) control registers serial operation mode specification register n (csiman) serial status register n (csisn) serial trigger register n (csitn) divisor selection register n (brgcan) automatic data transfer address point specification register n (adtpn) automatic data transfer interval specification register n (adtin) remark for the alternate-function pin settings, refer to table 4-19 settings when port pins are used for alternate functions . chapter 18 clocked serial interface a (csia) with automatic transmit/receive function preliminary user?s manual u17702ej1v0ud 551 figure 18-1. block diagram of csian f xx /6 to f xx /256 mastern sckan soan sian diran atmn cksan1 cksan0 atstpn atstan tsfn intcsian rxean txean 2 2 f xx buffer ram automatic data transfer address point specification register n (adtpn) automatic data transfer address count register n (adtcn) internal bus divisor selection register n (brgcan) serial i/o shift register an (sioan) serial trigger register n (csitn) serial status register n (csisn) selector selector 6-bit counter interrupt generator serial transfer controller serial clock counter automatic data transfer interval specification register n (adtin) chapter 18 clocked serial interface a (csia) with automatic transmit/receive function preliminary user?s manual u17702ej1v0ud 552 (1) serial i/o shift register an (sioan) this is an 8-bit register used to store transmit/receive data in 1-byte transfer mode (csiman.aten bit = 0). writing transmit data to the sioan regist er starts the transfer. in addition, after a transfer completion interrupt request signal (intcsian) is generat ed (csisn.tsfn bit = 0), data can be received by reading data from the sioan register. this register can be read or written in 8-bit units. ho wever, writing to the sioan register is prohibited when the csisn.tsfn bit = 1. after reset, this register is cleared to 00h. cautions 1. a transfer operation is started by writing to sioan register . consequently, when transmission is disabled (csiman.txean bi t = 0), write dummy data to the sioan register to start the transfer operation, and then perform a receive operation. 2. do not write data to the sioan register while the automatic transmit/receive function is operating. 7 sioan7 sioan (n = 0, 1) 6 sioan6 5 sioan5 4 sioan4 3 sioan3 2 sioan2 1 sioan1 0 sioan0 after reset: 00h r/w address: sioa0 fffffd46h, sioa1 fffffd56h (2) automatic data transfer a ddress count register n (adtcn) this is a register used to indicate buffer ram addresses during automatic transfer. when automatic transfer is stopped, the data position when transfer stopped can be ascertained by reading adtcn register value. this register is read-only in 8-bit units. however, reading from the adtcn register is prohibited when the csisn.tsfn bit = 1. after reset, this register is cleared to 00h. 7 adtcn7 adtcn (n = 0, 1) 6 adtcn6 5 adtcn5 4 adtcn4 3 adtcn3 2 adtcn2 1 adtcn1 0 adtcn0 after reset: 00h r address: adtc0 fffffd47h, adtc1 ffffd57h 18.3 registers serial interface csian is controlle d by the following six registers. ? serial operation mode specif ication register n (csiman) ? serial status register n (csisn) ? serial trigger register n (csitn) ? divisor selection register n (brgcan) ? automatic data transfer address point specification register n (adtpn) ? automatic data transfer interval specification register n (adtin) chapter 18 clocked serial interface a (csia) with automatic transmit/receive function preliminary user?s manual u17702ej1v0ud 553 (1) serial operation mode speci fication register n (csiman) this is an 8-bit register used to c ontrol the serial transfer operation. this register can be read or written in 8-bit or 1-bit units. after reset, this register is cleared to 00h. <7> csiaen disable csian operation (soan: low level, sckan: high level) enable csian operation csiaen 0 1 csian operation enable/disable control csiman (n = 0, 1) 6 aten 5 atmn 4 mastern <3> txean <2> rxean <1> diran 0 0 1-byte transfer mode automatic transfer mode aten 0 1 automatic transfer operation enable/disable control single transfer mode (stops at address specified with adtpn register) repeat transfer mode (following transfer completion, the adtcn register is cleared to 00h and transmission starts again.) atmn 0 1 specification of automatic transfer mode slave mode (synchronized with sckan input clock) master mode (synchronized with internal clock) mastern 0 1 specification of csian master/slave mode disable transmission (soan: low level) enable transmission txean 0 1 transmission enable/disable control disable reception enable reception rxean 0 1 reception enable/disable control msb first lsb first diran 0 1 specification of transfer data direction after reset: 00h r/w address: csima0 fffffd40h, csima1 ffffd50h when the csiaen bit is cleared to 0, the csian unit is reset note asynchronously. when the csiaen bit = 0, the csian unit is reset, so to operate csian, first set the csiaen bit to 1. if the csiaen bit is cleared from 1 to 0, all the registers in the csian unit are initialized. before the csiaen bit is set to 1 again, first re-set the registers of the csian unit. if the csiaen bit is cleared from 1 to 0, the buffer ram value is not held. also, when the csiaen bit = 0, the buffer ram cannot be accessed. note the adtcn, csitn, and sioan regi sters and the csis.tsfn bit are reset. chapter 18 clocked serial interface a (csia) with automatic transmit/receive function preliminary user?s manual u17702ej1v0ud 554 (2) serial status register n (csisn) this is an 8-bit register used to select the serial clock and to indicate the transfer status of csian. this register can be read or written in 8-bit or 1-bit units. after reset, this register is cleared to 00h. however, rewriting the csisn register is prohibited when the tsfn bit is 1. 7 cksan1 f xx f xx /2 f xx /4 f xx /8 20 mhz setting prohibited 100 ns 200 ns 400 ns 16 mhz setting prohibited 125 ns 250 ns 500 ns 10 mhz 100 ns 200 ns 400 ns 800 ns cksan1 0 0 1 1 cksan0 0 1 0 1 serial clock (f scka ) selection note csisn (n = 0, 1) 6 cksan0 5 0 4 0 3 0 2 0 1 0 0 tsfn csiaen bit = 0 at reset input at completion of specified transfer when transfer has been suspended by setting the csitn.atstpn bit to 1 from transfer start to completion of specified transfer rewriting csisn is prohibited when the csiman.csiaen bit is 1. tsfn 0 1 transfer status after reset: 00h r/w address: csis0 fffffd41h, csis1 ffffd51h note set f scka so as to satisfy the following conditions. ? regc = v dd = 4.0 to 5.5 v: f scka 12 mhz ? regc = 10 f, v dd = 4.0 to 5.5 v: f scka 6 mhz ? regc = v dd = 2.7 to 4.0 v: f scka 6 mhz cautions 1. the tsfn bit is read-only. 2. when the tsfn bit = 1, rewriting the csiman, csisn, brgcan, adtpn, adtin, and sioan registers is prohibited. however, the transfer buffe r ram can be rewritten. 3. be sure to clear bits 1 to 5 to 0. chapter 18 clocked serial interface a (csia) with automatic transmit/receive function preliminary user?s manual u17702ej1v0ud 555 (3) serial trigger register n (csitn) the csitn register between the buffer ram and shif t register is an 8-bit register used to control execution/stop of autom atic data transfer. this register can be read or written in 8-bit or 1-bi t units. however, manipulate only when the csiman.aten bit is 1 (manipulation prohibited when aten bit = 0). after reset, this register is cleared to 00h. 7 0 csitn (n = 0, 1) 6 0 5 0 4 0 3 0 2 0 <1> atstpn <0> atstan ? stop automatic data transfer atstpn 0 1 automatic data transfer suspension even when the atstpn bit is set to 1, transfer does not stop until 1 byte has been transferred. 1 is held until immediately before the transmission/reception completion interrupt request signal (intcsian) is generated, and atstpn is automatically cleared to 0 after that. after automatic transfer has been suspended, the data address at the point of suspension is stored in the adtcn register. a function to resume automatic data transfer is not provided, so if transfer has been interrupted by setting the atstpn bit to 1, set each register again, and set the atstan bit to 1 to start automatic data transfer. after reset: 00h r/w address: csit0 fffffd42h, csit1 ffffd52h ? start automatic data transfer atstan 0 1 automatic data transfer start even when the atstan bit is set to 1, automatic data transfer does not start until 1 byte has been transferred. 1 is held until immediately before the intcsian signal is generated, and atstan is automatically cleared to 0 after that. chapter 18 clocked serial interface a (csia) with automatic transmit/receive function preliminary user?s manual u17702ej1v0ud 556 (4) divisor selection register n (brgcan) this is an 8-bit register used to control the se rial transfer speed (divisor of csia clock). this register can be read or written in 8-bit units. however, when the csisn.tsfn bit is 1, rewriting the brgcan register is prohibited. after reset, this register is set to 03h. 7 0 brgcn1 0 0 1 1 brgcn0 0 1 0 1 selection of csian serial clock (f scka division ratio) brgcan (n = 0, 1) 6 0 5 0 4 0 3 0 2 0 1 brgcn1 0 brgcn0 after reset: 03h r/w address: brgca0 fffffd43h, brgca1 ffffd53h 6 (f scka /6) 8 (f scka /8) 16 (f scka /16) 32 (f scka /32) (5) automatic data transfer address point specification register n (adtpn) this is an 8-bit register used to specify the buffe r ram address that ends transfer during automatic data transfer (csiman.aten bit = 1). this register can be read or written in 8-bit units. however, when the csisn.tsfn bit is 1, rewriting the adtpn register is prohibited. after reset, this register is cleared to 00h. in the v850es/kj2, 00h to 1fh can be specified because 32 bytes of buffer ram are incorporated. example when the adtp0 register is set to 07h 8 bytes of fffffe00h to fffffe07h are transferred. in repeat transfer mode (csiman.atmn bit = 1), trans fer is performed repeatedly up to the address value specified by adtpn. example when the adtp0 register is set to 07h (repeat transfer mode) transfer is repeated as fffffe00h to fffffe07h, ? . 7 0 adtpn (n = 0, 1) 6 0 5 0 4 adtpn4 3 adtpn3 2 adtpn2 1 adtpn1 0 adtpn0 after reset: 00h r/w address: adtp0 fffffd44h, adtp1 ffffd54h caution be sure to clear bits 5 to 7 to 0. chapter 18 clocked serial interface a (csia) with automatic transmit/receive function preliminary user?s manual u17702ej1v0ud 557 the relationship between buffer ram address values and the adtpn register setting values is shown below. table 18-2. relationship between buffer ram a ddress values and adtp0 register setting values buffer ram address value adtp0 register setting value b uffer ram address value adtp0 register setting value fffffe00h 00h fffffe10h 10h fffffe01h 01h fffffe11h 11h fffffe02h 02h fffffe12h 12h fffffe03h 03h fffffe13h 13h fffffe04h 04h fffffe14h 14h fffffe05h 05h fffffe15h 15h fffffe06h 06h fffffe16h 16h fffffe07h 07h fffffe17h 17h fffffe08h 08h fffffe18h 18h fffffe09h 09h fffffe19h 19h fffffe0ah 0ah fffffe1ah 1ah fffffe0bh 0bh fffffe1bh 1bh fffffe0ch 0ch fffffe1ch 1ch fffffe0dh 0dh fffffe1dh 1dh fffffe0eh 0eh fffffe1eh 1eh fffffe0fh 0fh fffffe1fh 1fh table 18-3. relationship between buffer ram a ddress values and adtp1 register setting values buffer ram address value adtp1 register setting value b uffer ram address value adtp1 register setting value fffffe20h 00h fffffe30h 10h fffffe21h 01h fffffe31h 11h fffffe22h 02h fffffe32h 12h fffffe23h 03h fffffe33h 13h fffffe24h 04h fffffe34h 14h fffffe25h 05h fffffe35h 15h fffffe26h 06h fffffe36h 16h fffffe27h 07h fffffe37h 17h fffffe28h 08h fffffe38h 18h fffffe29h 09h fffffe39h 19h fffffe2ah 0ah fffffe3ah 1ah fffffe2bh 0bh fffffe3bh 1bh fffffe2ch 0ch fffffe3ch 1ch fffffe2dh 0dh fffffe3dh 1dh fffffe2eh 0eh fffffe3eh 1eh fffffe2fh 0fh fffffe3fh 1fh chapter 18 clocked serial interface a (csia) with automatic transmit/receive function preliminary user?s manual u17702ej1v0ud 558 (6) automatic data transfer inter val specification register n (adtin) this is an 8-bit register used to specify the interv al period between 1-byte trans fers during automatic data transfer (csiman.aten bit = 1). set this register when in master mode (csiman.mast ern bit = 1) (setting is unnecessary in slave mode). setting in 1-byte transfer mode (aten bit = 0) is also va lid. when the interval ti me specified by the adtin register after the end of 1-byte transfer has elapsed, a transmission/reception completion interrupt request signal (intcsian) is output. the number of clocks for the interval can be set to between 0 and 63 clocks. this register can be read or written in 8-bit units. however, when the csisn.tsfn bit is 1, rewriting the adtin register is prohibited. after reset, this register is cleared to 00h. adtin (n = 0, 1) after reset: 00h r/w address: adti0 fffffd45h, adti1 ffffd55h 7 0 6 0 5 adtin5 4 adtin4 3 adtin3 2 adtin2 1 adtin1 0 adtin0 the specified interval time is the transfer clock (specif ied by the brgcan register) multiplied by an integer value. example when adtin register = 03h sckan interval time of 3 clocks (7) csian buffer ram (csianbm) this area holds transmit/receive data (up to 32 byte s) in automatic transfer mode in 1-byte units. this register can be read or written in 16-bit units. however, when the higher 8 bits and the lower 8 bits of the csianbm register are used as the csianbmh r egister and csianbml register, respectively, these registers can be read or written in 8-bit units. after automatic transfer is started, only data equal to one byte more than the number of bytes stored in the adtpn register is transmitted/received in sequence from the csiamb0l register. cautions 1. to read the value of th e csianbm register after data is written to the register, wait for the duration of more than six clocks of f scka (serial clock set by the csisn.cksan1 and csisn.cksan0 bits) or until data is writte n to the buffer ram at another address. 2. when the main clock stops and th e cpu operates on the subclock, do not access the csianbm register. for details, refer to 3.4.8 (1) (b). remark n = 0, 1 m = 0 to f chapter 18 clocked serial interface a (csia) with automatic transmit/receive function preliminary user?s manual u17702ej1v0ud 559 table 18-4. csia0 buffer ram manipulatable bits address symbol r/w 8 16 after reset fffffe00h csia0b0 r/w undefined fffffe00h csia0b0l r/w undefined fffffe01h csia0b0h r/w undefined fffffe02h csia0b1 r/w undefined fffffe02h csia0b1l r/w undefined fffffe03h csia0b1h r/w undefined fffffe04h csia0b2 r/w undefined fffffe04h csia0b2l r/w undefined fffffe05h csia0b2h r/w undefined fffffe06h csia0b3 r/w undefined fffffe06h csia0b3l r/w undefined fffffe07h csia0b3h r/w undefined fffffe08h csia0b4 r/w undefined fffffe08h csia0b4l r/w undefined fffffe09h csia0b4h r/w undefined fffffe0ah csia0b5 r/w undefined fffffe0ah csia0b5l r/w undefined fffffe0bh csia0b5h r/w undefined fffffe0ch csia0b6 r/w undefined fffffe0ch csia0b6l r/w undefined fffffe0dh csia0b6h r/w undefined fffffe0eh csia0b7 r/w undefined fffffe0eh csia0b7l r/w undefined fffffe0fh csia0b7h r/w undefined fffffe10h csia0b8 r/w undefined fffffe10h csia0b8l r/w undefined fffffe11h csia0b8h r/w undefined fffffe12h csia0b9 r/w undefined fffffe12h csia0b9l r/w undefined fffffe13h csia0b9h r/w undefined fffffe14h csia0ba r/w undefined fffffe14h csia0bal r/w undefined fffffe15h csia0bah r/w undefined fffffe16h csia0bb r/w undefined fffffe16h csia0bbl r/w undefined fffffe17h csia0bbh r/w undefined fffffe18h csia0bc r/w undefined fffffe18h csia0bcl r/w undefined fffffe19h csia0bch r/w undefined fffffe1ah csia0bd r/w undefined fffffe1ah csia0bdl r/w undefined fffffe1bh csia0bdh r/w undefined fffffe1ch csia0be r/w undefined fffffe1ch csia0bel r/w undefined fffffe1dh csia0beh r/w undefined fffffe1eh csia0bf r/w undefined fffffe1eh csia0bfl r/w undefined fffffe1fh csia0bfh r/w undefined chapter 18 clocked serial interface a (csia) with automatic transmit/receive function preliminary user?s manual u17702ej1v0ud 560 table 18-5. csia1 buffer ram manipulatable bits address symbol r/w 8 16 after reset fffffe20h csia1b0 r/w undefined fffffe20h csia1b0l r/w undefined fffffe21h csia1b0h r/w undefined fffffe22h csia1b1 r/w undefined fffffe22h csia1b1l r/w undefined fffffe23h csia1b1h r/w undefined fffffe24h csia1b2 r/w undefined fffffe24h csia1b2l r/w undefined fffffe25h csia1b2h r/w undefined fffffe26h csia1b3 r/w undefined fffffe26h csia1b3l r/w undefined fffffe27h csia1b3h r/w undefined fffffe28h csia1b4 r/w undefined fffffe28h csia1b4l r/w undefined fffffe29h csia1b4h r/w undefined fffffe2ah csia1b5 r/w undefined fffffe2ah csia1b5l r/w undefined fffffe2bh csia1b5h r/w undefined fffffe2ch csia1b6 r/w undefined fffffe2ch csia1b6l r/w undefined fffffe2dh csia1b6h r/w undefined fffffe2eh csia1b7 r/w undefined fffffe2eh csia1b7l r/w undefined fffffe2fh csia1b7h r/w undefined fffffe30h csia1b8 r/w undefined fffffe30h csia1b8l r/w undefined fffffe31h csia1b8h r/w undefined fffffe32h csia1b9 r/w undefined fffffe32h csia1b9l r/w undefined fffffe33h csia1b9h r/w undefined fffffe34h csia1ba r/w undefined fffffe34h csia1bal r/w undefined fffffe35h csia1bah r/w undefined fffffe36h csia1bb r/w undefined fffffe36h csia1bbl r/w undefined fffffe37h csia1bbh r/w undefined fffffe38h csia1bc r/w undefined fffffe38h csia1bcl r/w undefined fffffe39h csia1bch r/w undefined fffffe3ah csia1bd r/w undefined fffffe3ah csia1bdl r/w undefined fffffe3bh csia1bdh r/w undefined fffffe3ch csia1be r/w undefined fffffe3ch csia1bel r/w undefined fffffe3dh csia1beh r/w undefined fffffe3eh csia1bf r/w undefined fffffe3eh csia1bfl r/w undefined fffffe3fh csia1bfh r/w undefined chapter 18 clocked serial interface a (csia) with automatic transmit/receive function preliminary user?s manual u17702ej1v0ud 561 18.4 operation csian can be used in the following two modes. ? 3-wire serial i/o mode ? 3-wire serial i/o mode with automatic transmit/receive function 18.4.1 3-wire serial i/o mode the one-byte data transmission/reception is executed in t he mode in which the csiman.aten bit is cleared to 0. in this mode, communication is executed by using three lin es: serial clock (sckan), serial data output (soan), and serial data input (sian) pins. the 3-wire serial i/o mode is controlled by the following three registers. ? serial operation mode specif ication register n (csiman) ? serial status register n (csisn) ? divisor selection register n (brgcan) remarks 1. for the alternate-function pin settings, refer to table 4-19 settings when port pins are used for alternate functions . 2. n = 0, 1 chapter 18 clocked serial interface a (csia) with automatic transmit/receive function preliminary user?s manual u17702ej1v0ud 562 (1) 1-byte transmission/recep tion communication operation (a) 1-byte transmission/reception when the csiman.csiaen bit and the csiman.aten bit = 1, 0, respectively, if transfer data is written to the sioan register, the data is out put via the soa0 pin in synchronization with the sckan pin falling edge, and then input via the sian pin in synchroni zation with the falling edge of the sckan pin, and stored in the sioan register in synchroniza tion with the rising edge 1 clock later. data transmission and data reception can be performed simultaneously. if only reception is to be performed, transfer can only be started by writing a dummy value to the sioan register. when transfer of 1 byte is complete, a transmission/reception completion interrupt request signal (intcsian) is generated. in 1-byte transmission/reception, the se tting of the csiman.atmn bit is invalid. be sure to read data after confi rming that the csisn.tsfn bit = 0. caution determine the setting proc edure of alternate-function pins considering the relationship with the communication partner. figure 18-2. 3-wire serial i/o mode timing 12345678 di7 di6 di5 di4 di3 di2 di1 di0 do7 do6 do5 do4 do3 do2 do1 do0 end of transfer transfer starts at falling edge of sckan pin sckan sian soan intcsian sioan write tsfn caution the soan pin becomes low l evel by the sioan register write. remark n = 0, 1 chapter 18 clocked serial interface a (csia) with automatic transmit/receive function preliminary user?s manual u17702ej1v0ud 563 (b) data format in the data format, data is changed in synchronization with the sckan pin falling edge as shown in figure 18-3. the data length is fixed to 8 bits and the data trans fer direction can be switched by the specification of the csiman.diran bit. figure 18-3. format of transmit/receive data (a) msb-first (diran bit = 0) sckan sian do7 do6 do5 do4 do3 do2 do1 do0 soan di7 di6 di5 di4 di3 di2 di1 di0 (b) lsb-first (diran bit = 1) sckan sian do0 do1 do2 do3 do4 do5 do6 do7 soan di0 di1 di2 di3 di4 di5 di6 di7 remark n = 0, 1 chapter 18 clocked serial interface a (csia) with automatic transmit/receive function preliminary user?s manual u17702ej1v0ud 564 (c) switching msb/lsb as start bit figure 18-4 shows the configuration of the sioan register and the internal bus. as shown in the figure, msb/lsb can be read or written in reverse form. switching msb/lsb as the start bit can be specified using the csiman.diran bit. start bit switching is realized by switching the bit order for data written to the sioan register. the sioan register shift order remains unchanged. thus, switching between msb-first and lsb-first must be performed before writing data to the sioan register. figure 18-4. transfer bit order switching circuit 7 6 internal bus 1 0 lsb-first msb-first read/write gate sian shift register n (sioan) read/write gate soan sckan dq soan latch remark n = 0, 1 (d) transfer start serial transfer is started by setting transfer data to the sioan register when the following two conditions are satisfied. ? csian operation control bit (csiman.csiaen) = 1 ? other than during serial communication caution if the csiaen bit is set to 1 after data is written to the sioan register, communication does not start. upon termination of 8-bit communication, serial communication automatically stops and the transmission/reception completion interrupt request signal (intcsian) is generated. remark n = 0, 1 chapter 18 clocked serial interface a (csia) with automatic transmit/receive function preliminary user?s manual u17702ej1v0ud 565 18.4.2 3-wire serial i/o mode with au tomatic transmit/receive function up to 32 bytes of data can be transmi tted/received without using software in the mode in which the csiman.aten bit is set to 1. after communication is started, only dat a of the set number of bytes stored in ram in advance can be transmitted, and only data of the set number of bytes can be received and stored in ram. the 3-wire serial i/o mode with automatic transmit/receive function is controlled by the following registers. ? serial operation mode specif ication register n (csiman) ? serial status register n (csisn) ? serial trigger register n (csitn) ? divisor selection register n (brgcan) ? automatic data transfer address point specification register n (adtpn) ? automatic data transfer interval specification register n (adtin) remarks 1. for the alternate-function pin settings, refer to table 4-19 settings when port pins are used for alternate functions . 2. n = 0, 1 (1) automatic transmit/receive data setting (a) transmit data setting <1> write transmit data from the least significant address fffffe00h/ fffffe20h of buffer ram (up to fffffe1fh/fffffe3fh at maximum). the transmit data should be in the order from lower address to higher address. <2> set the adtpn register to the value obtained by subtracting 1 from the number of transmit data bytes. (b) automatic transmissi on/reception mode setting <1> set the csiman.csiaen bit and the csiman.aten bit to 11. <2> set the csiman.rxean bit a nd the csiman.txean bit to 11. <3> set a data transfer interval in the adtin register. <4> set the csitn.atstan bit to 1. the following operations are automatically carried out when (a) and (b) are carried out. ? after the buffer ram data indicated by the adtcn register is transferred to the sioan register, transmission is carried out (start of automatic transmission/reception). ? the received data is written to the buffer ram address indicated by the adtcn register. ? adtcn register is incremented and the next data transmission/reception is carried out. data transmission/reception continues until the adtcn regist er incremental output matches the set value of the adtpn register (end of automatic transmission/rec eption). however, if the csiman.atmn bit is set to 1 (continuous transfer mode), the adtcn regist er is cleared after a match between the adtpn and adtcn registers, and then repeated tr ansmission/reception is started. ? when automatic transmission/reception is termi nated, the csisn.tsfn bit is cleared to 0. caution determine the setting proc edure of alternate-function pins considering the relationship with the communication partner. remark n = 0, 1 chapter 18 clocked serial interface a (csia) with automatic transmit/receive function preliminary user?s manual u17702ej1v0ud 566 (2) automatic transmission/re ception communication operation (a) automatic transmi ssion/reception mode automatic transmission/reception can be performed using buffer ram. the data stored in the buffer ram is output from the soan pin via the sioan register in synchronization with the sckan pin falling edge by performing (a) and (b) in (1) automatic transmit/receive data setting . the data is then input from the sian pin via the sioa n register in synchronization with the serial clock falling edge of the sckan pin and the receive data is stored in the buffer ram in synchronization with the rising edge 1 clock later. data transfer ends if the csisn.tsfn bit is cleared to 0 when any of the following conditions is met. ? reset by clearing the csiman.csiaen bit to 0 ? transfer of 1 byte is complete by setting the csitn.atstpn bit to 1 ? transfer of the range specified by the adtpn register is complete at this time, a transmission/reception completion inte rrupt request signal (intcsian) is generated except when the csiaen bit = 0. if a transfer is terminated in the middle, transfer star ting from the remaining data is not possible. read the adtcn register to confirm how much of the dat a has already been transferred, set the transfer data again, and perform (a) and (b) in (1) automatic transmit/receive data setting . figure 18-5 shows the operation timing in automatic transmission/reception mode and figure 18-6 shows the operation flowchart. figure 18-7 shows the oper ation of the buffer ram when 6 bytes of data are transmitted/received. remark n = 0, 1 chapter 18 clocked serial interface a (csia) with automatic transmit/receive function preliminary user?s manual u17702ej1v0ud 567 figure 18-5. automatic transmission/reception mo de operation timings interval sckan d7 soan sian intcsian tsfn interval d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 cautions 1. because, in the automatic transmission/reception mode, the automatic transmit/receive function reads/writes da ta from/to the buffer ram after 1-byte transmission/reception, an inter val is inserted until the next transmission/reception. as the buffer ram read/write is performed at the same time as cpu processing, the interval is dependent up on the value of the adtin register. 2. when the tsfn bit is cleared , the soan pin becomes low level. 3. if cpu access to the buffer ram conflicts with csian read/write during the interval time, the inter val time becomes longer. remark n = 0, 1 chapter 18 clocked serial interface a (csia) with automatic transmit/receive function preliminary user?s manual u17702ej1v0ud 568 figure 18-6. automatic transm ission/reception mode flowchart start write transmit data in buffer ram set adtpn register to the value (pointer value) obtained by subtracting 1 from the number of transmit data bytes set automatic transmission/ reception mode set csitn.atstan bit to 1 write transmit data from buffer ram to sioan register transmission/reception operation write receive data from sioan register to buffer ram adtpn register = adtcn register no tsfn bit = 0 no end yes yes increment pointer value software execution hardware execution software execution remark n = 0, 1 chapter 18 clocked serial interface a (csia) with automatic transmit/receive function preliminary user?s manual u17702ej1v0ud 569 in 6-byte transmission/reception (c siman.atmn bit = 0, csiman.rxean bit = 1, csiman.txean bit = 1) in automatic transmission/reception m ode, buffer ram operates as follows. (i) when transmission/reception operation is started (refer to figure 18-7 (a).) when the csitn.atstan bit is set to 1, transmit data 1 (t1) is transferred from the buffer ram to the sioan register. when transmission of the firs t byte is completed, receive data 1 (r1) is transferred from the sioan register to the buffer ram, and the adtcn register is incremented. then transmit data 2 (t2) is transferred from the buffer ram to the sioan register. (ii) 4th byte transmission/reception point (refer to figure 18-7 (b).) transmission/reception of the third byte is complete d, and transmit data 4 (t4) is transferred from the buffer ram to the sioan register. when transmission of the fourth byte is completed, the receive data 4 (r4) is transferred from t he sioan register to the buffer ram, and the adtcn register is incremented. (iii) completion of transmission/rece ption (refer to figure 18-7 (c).) when transmission of the sixth byte is completed, receive data 6 (r6) is transferred from sioan register to the buffer ram, and the transmission/ reception completion interrupt request signal (intcsian) is generated. figure 18-7. buffer ram operation in 6-byte transmission/reception (in automatic transmissi on/reception mode) (1/2) (a) when transmission/rece ption operation is started transmit data 6 (t6) transmit data 5 (t5) transmit data 4 (t4) transmit data 3 (t3) transmit data 2 (t2) transmit data 1 (t1) fffffe1fh fffffe05h fffffe00h receive data 1 (r1) sioan register not generated intcsian signal 0 adtcn register +1 5 adtpn register remarks 1. the above addresses are for csia0. fo r csia1, the addresses are fffffe20h to fffffe3fh. 2. n = 0, 1 chapter 18 clocked serial interface a (csia) with automatic transmit/receive function preliminary user?s manual u17702ej1v0ud 570 figure 18-7. buffer ram operation in 6-byte transmission/reception (in automatic transmissi on/reception mode) (2/2) (b) 4th byte transmission/reception transmit data 6 (r6) transmit data 5 (r5) transmit data 4 (r4) receive data 3 (t3) receive data 2 (t2) receive data 1 (t1) fffffe1fh fffffe05h fffffe00h receive data 4 (r4) sioan register not generated intcsian signal 3 adtcn register +1 5 adtpn register (c) completion of transmission/reception receive data 6 (r6) receive data 5 (r5) receive data 4 (r4) receive data 3 (r3) receive data 2 (r2) receive data 1 (r1) fffffe1fh fffffe05h fffffe00h sioan register generated intcsian signal 5 adtcn register 5 adtpn register remarks 1. the above addresses are for csia0. fo r csia1, the addresses are fffffe20h to fffffe3fh. 2. n = 0, 1 chapter 18 clocked serial interface a (csia) with automatic transmit/receive function preliminary user?s manual u17702ej1v0ud 571 (b) automatic transmission mode in this mode, the specified number of 8-bit unit data are transmitted. serial transfer is started when the csitn.atst an bit is set to 1 while the csiman.csiaen, csiman.aten, and csiman.txean bits are set to 1. when the final byte has been transmitted, an inte rrupt request signal (intcsian) is generated. figure 18-8 shows the automatic transmission mode operation timing, and figure 18-9 shows the operation flowchart. figure 18-10 shows the operat ion of the buffer ram when 6 bytes of data are transmitted. figure 18-8. automatic transm ission mode operation timing interval sckan d7 soan intcsian tsfn d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 interval cautions 1. because, in the automatic transmission mode, th e automatic transmit/receive function reads data from the buffer ram a fter 1-byte transmission, an interval is inserted until the next transm ission. as the buffer ram read is performed at the same time as cpu processing, the interval is dependent upon the value of the adtin register. 2. when the tsfn bit is cleared , the soan pin becomes low level. 3. if cpu access to the buffer ram conflicts with csian read/write during the interval time, the inter val time becomes longer. remark n = 0, 1 chapter 18 clocked serial interface a (csia) with automatic transmit/receive function preliminary user?s manual u17702ej1v0ud 572 figure 18-9. automatic tr ansmission mode flowchart start write transmit data in buffer ram set adtpn register to the value (pointer value) obtained by subtracting 1 from the number of transmit data bytes set automatic transmission mode set csitn.atstan bit to 1 write transmit data from buffer ram to sioan register transmission operation adtpn register = adtcn register no tsfn bit = 0 no end yes yes increment pointer value software execution hardware execution software execution remark n = 0, 1 chapter 18 clocked serial interface a (csia) with automatic transmit/receive function preliminary user?s manual u17702ej1v0ud 573 in 6-byte transmission (csiman.atmn bit = 0, csiman.rxean bit = 0, csiman.txean bit = 1, csiman.aten bit = 1) in automatic transmission mode, buffer ram operates as follows. (i) when transmission is started (refer to figure 18-10 (a).) when the csitn.atstan bit is set to 1, transmit data 1 (t1) is transferred from the buffer ram to the sioan register. when transmission of the firs t byte is completed, the adtcn register is incremented. then transmit data 2 (t2) is transfe rred from the buffer ram to the sioan register. (ii) 4th byte transm ission point (refer to figure 18-10 (b).) transmission of the third byte is completed, and transmit data 4 (t4) is transferred from the buffer ram to the sioan register. when transmission of t he fourth byte is completed, the adtcn register is incremented. (iii) completion of transmission (refer to figure 18-10 (c).) when transmission of the sixth byte is completed, the interrupt request signal (intcsian) is generated, and the tfsn flag is cleared to 0. figure 18-10. buffer ram operation in 6-byte transmission (in automatic transmission mode) (1/2) (a) when transmission is started transmit data 6 (t6) transmit data 5 (t5) transmit data 4 (t4) transmit data 3 (t3) transmit data 2 (t2) transmit data 1 (t1) fffffe1fh fffffe05h fffffe00h sioan register not generated intcsian signal 0 adtcn register +1 5 adtpn register remarks 1. the above addresses are for csia0. fo r csia1, the addresses are fffffe20h to fffffe3fh. 2. n = 0, 1 chapter 18 clocked serial interface a (csia) with automatic transmit/receive function preliminary user?s manual u17702ej1v0ud 574 figure 18-10. buffer ram operation in 6-byte transmission (in automatic transmission mode) (2/2) (b) 4th byte transmission point transmit data 6 (t6) transmit data 5 (t5) transmit data 4 (t4) transmit data 3 (t3) transmit data 2 (t2) transmit data 1 (t1) fffffe1fh fffffe05h fffffe00h sioan register not generated intcsian signal 3 adtcn register +1 5 adtpn register (c) completion of transmission transmit data 6 (t6) transmit data 5 (t5) transmit data 4 (t4) transmit data 3 (t3) transmit data 2 (t2) transmit data 1 (t1) fffffe1fh fffffe05h fffffe00h sioan register generated intcsian signal 5 adtcn register 5 adtpn register remarks 1. the above addresses are for csia0. fo r csia1, the addresses are fffffe20h to fffffe3fh. 2. n = 0, 1 chapter 18 clocked serial interface a (csia) with automatic transmit/receive function preliminary user?s manual u17702ej1v0ud 575 (c) repeat transmission mode in this mode, data stored in the buffer ram is transmitted repeatedly. serial transfer is started when the csitn.atst an bit is set to 1 while the csiman.csiaen, csiman.aten, csiman.atmn, and csiman.txean bits are set to 1. unlike the basic transmission mode, after the spec ified number of bytes has been transmitted, the transmission/reception completion interrupt request si gnal (intcsian) is not generated, the adtcn register is reset to 0, and the buffe r ram contents are transmitted again. the repeat transmission mode operation timing is shown in figure 18-11, and the operation flowchart in figure 18-12. figure 18-13 shows the operation of the buffer ram w hen 6 bytes of data are transmitted in the repeat transmission mode. figure 18-11. repeat transmission mode operation timing d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 interval interval d7 d6 d5 sckan soan cautions 1. because, in the repeat transmi ssion mode, a read is performed on the buffer ram after the transmission of one byte, th e interval is included in the period up to the next transmission. as the buffer ram read is performed at the same time as cpu processing, the interval is dependent upon the adtin register. 2. if cpu access to the buffer ram conflicts with csia read/write during the interval time, the inter val time becomes longer. remark n = 0, 1 chapter 18 clocked serial interface a (csia) with automatic transmit/receive function preliminary user?s manual u17702ej1v0ud 576 figure 18-12. repeat transmission mode flowchart start write transmit data in buffer ram set adtpn register to the value (pointer value) obtained by subtracting 1 from the number of transmit data bytes set repeat transmission mode set csitn.atstan bit to 1 write transmit data from buffer ram to sioan register transmission operation adtpn register = adtcn register no yes increment pointer value software execution hardware execution reset adtcn register to 0 remark n = 0, 1 chapter 18 clocked serial interface a (csia) with automatic transmit/receive function preliminary user?s manual u17702ej1v0ud 577 in 6-byte transmission (csiman.atmn bit = 1, csiman.rxean bit = 0, csiman.txean bit = 1, csiman.aten bit = 1) in repeat transmission mode, buffer ram operates as follows. (i) when transmission is started (refer to figure 18-13 (a).) when the csitn.atstan bit is set to 1, transmit data 1 (t1) is transferred from the buffer ram to the sioan register. when transmission of the firs t byte is completed, the adtcn register is incremented. then transmit data 2 (t2) is transfe rred from the buffer ram to the sioan register. (ii) upon completion of transmission of 6 bytes (refer to figure 18-13 (b).) when transmission of the sixth byte is completed, the interrupt request signal (intcsian) is not generated. the adtcn register is reset to 0. (iii) 7th byte transmission poin t (refer to figure 18-13 (c).) transmit data 1 (t1) is transferred from the buffe r ram to sioan register again. when transmission of the first byte is completed, the adtcn regist er is incremented. then transmit data 2 (t2) is transferred from the buffer ram to the sioan register. figure 18-13. buffer ram operation in 6-byte transmission (in repeat transmission mode) (1/2) (a) when transmission is started transmit data 6 (t6) transmit data 5 (t5) transmit data 4 (t4) transmit data 3 (t3) transmit data 2 (t2) transmit data 1 (t1) fffffe1fh fffffe05h fffffe00h sioan register not generated intcsian signal 0 adtcn register +1 5 adtpn register remarks 1. the above addresses are for csia0. fo r csia1, the addresses are fffffe20h to fffffe3fh. 2. n = 0, 1 chapter 18 clocked serial interface a (csia) with automatic transmit/receive function preliminary user?s manual u17702ej1v0ud 578 figure 18-13. buffer ram operation in 6-byte transmission (in repeat transmission mode) (2/2) (b) upon completion of transmission of 6 bytes transmit data 6 (t6) transmit data 5 (t5) transmit data 4 (t4) transmit data 3 (t3) transmit data 2 (t2) transmit data 1 (t1) fffffe1fh fffffe05h fffffe00h sioan register not generated intcsian signal 5 adtcn register 5 adtpn register (c) 7th byte transmission point transmit data 6 (t6) transmit data 5 (t5) transmit data 4 (t4) transmit data 3 (t3) transmit data 2 (t2) transmit data 1 (t1) fffffe1fh fffffe05h fffffe00h sioan register not generated intcsian signal 0 adtcn register +1 5 adtpn register remarks 1. the above addresses are for csia0. fo r csia1, the addresses are fffffe20h to fffffe3fh. 2. n = 0, 1 chapter 18 clocked serial interface a (csia) with automatic transmit/receive function preliminary user?s manual u17702ej1v0ud 579 (d) data format in the data format, data is changed in synchronization with the sckan pin falling edge as shown in figure 18-14. the data length is fixed to 8 bits and the data trans fer direction can be switched by the specification of the csiman.diran bit. figure 18-14. format of csian transmit/receive data (a) msb-first (diran bit = 0) sckan sian do7 do6 do5 do4 do3 do2 do1 do0 soan di7 di6 di5 di4 di3 di2 di1 di0 (b) lsb-first (diran bit = 1) sckan sian do0 do1 do2 do3 do4 do5 do6 do7 soan di0 di1 di2 di3 di4 di5 di6 di7 remark n = 0, 1 chapter 18 clocked serial interface a (csia) with automatic transmit/receive function preliminary user?s manual u17702ej1v0ud 580 (e) automatic transmission/rece ption suspension and restart automatic transmission/reception can be temporarily suspended by setting the csitn.atstpn bit to 1. during 8-bit data transfer, the transmission/reception is not suspended. it is suspended upon completion of 8-bit data transfer. when suspended, the csisn.tsfn bit is cleared to 0 after transfer of the 8th bit. to restart automatic transmission/rec eption, set the csitn.atstan bit to 1. the remaining data can be transmitted in this way. cautions 1. if the idle instruction is executed during automatic transmissi on/reception, transfer is suspended and the idle mode is set if during 8-bit data transfer. when the idle mode is cleared, automatic transmission/ reception is restarted from the suspended point. 2. when suspending automa tic transmission/reception, do not change the operating mode to 3-wire serial i/o mode while the tsfn bit = 1. figure 18-15. automatic transmissi on/reception suspension and restart sckan soan d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 sian d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 restart command atstan bit = 1 suspend atstpn bit = 1 (suspend command) remark n = 0, 1 preliminary user?s manual u17702ej1v0ud 581 chapter 19 i 2 c bus to use the i 2 c bus function, set the p38/sda0, p39/scl0, p80/sda1, and p81/scl1 pins to n-ch open drain output as the al ternate function. in the v850es/kj2, two channels of i 2 c bus are provided. 19.1 selecting uart2 or i 2 c1 mode uart2 and i 2 c1 of the v850es/kj2 share pins, and therefore these inte rfaces cannot be used at the same time. when i 2 c1 is used, set with the pmc8 and pf c8 registers in advance (refer to 4.3.8 port 8 ). caution uart2 or i 2 c1 transmission/reception operations are not guaranteed if the mode is changed during transmission or reception. be sure to disable the operation of the unit that is not used. figure 19-1. selecting mode of uart2 or i 2 c1 7 0 pmc8 6 0 5 0 4 0 3 0 2 0 1 pmc81 0 pmc80 7 0 pfc8 6 0 5 0 4 0 3 0 2 0 1 pfc81 0 pfc80 after reset: 00h r/w address: fffff450h after reset: 00h r/w address: fffff470h pfc8n pmc8n operation mode 0 0 port i/o mode 0 1 uart2 mode 1 0 port i/o mode 1 1 i 2 c1 mode remark n = 0, 1 chapter 19 i 2 c bus 582 preliminary user?s manual u17702ej1v0ud 19.2 features the i 2 c0 and i 2 c1 have the following two modes. operation stop mode i 2 c (inter ic) bus mode (multimaster supported) (1) operation stop mode this mode is used when serial transfers are not per formed. it can therefor e be used to reduce power consumption. (2) i 2 c bus mode (multi master supported) this mode is used for 8-bit data transfers with several dev ices via two lines: a serial clock (scln) line and a serial data bus (sdan) line. this mode complies with the i 2 c bus format and the master device can generate ?start condition?, ?address?, ?transfer direction specification?, ? data?, and ?stop condition? data to the sl ave device, via the serial data bus. the slave device automatically detects these received st ate and data by hardware. this function can simplify the part of application progr am that controls the i 2 c bus. since the scln and sdan pins are used for n-ch open drain outputs, i 2 cn requires pull-up resistors for the serial clock line and the serial data bus line. remark n = 0, 1 chapter 19 i 2 c bus preliminary user?s manual u17702ej1v0ud 583 figure 19-2. block diagram of i 2 cn internal bus iic status register n (iicsn) iic control register n (iiccn) so latch iicen dq cln1, cln0 trcn dfcn dfcn sdan scln output control intiicn iic shift register n (iicn) iiccn.sttn, sptn iicsn.mstsn, excn, coin iicsn.mstsn, excn, coin lreln wreln spien wtimn acken sttn sptn mstsn aldn excn coin trcn ackdn stdn spdn internal bus cldn dadn smcn dfcn cln1 cln0 clxn iic clock select register n (iiccln) stcfn iicbsyn stcenn iicrsvn iic flag register n (iicfn) iic function expansion register n (iicxn) fxx clear slave address register n (svan) match signal set noise eliminator iic shift register n (iicn) data retention time correction circuit n-ch open-drain output ack detector ack generator start condition detector stop condition detector serial clock counter serial clock controller noise eliminator n-ch open-drain output start condition generator stop condition generator wakeup controller interrupt request signal generator serial clock wait controller bus status detector prescaler remark n = 0, 1 chapter 19 i 2 c bus 584 preliminary user?s manual u17702ej1v0ud a serial bus configuration example is shown below. figure 19-3. serial bus configuration example using i 2 c bus sda scl sda +v dd +v dd scl sda scl slave cpu3 address 3 sda scl slave ic address 4 sda scl slave ic address n master cpu1 slave cpu1 address 1 serial data bus serial clock master cpu2 slave cpu2 address 2 chapter 19 i 2 c bus preliminary user?s manual u17702ej1v0ud 585 19.3 configuration i 2 cn includes the following hardware. table 19-1. configuration of i 2 cn item configuration registers iic shift registers 0 and 1 (iic0, iic1) slave address registers 0 and 1 (sva0, sva1) control registers iic control registers 0 and 1 (iicc0, iicc1) iic status registers 0 and 1 (iics0, iics1) iic flag registers 0 and 1 (iiccf0, iiccf1) iic clock selection registers 0 and 1 (iiccl0, iiccl1) iic function expansion registers 0 and 1 (iicx0, iicx1) remark n = 0, 1 (1) iic shift registers 0 and 1 (iic0, iic1) the iicn register is used to convert 8-bit serial data to 8-bit parallel data and to convert 8-bit parallel data to 8- bit serial data. the iicn register can be used for both transmission and reception. write and read operations to the iicn r egister are used to control the act ual transmit and receive operations. the iicn register can be read or written in 8-bit units. after reset, iic0 and iic1 are cleared to 00h. (2) slave address registers 0 and 1 (sva0, sva1) the svan register sets local addresses when in slave mode. the svan register can be read or written in 8-bit units. after reset, sva0 and sva1 are cleared to 00h. (3) so latch the so latch is used to retain the sdan pin?s output level. (4) wakeup controller this circuit generates an interrupt r equest signal (intiicn) when the address re ceived by this register matches the address value set to the svan register or when an extension code is received. (5) prescaler this selects the sampling clock to be used. (6) serial clock counter this counter counts the serial clocks that are output and the serial clocks t hat are input during transmit/receive operations and is used to verify that 8-bit data was sent or received. (7) interrupt request signal generator this circuit controls the generation of interrupt request signals (intiicn). an i 2 c interrupt is generated followi ng either of two triggers. ? falling of the eighth or ninth clock of t he serial clock (set by iiccn.wtimn bit) ? interrupt request generated when a stop condition is detected (set by iiccn.spien bit) chapter 19 i 2 c bus 586 preliminary user?s manual u17702ej1v0ud (8) serial clock controller in master mode, this circuit generates the clo ck output via the scln pin from a sampling clock. (9) serial clock wait controller this circuit controls the wait timing. (10) ack generator, stop condition detector, start condition detector, and ack detector these circuits are used to gener ate and detect various statuses. (11) data hold time correction circuit this circuit generates the hold time for data corre sponding to the falling edge of the serial clock. (12) start condition generator this circuit generates a start condition when the iiccn.sttn bit is set. however, in the communication reservation disabled st atus (iicfn.iicrsvn bit = 1), when the bus is not released (iicfn.iicbsyn bit = 1), start condition requests are ignored and the iicfn.stcfn bit is set to 1. (13) stop condition generator a stop condition is generated when t he iicn.sptn bit is set (1). (14) bus status detector this circuit detects whether or not the bus is rel eased by detecting start conditions and stop conditions. however, as the bus status cannot be detected immediatel y following operation, the init ial status is set by the iicfn.stcenn bit. chapter 19 i 2 c bus preliminary user?s manual u17702ej1v0ud 587 19.4 registers i 2 c0 and i 2 c1 are controlled by t he following registers. iic control registers 0, 1 (iicc0, iicc1) iic status registers 0, 1 (iics0, iics1) iic flag registers 0, 1 (iicf0, iicf1) iic clock selection regist ers 0, 1 (iiccl0, iiccl1) iic function expansion registers 0, 1 (iicx0, iicx1) the following registers are also used. iic shift registers 0, 1 (iic0, iic1) slave address registers 0, 1 (sva0, sva1) remark for the alternate-function pin settings, refer to table 4-19 settings when port pins are used for alternate functions . (1) iic control registers 0, 1 (iicc0, iicc1) the iiccn register is used to enable/stop i 2 cn operations, set wait timing, and set other i 2 c operations. the iiccn register can be r ead or written in 8-bit or 1-bit units. however, set the spien, wtimn, and acken bits when the iicen bit is 0 or during the wait period. when setting the iicen bit from ?0? to ?1?, these bits can also be set at the same time. reset sets these registers to 00h. chapter 19 i 2 c bus 588 preliminary user?s manual u17702ej1v0ud (1/4) after reset: 00h r/w address: iicc0 fffffd82h, iicc1 fffffd92h <7> <6> <5> <4> <3> <2> <1> <0> iiccn iicen lreln wreln spien wtimn acken sttn sptn (n = 0, 1) iicen i 2 cn operation enable/dis able specification 0 stop operation. reset the iicsn register note 1 . stop internal operation. 1 enable operation. be sure to set this bit to 1 when the scln and sdan lines are high level. condition for clearing (iicen bit = 0) condition for setting (iicen bit = 1) ? cleared by instruction ? reset ? set by instruction lreln note 2 exit from communications 0 normal operation 1 this exits from the current communications and sets standby mode. this setting is automatically cleared to 0 after being executed. its uses include cases in which a locally irrelevant extension code has been received. the scln and sdan lines are set to high impedance. the sttn, sptn, iicsn.mstsn, iicsn.excn, iicsn.coi n, iicsn.trcn, iicsn.ackdn, and iicsn.stdn bits are cleared to 0. the standby mode following exit from communications remains in effect until the following communications entry conditions are met. ? after a stop condition is detected, restart is in master mode. ? an address match or extension code rec eption occurs after the start condition. condition for clearing (lreln bit = 0) condition for setting (lreln bit = 1) ? automatically cleared after execution ? reset ? set by instruction wreln note 2 wait cancellation control 0 do not cancel wait 1 cancel wait. this setting is automatica lly cleared to 0 after wait is canceled. condition for clearing (wreln bit = 0) condition for setting (wreln bit = 1) ? automatically cleared after execution ? reset ? set by instruction notes 1. the iicsn register, and the iicfn.stcfn, iicfn .iicbsyn, iiccln.cldn, and iiccln.dadn bits are reset. 2. this flag?s signal is invalid when the iicen bit = 0. caution if the i 2 cn operation is enabled (iicen bit = 1) wh en the scln line is high level and the sdan line is low level, the start condition is detected immediately. to avoid this, after enabling the i 2 cn operation, immediately set the lreln bit to 1 with a bit manipulation instruction. chapter 19 i 2 c bus preliminary user?s manual u17702ej1v0ud 589 (2/4) spien note enable/disable generation of interrupt request when stop condition is detected 0 disable 1 enable condition for clearing (spien bit = 0) condition for setting (spien bit = 1) ? cleared by instruction ? reset ? set by instruction wtimn note control of wait and interrupt request generation 0 interrupt request is generated at the eighth clock?s falling edge. master mode: after output of eight clocks, clock output is set to low level and wait is set. slave mode: after input of eight clocks, the clock is set to low level and wait is set for master device. 1 interrupt request is generated at the ninth clock?s falling edge. master mode: after output of nine clocks, clock output is set to low level and wait is set. slave mode: after input of nine clocks, the clock is set to low level and wait is set for master device. an interrupt is generated at the falling of the 9th clock during address transfer independently of the setting of this bit. the setting of this bit is valid when the address transfer is co mpleted. when in master mode, a wait is inserted at the falling edge of the ninth clock during address transfers. for a slave device that has received a local address, a wait is inserted at the falling edge of the ninth clock after ack is issued. however, when t he slave device has received an extension code, a wait is inserted at the falling edge of the eighth clock. condition for clearing (wtimn bit = 0) condition for setting (wtimn bit = 1) ? cleared by instruction ? reset ? set by instruction acken note acknowledgment control 0 disable acknowledgment. 1 enable acknowledgment. during t he ninth clock period, the sdan line is set to low level. the acken bit setting is invalid for address reception. in this case, ack is generated when the addresses match. however, the acken bit setting is valid for address reception of the extension code. condition for clearing (acken bit = 0) condition for setting (acken bit = 1) ? cleared by instruction ? reset ? set by instruction note this flag?s signal is invalid when the iicen bit = 0. chapter 19 i 2 c bus 590 preliminary user?s manual u17702ej1v0ud (3/4) sttn start condition trigger 0 do not generate a start condition. 1 when bus is released (in stop mode): generate a start condition (for starting as master). the sdan line is changed from high level to low level while the scln line is high level and then the start c ondition is generated. next, after the rated amount of time has elapsed, the scln line is changed to low level (wait status). when a third party is communicating ? when communication reservation functi on is enabled (iicfn.iicrsvn bit = 0) functions as the start condition reservation flag. when set to 1, automatically generates a start condition after the bus is released. ? when communication reservation functi on is disabled (iicrsvn bit = 1) the iicfn.stcfn bit is set to 1 and the informati on set (1) to the sttn bit is cleared. no start condition is generated. in the wait state (when master device): generates a restart condition after releasing the wait. cautions concerning set timing for master reception: cannot be set to 1 during transfer. can be set to 1 only when the acken bit has been cleared to 0 and slave has been notified of final reception. for master transmission: a start condition may not be generat ed normally during the ack period. set to 1 during the wait period that follows output of the ninth clock. ? cannot be set to 1 at the same time as the sptn bit. ? when the sttn bit is set to 1, setting the sttn bit to 1 again is disabled until the setting is cleared to 0. condition for clearing (sttn bit = 0) condition for setting (sttn bit = 1) ? when the sttn bit is set to 1 in the communication reservation disabled status ? cleared when start conditi on is generated by master device ? when the lreln bit = 1 (e xit from communications) ? when the iicen bit = 0 (operation stop) ? reset ? set by instruction remark the sttn bit is 0 if it is read after data setting. chapter 19 i 2 c bus preliminary user?s manual u17702ej1v0ud 591 (4/4) sptn stop condition trigger 0 stop condition is not generated. 1 stop condition is generated (terminati on of master device?s transfer). after the sdan line goes to low level, either set the scln line to high level or wait until the scln pin goes to high level. next, after the rated amount of time has elapsed, the sdan line is changed from low level to high level and a stop condition is generated. cautions concerning setting timing for master reception: cannot be set to 1 during transfer. can be set to 1 only when the acken bit has been cleared to 0 and during the wait period after slave has been notified of final reception. for master transmission: a stop condition may not be generated normally during the ack period. set to 1 during the wait period that follows output of the ninth clock. ? cannot be set to 1 at the same time as the sttn bit. ? the sptn bit can be set to 1 only when in master mode note . ? when the wtimn bit has been cleared to 0, if the sptn bit is set to 1 during the wait period that follows output of eight clocks, note that a stop condition will be generat ed during the high-level period of the ninth clock. the wtimn bit should be changed from 0 to 1 during the wait period following output of eight clocks, and the sptn bit should be set to 1 during the wait peri od that follows output of the ninth clock. ? when the sptn bit is set to 1, setting the sptn bit to 1 again is disabled until the setting is cleared to 0. condition for clearing (sptn bit = 0) condition for setting (sptn bit = 1) ? cleared by loss in arbitration ? automatically cleared after stop condition is detected ? when the lreln bit = 1 (e xit from communications) ? when the iicen bit = 0 (operation stop) ? reset ? set by instruction note set the sptn bit to 1 only in master mode. however, the sptn bit must be set to 1 and a stop condition generated before the first stop condition is detected follo wing the switch to operation enable status. for details, refer to 19.15 cautions . caution when the iicsn.trcn bit is set to 1, th e wreln bit is set to 1 during the ninth clock and wait is canceled, after which the trcn bi t is cleared to 0 and the sdan line is set to high impedance. remark the sptn bit is 0 if it is read after data setting. chapter 19 i 2 c bus 592 preliminary user?s manual u17702ej1v0ud (2) iic status registers 0, 1 (iics0, iics1) the iicsn register indica tes the status of the i 2 cn bus. the iicsn register is read-only, in 8-bit or 1-bit units. however, the iicsn register can only be read when t he iiccn.sttn bit is 1 or during the wait period. reset sets these registers to 00h. caution when the main clock is stopped and the cpu is operating on the subclock, do not access the iicsn register. for details, refer to 3.4.8 (1) (b). (1/3) after reset: 00h r address: iics0 fffffd86h, iics1 fffffd96h <7> <6> <5> <4> <3> <2> <1> <0> iicsn mstsn aldn excn coin trcn ackdn stdn spdn (n = 0, 1) mstsn master device status 0 slave device status or communication standby status 1 master device communication status condition for clearing (mstsn bit = 0) condition for setting (mstsn bit = 1) ? when a stop condition is detected ? when the aldn bit = 1 (arbitration loss) ? cleared by the iiccn.lreln bit = 1 (exit from communications) ? when the iiccn.iicen bit changes from 1 to 0 (operation stop) ? reset ? when a start condition is generated aldn detection of arbitration loss 0 this status means either that there was no arbitr ation or that the arbitration result was a ?win?. 1 this status indicates the arbitration result was a ?loss?. the mstsn bit is cleared to 0. condition for clearing (aldn bit = 0) condition for setting (aldn bit = 1) ? automatically cleared after the iicsn register is read note ? when the iicen bit changes from 1 to 0 (operation stop) ? reset ? when the arbitration result is a ?loss?. note this register is also cleared when a bit manipulation instruction is executed for bits other than the iicsn register. chapter 19 i 2 c bus preliminary user?s manual u17702ej1v0ud 593 (2/3) excn detection of extension code reception 0 extension code was not received. 1 extension code was received. condition for clearing (excn bit = 0) condition for setting (excn bit = 1) ? when a start condition is detected ? when a stop condition is detected ? cleared by the lreln bit = 1 (exit from communications) ? when the iicen bit changes from 1 to 0 (operation stop) ? reset ? when the higher four bits of the received address data is either ?0000? or ?1111? (s et at the rising edge of the eighth clock). coin detection of matching addresses 0 addresses do not match. 1 addresses match. condition for clearing (coin bit = 0) condition for setting (coin bit = 1) ? when a start condition is detected ? when a stop condition is detected ? cleared by the lreln bit = 1 (exit from communications) ? when the iicen bit changes from 1 to 0 ? reset ? when the received address matches the local address (svan register) (set at the rising edge of the eighth clock). trcn detection of transmit/receive status 0 receive status (other than transmit status ). the sdan line is set for high impedance. 1 transmit status. the value in the so latch is enabled for output to the sdan line (valid starting at the rising edge of the first byte?s ninth clock). condition for clearing (trcn bit = 0) condition for setting (trcn bit = 1) ? when a stop condition is detected ? cleared by the lreln bit = 1 (exit from communications) ? when the iicen bit changes from 1 to 0 (operation stop) ? cleared by the iiccn.wreln bit = 1 note (wait release) ? when the aldn bit changes from 0 to 1 (arbitration loss) ? reset master ? when ?1? is output to the first byte?s lsb (transfer direction specification bit) slave ? when a start condition is detected when not used for communication master ? when a start condition is generated ? when ?0? is output to the first byte?s lsb (transfer direction specification bit) slave ? when ?1? is input in the first byte?s lsb (transfer direction specification bit) note the iicsn.trcn bit is cleared to 0 and the sdan line become high impedance when the iiccn.wreln bit is set to 1 and wait state is rel eased at the ninth clock with the trcn bit = 1. chapter 19 i 2 c bus 594 preliminary user?s manual u17702ej1v0ud (3/3) ackdn detection of ack 0 ack was not detected. 1 ack was detected. condition for clearing (ackdn bit = 0) condition for setting (ackdn bit = 1) ? when a stop condition is detected ? at the rising edge of the next byte?s first clock ? cleared by the lreln bit = 1 (exit from communications) ? when the iicen bit changes from 1 to 0 (operation stop) ? reset ? after the sdan pin is set to low level at the rising edge of the scln pin?s ninth clock stdn detection of start condition 0 start condition was not detected. 1 start condition was detected. this indicates that the address transfer period is in effect condition for clearing (stdn bit = 0) condition for setting (stdn bit = 1) ? when a stop condition is detected ? at the rising edge of the next byte?s first clock following address transfer ? cleared by the lreln bit = 1 (exit from communications) ? when the iicen bit changes from 1 to 0 (operation stop) ? reset ? when a start condition is detected spdn detection of stop condition 0 stop condition was not detected. 1 stop condition was detected. the master device?s communication is terminated and the bus is released. condition for clearing (spdn bit = 0) condition for setting (spdn bit = 1) ? at the rising edge of the address transfer byte?s first clock following setting of this bit and detection of a start condition ? when the iicen bit changes from 1 to 0 (operation stop) ? reset ? when a stop condition is detected chapter 19 i 2 c bus preliminary user?s manual u17702ej1v0ud 595 (3) iic flag registers 0, 1 (iicf0, iicf1) iicf0 and iicf1 are registers t hat set the operation mode of i 2 cn and indicate the status of the i 2 c bus. these registers can be read or writt en in 8-bit or 1-bit units. howeve r, the stcfn and iicbsyn bits are read- only. the iicrsvn bit can be used to enable/disable t he communication reservation function (refer to 19.14 communication reservation ). the stcenn bit can be used to set the in itial value of the iicbsyn bit (refer to 19.15 cautions ). the iicrsvn and stcenn bits can be written only when the operation of i 2 cn is disabled (iiccn.iicen bit = 0). when operation is enabled, the iic fn register can be read. reset sets these registers to 00h. chapter 19 i 2 c bus 596 preliminary user?s manual u17702ej1v0ud <7> stcfn condition for clearing (stcfn bit = 0) clearing by setting the sttn bit = 1 when the iicen bit = 0 reset condition for setting (stcfn bit = 1) generating start condition unsuccessful and the sttn bit cleared to 0 when communication reservation is disabled (iicrsvn bit = 1). stcfn 0 1 generate start condition start condition generation unsuccessful: clear sttn flag iiccn.sttn clear flag iicfn (n = 0, 1) <6> iicbsyn 5 0 4 0 3 0 2 0 <1> stcenn <0> iicrsvn after reset: 00h r/w note address: iicf0 fffffd8ah, iicf1 fffffd9ah condition for clearing (iicbsyn bit = 0) detection of stop condition when the iicen bit = 0 reset condition for setting (iicbsyn bit = 1) detection of start condition setting of the iicen bit when the stcenn bit = 0 iicbsyn 0 1 bus release status (initial communication status when stcenn bit = 1) bus communication status (initial communication status when stcenn bit = 0) i 2 cn bus status flag condition for clearing (stcenn bit = 0) detection of start condition reset condition for setting (stcenn bit = 1) setting by instruction stcenn 0 1 after operation is enabled (iicen bit = 1), enable generation of a start condition upon detection of a stop condition. after operation is enabled (iicen bit = 1), enable generation of a start condition without detecting a stop condition. initial start enable trigger condition for clearing (iicrsvn bit = 0) clearing by instruction reset condition for setting (iicrsvn bit = 1) setting by instruction iicrsvn 0 1 enable communication reservation disable communication reservation communication reservation function disable bit note bits 6 and 7 are read-only bits. cautions 1. write to the stcenn bit only wh en the operation is stopped (iicen bit = 0). 2. as the bus release status (iicbsyn bit = 0) is recognized regardless of the actual bus status when the stcenn bit = 1, when ge nerating the first start condition (sttn bit = 1), it is necessary to verify that no third pa rty communications are in progress in order to prevent such communications from being destroyed. 3. write to the iicrsvn bit only when the operation is stopped (iicen bit = 0). chapter 19 i 2 c bus preliminary user?s manual u17702ej1v0ud 597 (4) iic clock selection regist ers 0, 1 (iiccl0, iiccl1) the iiccln register is used to set the transfer clock for the i 2 c bus. the iiccln register can be r ead or written in 8-bit or 1-bit units. however, the cldn and dadn bits are read- only. the smcn, cln1 and cln0 bits are set in combination with the iicxn.clxn bit (refer to 19.4 (6) i 2 cn transfer clock setting method ). set the iiccln register when the iiccn.iicen bit = 0. reset sets these registers to 00h. after reset: 00h r/w note address: iiccl0 fffffd84h, iiccl1 fffffd94h 7 6 <5> <4> 3 2 1 0 iiccln 0 0 cldn dadn smcn dfcn cln1 cln0 (n = 0, 1) cldn detection of scln pin level (valid only when iiccn.iicen bit = 1) 0 the scln pin was detected at low level. 1 the scln pin was detected at high level. condition for clearing (cldn bit = 0) condition for setting (cldn bit = 1) ? when the scln pin is at low level ? when the iicen bit = 0 (operation stop) ? reset ? when the scln pin is at high level dadn detection of sdan pin level (valid only when iicen bit = 1) 0 the sdan pin was detected at low level. 1 the sdan pin was detected at high level. condition for clearing (dadn bit = 0) condition for setting (dadn bit = 1) ? when the sdan pin is at low level ? when iicen bit = 0 (operation stop) ? reset ? when the sdan pin is at high level smcn operation mode switching 0 operates in standard mode. 1 operates in high-speed mode. dfcn digital filter operation control 0 digital filter off. 1 digital filter on. digital filter can be used only in high-speed mode. in high-speed mode, the transfer clock does not vary regardless of dfcn bit set/clear. the digital filter is used for noi se elimination in high-speed mode. note bits 4 and 5 are read-only bits. chapter 19 i 2 c bus 598 preliminary user?s manual u17702ej1v0ud (5) iic function expansion regi sters 0, 1 (iicx0, iicx1) these registers set the function expansion of i 2 cn (valid only in high-speed mode). these registers can be read or written in 8-bit or 1-bit units. the clxn bit is set in combination with the iiccln.smcn, iiccln.cln1, and iiccln.cln0 bits (refer to 19.4 (6) i 2 cn transfer clock setting method ). set the iicxn register when the iiccn.iicen bit = 0. reset sets these registers to 00h. after reset: 00h r/w address: iicx0 fffffd85h, iicx1 fffffd95h 7 6 5 4 3 2 1 <0> iicxn 0 0 0 0 0 0 0 clxn (n = 0, 1) (6) i 2 cn transfer clock setting method the i 2 cn transfer clock frequency (f scl ) is calculated using the following expression (n = 0, 1). f scl = 1/(m t + t r + t f ) m = 12, 24, 48, 54, 86, 88, 172, 198 (refer to table 19-2 selection clock setting .) t: 1/f xx t r : scln rise time t f : scln fall time for example, the i 2 cn transfer clock frequency (f scl ) when f xx = 20 mhz, m = 54, t r = 200 ns, and t f = 50 ns is calculated using following expression. f scl = 1/(54 50 ns + 200 ns + 50 ns) ? 339 khz m t + t r + t f m/2 t t f t r m/2 t scln scln inversion scln inversion scln inversion the selection clock is set using a combination of the iiccln.smcn, iiccln.cln1, and iiccln.cln0 bits and the iicxn.clxn bit. chapter 19 i 2 c bus preliminary user?s manual u17702ej1v0ud 599 table 19-2. selection clock setting iicxn iiccln bit 0 bit 3 bit 1 bit 0 clxn smcn cln1 cln0 selection clock transfer clock (f xx /m) settable internal system clock frequency (f xx ) range operation mode 0 0 0 0 f xx /2 f xx /88 4.0 mhz to 8.38 mhz 0 0 0 1 f xx /2 f xx /172 8.38 mhz to 16.76 mhz 0 0 1 0 f xx f xx /86 4.19 mhz to 8.38 mhz 0 0 1 1 f xx /3 f xx /198 16.0 mhz to 19.8 mhz normal mode (smcn bit = 0) 0 1 0 x f xx /2 f xx /48 8 mhz to 16.76 mhz 0 1 1 0 f xx f xx /24 4 mhz to 8.38 mhz 0 1 1 1 f xx/ 3 f xx /54 16 mhz to 20 mhz high-speed mode (smcn bit = 1) 1 0 x x setting prohibited 1 1 0 x f xx /2 f xx /24 8.00 mhz to 8.38 mhz 1 1 1 0 f xx f xx /12 4.00 mhz to 4.19 mhz high-speed mode (smcn bit = 1) 1 1 1 1 setting prohibited remarks 1. n = 0, 1 2. x: don?t care chapter 19 i 2 c bus 600 preliminary user?s manual u17702ej1v0ud (7) iic shift registers 0, 1 (iic0, iic1) the iicn register is used for serial transmission/reception (shift operations) t hat is synchronized with the serial clock. the iicn register can be read or writt en in 8-bit units, but data should not be written to the iicn register during a data transfer. access (read/write) the iicn register only during the wait period. accessi ng this register in communication states other than the wa it period is prohibited. howe ver, for the master device, t he iicn register can be written once only after the transmission trigger bit (iiccn.sttn bit) has been set to 1. when the iicn register is written during wait, the wait is cancelled and dat a transfer is started. reset sets these registers to 00h. after reset: 00h r/w address: iic0 fffffd80h, iic1 fffffd90h 7 6 5 4 3 2 1 0 iicn (n = 0, 1) (8) slave address registers 0, 1 (sva0, sva1) the svan register holds the i 2 c bus?s slave addresses. however, rewriting these register s is prohibited when the iicsn.stdn bit = 1 (start condition detection). the svan register can be read or written in 8-bit units, but bit 0 should be fixed as 0. reset sets these registers to 00h. after reset: 00h r/w address: sva0 fffffd83h, sva1 fffffd93h 7 6 5 4 3 2 1 0 svan 0 (n = 0, 1) chapter 19 i 2 c bus preliminary user?s manual u17702ej1v0ud 601 19.5 functions 19.5.1 pin configuration the serial clock pin (scln) and serial data bus pi n (sdan) are configured as follows (n = 0, 1). scln .............. this pin is used for serial clock input and output. this pin is an n-ch open-drain output for both ma ster and slave devices. input is schmitt input. sdan .............. this pi n is used for serial data input and output. this pin is an n-ch open-drain output for both ma ster and slave devices. input is schmitt input. since outputs from the serial clock line and the serial dat a bus line are n-ch open-drain outputs, an external pull-up resistor is required. figure 19-4. pin configuration diagram v dd scln sdan scln sdan v dd clock output master device (clock input) data output data input (clock output) clock input data output data input slave device chapter 19 i 2 c bus 602 preliminary user?s manual u17702ej1v0ud 19.6 i 2 c bus definitions and control methods the following section describes the i 2 c bus?s serial data communication fo rmat and the status generated by the i 2 c bus. the transfer timing for the ?start condition?, ?addre ss?, ?transfer direction spec ification?, ?data?, and ?stop condition? generated via the i 2 c bus?s serial data bus is shown below. figure 19-5. i 2 c bus?s serial data transfer timing 1 to 7 8 9 1 to 8 9 1 to 8 9 scln sdan start condition address r/w ack data data stop condition ack ack the master device generates the start condition, slave address, and stop condition. ack can be generated by either the master or slave device (normally, it is generated by the devic e that receives 8- bit data). the serial clock (scln) is continuously output by the master devic e. however, in the sl ave device, the scln?s low- level period can be extended and a wait can be inserted (n = 0, 1). 19.6.1 start condition a start condition is met when the scln pin is at high level and the sdan pin changes from high level to low level. the start conditions for the scln pin and sdan pin are generat ed when the master device starts a serial transfer to the slave device. start conditions can be detected when the device is used as a slave (n = 0, 1). figure 19-6. start conditions h scln sdan a start condition is generated when the iiccn.sttn bit is set to 1 after a stop condition has been detected (iicsn.spdn bit = 1). when a start condition is detected, iicsn.stdn bit is set to 1. chapter 19 i 2 c bus preliminary user?s manual u17702ej1v0ud 603 19.6.2 addresses the 7 bits of data that follow the st art condition are defined as an address. an address is a 7-bit data segment that is output in order to select one of t he slave devices that are connected to the master device via bus lines. t herefore, each slave devic e connected via the bus lines must have a unique address. the slave devices include hardware that detects the start condition and che cks whether or not the 7-bit address data matches the data values stored in the svan register. if the address dat a matches the svan values, the slave device is selected and communicates with the master device until t he master device generates a start condition or stop condition (n = 0, 1). figure 19-7. address address scln 1 sdan intiicn note 23456789 ad6 ad5 ad4 ad3 ad2 ad1 ad0 r/w note the interrupt request signal (int iicn) is generated if a local addre ss or extension code is received during slave device operation. remark n = 0, 1 the slave address and the eighth bit, which specif ies the transfer direction as described in 19.6.3 transfer direction specification below, are together written to the iicn regi ster and are then output. received addresses are written to the iicn register. the slave address is assigned to the hi gher 7 bits of the iicn register. chapter 19 i 2 c bus 604 preliminary user?s manual u17702ej1v0ud 19.6.3 transfer di rection specification in addition to the 7-bit address data, the master device sends 1 bit that specifies the transfe r direction. when this transfer direction specification bit has a value of 0, it indicates that the mast er device is transmitting data to a slave device. when the transfer direction specif ication bit has a value of 1, it indica tes that the master device is receiving data from a slave device. figure 19-8. transfer direction specification scln 1 sdan intiicn 23456789 ad6 ad5 ad4 ad3 ad2 ad1 ad0 r/w transfer direction specification note note the interrupt request signal (int iicn) is generated if a local addre ss or extension code is received during slave device operation. remark n = 0, 1 chapter 19 i 2 c bus preliminary user?s manual u17702ej1v0ud 605 19.6.4 ack ack is used to confirm the serial data stat us of the transmitting and receiving devices. the receiving device returns ack for every 8 bits of data it receives. the transmitting device normally receives ack after transmi tting 8 bits of data. when ack is returned from the receiving device, the reception is j udged as normal and processing continues. t he detection of ack is confirmed with the iicsn.ackdn bit. when the master device is the receivi ng device, after receiving the final dat a, it does not return ack and generates the stop condition. when the slave dev ice is the receiving device and does not return ack, the master device generates either a stop condition or a rest art condition, and then stops the current transmission. failure to return ack may be caused by the following factors. (a) reception was not performed normally. (b) the final data was received. (c) the receiving device (slave) does not exist for the specified address. when the receiving device sets the sdan line to low level during the ninth clo ck, ack is generated (normal reception). when the iiccn.acken bit is set to 1, automatic ac k generation is enabled. trans mission of the eighth bit following the 7 address data bits causes the iicsn.trcn bit to be set. normally, set the acken bit to 1 for reception (trcn bit = 0). when the slave device is receiving (when trcn bit = 0), if the slave device cannot rece ive data or does not need to receive any more data, clear the acken bit to 0 to indi cate to the master that no more data can be received. similarly, when the master device is receiving (when trcn bit = 0) and the subsequent data is not needed, clear the acken bit to 0 to prevent ack from being generated. th is notifies the slave device (transmitting device) of the end of the data transmissi on (transmission stopped). figure 19-9. ack scln 1 sdan 23456789 ad6 ad5 ad4 ad3 ad2 ad1 ad0 r/w ack remark n = 0, 1 when the local address is received, ack is automatically generated regardless of the value of the acken bit. no ack is generated if the received addre ss is not a local address (nack). when receiving the extension code, set the acken bit to 1 in advance to generate ack. the ack generation method during data rec eption is based on the wait timing setti ng, as described by the following. ? when 8-clock wait is selected (iiccn.wtimn bit = 0): ack is generated at the falling edge of t he scl0n pin?s eighth clock if the acken bit is set to 1 before the wait state cancellation. ? when 9-clock wait is selected (iiccn.wtimn bit = 1): ack is generated if the acken bit is set to 1 in advance. remark n = 0, 1 chapter 19 i 2 c bus 606 preliminary user?s manual u17702ej1v0ud 19.6.5 stop condition when the scln pin is at high level, changing the sdan pi n from low level to high level generates a stop condition (n = 0, 1). a stop condition is generated when serial transfer from the master device to the slave device has been completed. stop conditions can be detected when the device is used as a slave. figure 19-10. stop condition h scln sdan remark n = 0, 1 a stop condition is generated when the ii ccn.sptn bit is set to 1. when the stop condition is detected, the iicsn.spdn bit is set to 1 and the interrupt request signal (i ntiicn) is generated when the iiccn .spien bit is set to 1. chapter 19 i 2 c bus preliminary user?s manual u17702ej1v0ud 607 19.6.6 wait state the wait state is used to not ify the communication partner t hat a device (master or slave) is preparing to transmit or receive data (i.e., is in a wait state). setting the scln pin to low level notifies the communication partner of the wait status. when wait status has been canceled for both the master and slave devices, the next data transfer can begin (n = 0, 1). figure 19-11. wait state (1/2) (a) when master device has a nine-clock wa it and slave device has an eight-clock wait (master: transmission, slave: reception, and iiccn.acken bit = 1) scln 6 sdan 78 9 123 scln iicn 6 h 78 123 d2 d1 d0 ack d7 d6 d5 9 iicn scln acken master master returns to high impedance but slave is in wait state (low level). wait after output of ninth clock. iicn data write (cancel wait) slave wait after output of eighth clock. ffh is written to iicn register or iiccn.wreln bit is set to 1. transfer lines wait state from slave wait state from master remark n = 0, 1 chapter 19 i 2 c bus 608 preliminary user?s manual u17702ej1v0ud figure 19-11. wait state (2/2) (b) when master and slave devices both have a nine-clock wait (master: transmission, slave: reception, and acken = 1) scln 6 sdan 789 123 scln iicn 6 h 78 1 23 d2 d1 d0 ack d7 d6 d5 9 iicn scln acken master master and slave both wait after output of ninth clock. iicn data write (cancel wait) slave ffh is written to iicn register or wreln bit is set to 1. generated according to previously set acken bit value transfer lines wait state from master and slave wait state from slave remark n = 0, 1 a wait state is automatically generated after a start condition is generated. moreover, a wait stat e is automatically generated depending on the setting of the iiccn.wtimn bit. normally, when the iiccn.wreln bit is set to 1 or when ffh is written to the iicn regi ster, the wait status is canceled and the transmitting side writes data to t he iicn register to cancel the wait status. the master device can also c ancel the wait status via ei ther of the following methods. by setting the iiccn.sttn bit to 1 by setting the iiccn.sptn bit to 1 chapter 19 i 2 c bus preliminary user?s manual u17702ej1v0ud 609 19.6.7 wait state cancellation method in the case of i 2 cn, wait state can be canceled normally in the following ways (n = 0 to 2). ? by writing data to the iicn register ? by setting the iiccn.wreln bit to 1 (wait state cancellation) ? by setting the iiccn.sttn bit to 1 (start condition generation) note ? by setting the iiccn.sptn bit to 1 (stop condition generation) note note master only if any of these wait state canc ellation actions is performed, i 2 cn will cancel wait state and restart communication. when canceling wait state and s ending data (including address), writ e data to the iicn register. to receive data after canceling wait state, or to complete data transmission, set the wreln bit to 1. to generate a restart condition after canceli ng wait state, set the sttn bit to 1. to generate a stop condition after canceling wait state, set the sptn bit to 1. execute cancellation only once for each wait state. for example, if data is written to t he iicn register following wait state canc ellation by setting the wreln bit to 1, conflict between the sdan line change timing and iicn register write timing may resu lt in the data output to the sdan line may be incorrect. even in other operations, if communication is stopped halfway, clearing the iiccn.iicen bit to 0 will stop communication, enabling wait state to be cancelled. if the i 2 c bus dead-locks due to noise, etc., setting the iiccn.lre ln bit to 1 causes the communication operation to be exited, enabling wait st ate to be cancelled. chapter 19 i 2 c bus 610 preliminary user?s manual u17702ej1v0ud 19.7 i 2 c interrupt request signals (intiicn) the following shows the value of the iic sn register at the intiicn interr upt request signal generation timing and at the intiicn signal timing. remarks 1. st: start condition ad6 to ad0: address r/w: transfer direction specification ack: acknowledge d7 to d0: data sp: stop condition 2. n = 0, 1 chapter 19 i 2 c bus preliminary user?s manual u17702ej1v0ud 611 19.7.1 master device operation (1) start ~ address ~ data ~ data ~ stop (normal transmission/reception) <1> when iiccn.wtimn bit = 0 iiccn.sptn bit = 1 st ad6 to ad0 r/w ack d7 to d0 ack d7 to d0 ack sp s 1 s 2 s 3 s 4 ? 5 s 1: iicsn register = 1000x110b s 2: iicsn register = 1000x000b s 3: iicsn register = 1000x000b (wtimn bit = 1 note ) s 4: iicsn register = 1000xx00b ? 5: iicsn register = 00000001b note to generate a stop condition, set the wtimn bit to 1 and change the timing of the generation of the interrupt request signal (intiicn). remarks 1. s : always generated ? : generated only when iiccn.spien bit = 1 x: don?t care 2. n = 0, 1 <2> when wtimn bit = 1 sptn bit = 1 st ad6 to ad0 r/w ack d7 to d0 ack d7 to d0 ack sp s 1 s 2 s 3 ? 4 s 1: iicsn register = 1000x110b s 2: iicsn register = 1000x100b s 3: iicsn register = 1000xx00b ? 4: iicsn register = 00000001b remarks 1. s : always generated ? : generated only when spien bit = 1 x: don?t care 2. n = 0, 1 chapter 19 i 2 c bus 612 preliminary user?s manual u17702ej1v0ud (2) start ~ address ~ data ~ star t ~ address ~ data ~ stop (restart) <1> when wtimn bit = 0 iiccn.sttn bit = 1 sptn bit = 1 st ad6 to ad0 r/w ack d7 to d0 ack st ad6 to ad0 r/w ack d7 to d0 ack sp s 1 s 2 s 3 s 4 s 5 s 6 ? 7 s 1: iicsn register = 1000x110b s 2: iicsn register = 1000x000b (wtimn bit = 1 note 1 ) s 3: iicsn register = 1000xx00b (wtimn bit = 0 note 2 ) s 4: iicsn register = 1000x110b s 5: iicsn register = 1000x000b (wtimn bit = 1 note 3 ) s 6: iicsn register = 1000xx00b ? 7: iicsn register = 00000001b notes 1. to generate a start condition, set the wt imn bit to 1 and change the timing of the generation of the interrupt request signal (intiicn). 2. clear the wtimn bit to 0 to make the settings original. 3. to generate a stop condition, set the wt imn bit to 1 and change the timing of the generation of the interrupt request signal (intiicn). remarks 1. s : always generated ? : generated only when spien bit = 1 x: don?t care 2. n = 0, 1 <2> when wtimn bit = 1 sttn bit = 1 sptn bit = 1 st ad6 to ad0 r/w ack d7 to d0 ack st ad6 to ad0 r/w ack d7 to d0 ack sp s 1 s 2 s 3 s 4 ? 5 s 1: iicsn register = 1000x110b s 2: iicsn register = 1000xx00b s 3: iicsn register = 1000x110b s 4: iicsn register = 1000xx00b ? 5: iicsn register = 00000001b remarks 1. s : always generated ? : generated only when spien bit = 1 x: don?t care 2. n = 0, 1 chapter 19 i 2 c bus preliminary user?s manual u17702ej1v0ud 613 (3) start ~ code ~ data ~ data ~ stop (extension code transmission) <1> when wtimn bit = 0 sptn bit = 1 st ad6 to ad0 r/w ack d7 to d0 ack d7 to d0 ack sp s 1 s 2 s 3 s 4 ? 5 s 1: iicsn register = 1010x110b s 2: iicsn register = 1010x000b s 3: iicsn register = 1010x000b (wtimn bit = 1 note ) s 4: iicsn register = 1010xx00b ? 5: iicsn register = 00000001b note to generate a stop condition, set the wtimn bit to 1 and change the timing of the generation of the interrupt request signal (intiicn). remarks 1. s : always generated ? : generated only when spien bit = 1 x: don?t care 2. n = 0, 1 <2> when wtimn bit = 1 sptn bit = 1 st ad6 to ad0 r/w ack d7 to d0 ack d7 to d0 ack sp s 1 s 2 s 3 ? 4 s 1: iicsn register = 1010x110b s 2: iicsn register = 1010x100b s 3: iicsn register = 1010xx00b ? 4: iicsn register = 00000001b remarks 1. s : always generated ? : generated only when spien bit = 1 x: don?t care 2. n = 0, 1 chapter 19 i 2 c bus 614 preliminary user?s manual u17702ej1v0ud 19.7.2 slave device operation (when recei ving slave address data (address match)) (1) start ~ address ~ data ~ data ~ stop <1> when iiccn.wtimn bit = 0 st ad6 to ad0 r/w ack d7 to d0 ack d7 to d0 ack sp s 1 s 2 s 3 ? 4 s 1: iicsn register = 0001x110b s 2: iicsn register = 0001x000b s 3: iicsn register = 0001x000b ? 4: iicsn register = 00000001b remarks 1. s : always generated ? : generated only when iiccn.spien bit = 1 x: don?t care 2. n = 0, 1 <2> when wtimn bit = 1 st ad6 to ad0 r/w ack d7 to d0 ack d7 to d0 ack sp s 1 s 2 s 3 ? 4 s 1: iicsn register = 0001x110b s 2: iicsn register = 0001x100b s 3: iicsn register = 0001xx00b ? 4: iicsn register = 00000001b remarks 1. s : always generated ? : generated only when spien bit = 1 x: don?t care 2. n = 0, 1 chapter 19 i 2 c bus preliminary user?s manual u17702ej1v0ud 615 (2) start ~ address ~ data ~ start ~ address ~ data ~ stop <1> when wtimn bit = 0 (after restart, address match) st ad6 to ad0 r/w ack d7 to d0 ack st ad6 to ad0 r/w ack d7 to d0 ack sp s 1 s 2 s 3 s 4 ? 5 s 1: iicsn register = 0001x110b s 2: iicsn register = 0001x000b s 3: iicsn register = 0001x110b s 4: iicsn register = 0001x000b ? 5: iicsn register = 00000001b remarks 1. s : always generated ? : generated only when spien bit = 1 x: don?t care 2. n = 0, 1 <2> when wtimn bit = 1 (after restart, address match) st ad6 to ad0 r/w ack d7 to d0 ack st ad6 to ad0 r/w ack d7 to d0 ack sp s 1 s 2 s 3 s 4 ? 5 s 1: iicsn register = 0001x110b s 2: iicsn register = 0001xx00b s 3: iicsn register = 0001x110b s 4: iicsn register = 0001xx00b ? 5: iicsn register = 00000001b remarks 1. s : always generated ? : generated only when spien bit = 1 x: don?t care 2. n = 0, 1 chapter 19 i 2 c bus 616 preliminary user?s manual u17702ej1v0ud (3) start ~ address ~ data ~ start ~ code ~ data ~ stop <1> when wtimn bit = 0 (after restart, extension code reception) st ad6 to ad0 r/w ack d7 to d0 ack st ad6 to ad0 r/w ack d7 to d0 ack sp s 1 s 2 s 3 s 4 ? 5 s 1: iicsn register = 0001x110b s 2: iicsn register = 0001x000b s 3: iicsn register = 0010x010b s 4: iicsn register = 0010x000b ? 5: iicsn register = 00000001b remarks 1. s : always generated ? : generated only when spien bit = 1 x: don?t care 2. n = 0, 1 <2> when wtimn bit = 1 (after restart, extension code reception) st ad6 to ad0 r/w ack d7 to d0 ack st ad6 to ad0 r/w ack d7 to d0 ack sp s 1 s 2 s 3 s 4 s 5 ? 6 s 1: iicsn register = 0001x110b s 2: iicsn register = 0001xx00b s 3: iicsn register = 0010x010b s 4: iicsn register = 0010x110b s 5: iicsn register = 0010xx00b ? 6: iicsn register = 00000001b remarks 1. s : always generated ? : generated only when spien bit = 1 x: don?t care 2. n = 0, 1 chapter 19 i 2 c bus preliminary user?s manual u17702ej1v0ud 617 (4) start ~ address ~ data ~ start ~ address ~ data ~ stop <1> when wtimn bit = 0 (after restart, address mismatch (= not extension code)) st ad6 to ad0 r/w ack d7 to d0 ack st ad6 to ad0 r/w ack d7 to d0 ack sp s 1 s 2 s 3 ? 4 s 1: iicsn register = 0001x110b s 2: iicsn register = 0001x000b s 3: iicsn register = 00000110b ? 4: iicsn register = 00000001b remarks 1. s : always generated ? : generated only when spien bit = 1 x: don?t care 2. n = 0, 1 <2> when wtimn bit = 1 (after restart, address mismatch (= not extension code)) st ad6 to ad0 r/w ack d7 to d0 ack st ad6 to ad0 r/w ack d7 to d0 ack sp s 1 s 2 s 3 ? 4 s 1: iicsn register = 0001x110b s 2: iicsn register = 0001xx00b s 3: iicsn register = 00000110b ? 4: iicsn register = 00000001b remarks 1. s : always generated ? : generated only when spien bit = 1 x: don?t care 2. n = 0, 1 chapter 19 i 2 c bus 618 preliminary user?s manual u17702ej1v0ud 19.7.3 slave device operation (w hen receiving extension code) always under communication when re ceiving the extension code. (1) start ~ code ~ data ~ data ~ stop <1> when iiccn.wtimn bit = 0 st ad6 to ad0 r/w ack d7 to d0 ack d7 to d0 ack sp s 1 s 2 s 3 ? 4 s 1: iicsn register = 0010x010b s 2: iicsn register = 0010x000b s 3: iicsn register = 0010x000b ? 4: iicsn register = 00000001b remarks 1. s : always generated ? : generated only when iiccn.spien bit = 1 x: don?t care 2. n = 0, 1 <2> when wtimn bit = 1 st ad6 to ad0 r/w ack d7 to d0 ack d7 to d0 ack sp s 1 s 2 s 3 s 4 ? 5 s 1: iicsn register = 0010x010b s 2: iicsn register = 0010x110b s 3: iicsn register = 0010x100b s 4: iicsn register = 0010xx00b ? 5: iicsn register = 00000001b remarks 1. s : always generated ? : generated only when spien bit = 1 x: don?t care 2. n = 0, 1 chapter 19 i 2 c bus preliminary user?s manual u17702ej1v0ud 619 (2) start ~ code ~ data ~ st art ~ address ~ data ~ stop <1> when wtimn bit = 0 (after restart, address match) st ad6 to ad0 r/w ack d7 to d0 ack st ad6 to ad0 r/w ack d7 to d0 ack sp s 1 s 2 s 3 s 4 ? 5 s 1: iicsn register = 0010x010b s 2: iicsn register = 0010x000b s 3: iicsn register = 0001x110b s 4: iicsn register = 0001x000b ? 5: iicsn register = 00000001b remarks 1. s : always generated ? : generated only when spien bit = 1 x: don?t care 2. n = 0, 1 <2> when wtimn bit = 1 (after restart, address match) st ad6 to ad0 r/w ack d7 to d0 ack st ad6 to ad0 r/w ack d7 to d0 ack sp s 1 s 2 s 3 s 4 s 5 ? 6 s 1: iicsn register = 0010x010b s 2: iicsn register = 0010x110b s 3: iicsn register = 0010xx00b s 4: iicsn register = 0001x110b s 5: iicsn register = 0001xx00b ? 6: iicsn register = 00000001b remarks 1. s : always generated ? : generated only when spien bit = 1 x: don?t care 2. n = 0, 1 chapter 19 i 2 c bus 620 preliminary user?s manual u17702ej1v0ud (3) start ~ code ~ data ~ st art ~ code ~ data ~ stop <1> when wtimn bit = 0 (after restart, extension code reception) st ad6 to ad0 r/w ack d7 to d0 ack st ad6 to ad0 r/w ack d7 to d0 ack sp s 1 s 2 s 3 s 4 ? 5 s 1: iicsn register = 0010x010b s 2: iicsn register = 0010x000b s 3: iicsn register = 0010x010b s 4: iicsn register = 0010x000b ? 5: iicsn register = 00000001b remarks 1. s : always generated ? : generated only when spien bit = 1 x: don?t care 2. n = 0, 1 <2> when wtimn bit = 1 (after restart, extension code reception) st ad6 to ad0 r/w ack d7 to d0 ack st ad6 to ad0 r/w ack d7 to d0 ack sp s 1 s 2 s 3 s 4 s 5 s 6 ? 7 s 1: iicsn register = 0010x010b s 2: iicsn register = 0010x110b s 3: iicsn register = 0010xx00b s 4: iicsn register = 0010x010b s 5: iicsn register = 0010x110b s 6: iicsn register = 0010xx00b ? 7: iicsn register = 00000001b remarks 1. s : always generated ? : generated only when spien bit = 1 x: don?t care 2. n = 0, 1 chapter 19 i 2 c bus preliminary user?s manual u17702ej1v0ud 621 (4) start ~ code ~ data ~ st art ~ address ~ data ~ stop <1> when wtimn bit = 0 (after restart, address mismatch (= not extension code)) st ad6 to ad0 r/w ack d7 to d0 ack st ad6 to ad0 r/w ack d7 to d0 ack sp s 1 s 2 s 3 ? 4 s 1: iicsn register = 0010x010b s 2: iicsn register = 0010x000b s 3: iicsn register = 00000110b ? 4: iicsn register = 00000001b remarks 1. s : always generated ? : generated only when spien bit = 1 x: don?t care 2. n = 0, 1 <2> when wtimn bit = 1 (after restart, address mismatch (= not extension code)) st ad6 to ad0 r/w ack d7 to d0 ack st ad6 to ad0 r/w ack d7 to d0 ack sp s 1 s 2 s 3 s 4 ? 5 s 1: iicsn register = 0010x010b s 2: iicsn register = 0010x110b s 3: iicsn register = 0010xx00b s 4: iicsn register = 00000110b ? 5: iicsn register = 00000001b remarks 1. s : always generated ? : generated only when spien bit = 1 x: don?t care 2. n = 0, 1 chapter 19 i 2 c bus 622 preliminary user?s manual u17702ej1v0ud 19.7.4 operation without communication (1) start ~ code ~ data ~ data ~ stop st ad6 to ad0 r/w ack d7 to d0 ack d7 to d0 ack sp ? 1 ? 1: iicsn register = 00000001b remarks 1. ? : generated only when iiccn.spien bit = 1 2. n = 0, 1 chapter 19 i 2 c bus preliminary user?s manual u17702ej1v0ud 623 19.7.5 arbitration loss operation (ope ration as slave after arbitration loss) when used as master in the multi-mast er system, check the arbitration result by reading the iicsn.mstsn bit for checking arbitration result by eac h intiicn interrupt occurrence. (1) when arbitration loss occurs duri ng transmission of slave address data <1> when iiccn.wtimn bit = 0 st ad6 to ad0 r/w ack d7 to d0 ack d7 to d0 ack sp s 1 s 2 s 3 ? 4 s 1: iicsn register = 0101x110b s 2: iicsn register = 0001x000b s 3: iicsn register = 0001x000b ? 4: iicsn register = 00000001b remarks 1. s : always generated ? : generated only when iiccn.spien bit = 1 x: don?t care 2. n = 0, 1 <2> when wtimn bit = 1 st ad6 to ad0 r/w ack d7 to d0 ack d7 to d0 ack sp s 1 s 2 s 3 ? 4 s 1: iicsn register = 0101x110b s 2: iicsn register = 0001x100b s 3: iicsn register = 0001xx00b ? 4: iicsn register = 00000001b remarks 1. s : always generated ? : generated only when spien bit = 1 x: don?t care 2. n = 0, 1 chapter 19 i 2 c bus 624 preliminary user?s manual u17702ej1v0ud (2) when arbitration loss occurs dur ing transmission of extension code <1> when wtimn bit = 0 st ad6 to ad0 r/w ack d7 to d0 ack d7 to d0 ack sp s 1 s 2 s 3 ? 4 s 1: iicsn register = 0110x010b s 2: iicsn register = 0010x000b s 3: iicsn register = 0010x000b ? 4: iicsn register = 00000001b remarks 1. s : always generated ? : generated only when spien bit = 1 x: don?t care 2. n = 0, 1 <2> when wtimn bit = 1 st ad6 to ad0 r/w ack d7 to d0 ack d7 to d0 ack sp s 1 s 2 s 3 s 4 ? 5 s 1: iicsn register = 0110x010b s 2: iicsn register = 0010x110b s 3: iicsn register = 0010x100b s 4: iicsn register = 0010xx00b ? 5: iicsn register = 00000001b remarks 1. s : always generated ? : generated only when spien bit = 1 x: don?t care 2. n = 0, 1 chapter 19 i 2 c bus preliminary user?s manual u17702ej1v0ud 625 19.7.6 operation when arbitr ation loss occurs (no communicat ion after arbitration loss) when used as master in the multi-mast er system, check the arbitration result by reading the iicsn.mstsn bit for checking arbitration result by eac h intiicn interrupt occurrence. (1) when arbitration loss occurs dur ing transmission of slave address data st ad6 to ad0 r/w ack d7 to d0 ack d7 to d0 ack sp s 1 ? 2 s 1: iicsn register = 01000110b ? 2: iicsn register = 00000001b remarks 1. s : always generated ? : generated only when iiccn.spien bit = 1 2. n = 0, 1 (2) when arbitration loss occurs during transmission of extension code st ad6 to ad0 r/w ack d7 to d0 ack d7 to d0 ack sp s 1 ? 2 s 1: iicsn register = 0110x010b iiccn.lreln bit is set to 1 by software ? 2: iicsn register = 00000001b remarks 1. s : always generated ? : generated only when spien bit = 1 x: don?t care 2. n = 0, 1 chapter 19 i 2 c bus 626 preliminary user?s manual u17702ej1v0ud (3) when arbitration loss o ccurs during data transfer <1> when iiccn.wtimn bit = 0 st ad6 to ad0 r/w ack d7 to d0 ack d7 to d0 ack sp s 1 s 2 ? 3 s 1: iicsn register = 10001110b s 2: iicsn register = 01000000b ? 3: iicsn register = 00000001b remarks 1. s : always generated ? : generated only when spien bit = 1 2. n = 0, 1 <2> when wtimn bit = 1 st ad6 to ad0 r/w ack d7 to d0 ack d7 to d0 ack sp s 1 s 2 ? 3 s 1: iicsn register = 10001110b s 2: iicsn register = 01000100b ? 3: iicsn register = 00000001b remarks 1. s : always generated ? : generated only when spien bit = 1 2. n = 0, 1 chapter 19 i 2 c bus preliminary user?s manual u17702ej1v0ud 627 (4) when arbitration loss occurs due to restart condition duri ng data transfer <1> not extension code (example: address mismatch) st ad6 to ad0 r/w ack d7 to dn st ad6 to ad0 r/w ack d7 to d0 ack sp s 1 s 2 ? 3 s 1: iicsn register = 1000x110b s 2: iicsn register = 01000110b ? 3: iicsn register = 00000001b remarks 1. s : always generated ? : generated only when spien bit = 1 x: don?t care 2. dn = d6 to d0 n = 0, 1 <2> extension code st ad6 to ad0 r/w ack d7 to dn st ad6 to ad0 r/w ack d7 to d0 ack sp s 1 s 2 ? 3 s 1: iicsn register = 1000x110b s 2: iicsn register = 0110x010b iiccn.lreln bit is set to 1 by software ? 3: iicsn register = 00000001b remarks 1. s : always generated ? : generated only when spien bit = 1 x: don?t care 2. dn = d6 to d0 n = 0, 1 chapter 19 i 2 c bus 628 preliminary user?s manual u17702ej1v0ud (5) when arbitration loss occurs due to stop condition during data transfer st ad6 to ad0 r/w ack d7 to dn sp s 1 ? 2 s 1: iicsn register = 1000x110b ? 2: iicsn register = 01000001b remarks 1. s : always generated ? : generated only when spien bit = 1 x: don?t care 2. dn = d6 to d0 n = 0, 1 chapter 19 i 2 c bus preliminary user?s manual u17702ej1v0ud 629 (6) when arbitration loss occurs due to low level of sda0n pin when attempting to generate a restart condition <1> when wtimn bit = 0 iiccn.sttn bit = 1 st ad6 to ad0 r/w ack d7 to d0 ack d7 to d0 ack d7 to d0 ack sp s 1 s 2 s 3 s 4 ? 5 s 1: iicsn register = 1000x110b s 2: iicsn register = 1000x000b (wtimn bit = 1) s 3: iicsn register = 1000x100b (wtimn bit = 0) s 4: iicsn register = 01000000b ? 5: iicsn register = 00000001b remarks 1. s : always generated ? : generated only when spien bit = 1 x: don?t care 2. n = 0, 1 <2> when wtimn bit = 1 iiccn.sttn bit = 1 st ad6 to ad0 r/w ack d7 to d0 ack d7 to d0 ack d7 to d0 ack sp s 1 s 2 s 3 ? 4 s 1: iicsn register = 1000x110b s 2: iicsn register = 1000x100b s 3: iicsn register = 01000100b ? 4: iicsn register = 00000001b remarks 1. s : always generated ? : generated only when spien bit = 1 x: don?t care 2. n = 0, 1 chapter 19 i 2 c bus 630 preliminary user?s manual u17702ej1v0ud (7) when arbitration loss occurs due to a stop conditi on when attempting to gene rate a restart condition <1> when wtimn bit = 0 sttn bit = 1 st ad6 to ad0 r/w ack d7 to d0 ack sp s 1 s 2 s 3 ? 4 s 1: iicsn register = 1000x110b s 2: iicsn register = 1000x000b (wtimn bit = 1) s 3: iicsn register = 1000xx00b ? 4: iicsn register = 01000001b remarks 1. s : always generated ? : generated only when spien bit = 1 x: don?t care 2. n = 0, 1 <2> when wtimn bit = 1 sttn bit = 1 st ad6 to ad0 r/w ack d7 to d0 ack sp s 1 s 2 ? 3 s 1: iicsn register = 1000x110b s 2: iicsn register = 1000xx00b ? 3: iicsn register = 01000001b remarks 1. s : always generated ? : generated only when spien bit = 1 x: don?t care 2. n = 0, 1 chapter 19 i 2 c bus preliminary user?s manual u17702ej1v0ud 631 (8) when arbitration loss occurs due to low level of sda0n pin wh en attempting to generate a stop condition <1> when wtimn bit = 0 iiccn.sptn bit = 1 st ad6 to ad0 r/w ack d7 to d0 ack d7 to d0 ack d7 to d0 ack sp s 1 s 2 s 3 s 4 ? 5 s 1: iicsn register = 1000x110b s 2: iicsn register = 1000x000b (wtimn bit = 1) s 3: iicsn register = 1000x100b (wtimn bit = 0) s 4: iicsn register = 01000100b ? 5: iicsn register = 00000001b remarks 1. s : always generated ? : generated only when spien bit = 1 x: don?t care 2. n = 0, 1 <2> when wtimn bit = 1 iiccn.sptn bit = 1 st ad6 to ad0 r/w ack d7 to d0 ack d7 to d0 ack d7 to d0 ack sp s 1 s 2 s 3 ? 4 s 1: iicsn register = 1000x110b s 2: iicsn register = 1000x100b s 3: iicsn register = 01000100b ? 4: iicsn register = 00000001b remarks 1. s : always generated ? : generated only when spien bit = 1 x: don?t care 2. n = 0, 1 chapter 19 i 2 c bus 632 preliminary user?s manual u17702ej1v0ud 19.8 interrupt request signal (intiicn) generation timing and wait control the setting of the iiccn.wtimn bit determines the ti ming by which the intiic n signal is generated and the corresponding wait control, as shown below. table 19-3. intiicn signal gene ration timing and wait control during slave device operation du ring master device operation wtimn bit address data reception data transmission address data reception data transmission 0 9 notes 1, 2 8 note 2 8 note 2 9 8 8 1 9 notes 1, 2 9 note 2 9 note 2 9 9 9 notes 1. the slave device?s intiicn signal and wait period o ccurs at the falling edge of the ninth clock only when there is a match with the addre ss set to the svan register. at this point, ack is generated regardless of the va lue set to the iiccn.acken bit. for a slave device that has received an extension code, the intiicn signal occurs at t he falling edge of the eighth clock. when the address does not match after restart, the intiicn signal is generated at the falling edge of the ninth clock, but no wait occurs. 2. if the received address does not ma tch the contents of the svan regi ster and extensi on codes have not been received, neither the intiicn signal nor a wait occurs. remarks 1. the numbers in the table indicate the number of the serial clock?s clock signals. interrupt requests and wait control are both synchronized wit h the falling edge of these clock signals. 2. n = 0, 1 (1) during address transmission/reception ? slave device operation: interrupt and wait timing are determined depending on the conditions in notes 1 and 2 above regardless of the wtimn bit. ? master device operation: interrupt and wait timing occur at the falling edge of the ninth clock regardless of the wtimn bit. (2) during data reception ? master/slave device operation: interrupt and wait timing are determined according to the wtimn bit. (3) during data transmission ? master/slave device operation: interrupt and wait timing are determined according to the wtimn bit. chapter 19 i 2 c bus preliminary user?s manual u17702ej1v0ud 633 (4) wait cancellation method the four wait cancellation methods are as follows. ? by writing data to the iicn register ? by setting the iiccn.wreln bit (canceling wait state) ? by setting the iiccn.sttn bit (generating start condition) note ? by setting the iiccn.sptn bit (generating stop condition) note note master only when an 8-clock wait has been selected (wtimn bit = 0), whether or not ac k has been generated must be determined prior to wait cancellation. remark n = 0, 1 (5) stop condition detection the intiicn signal is generated w hen a stop condition is detected. remark n = 0, 1 19.9 address match detection method when in i 2 c bus mode, the master device c an select a particular slave device by transmitting the corresponding slave address. address match detection is performed autom atically by hardware. an intiic n interrupt request signal occurs when a local address has been set to the svan register and when t he address set to the svan register matches the slave address sent by the master device, or when an extension code has been received (n = 0, 1). 19.10 error detection in i 2 c bus mode, the status of the serial data bus (sdan) during data transmission is capt ured by the iicn register of the transmitting device, so the iic n register data prior to transmission can be compared with the transmitted iicn register data to enable detection of tr ansmission errors. a transmission error is judged as having occurred when the compared data values do not match (n = 0, 1). chapter 19 i 2 c bus 634 preliminary user?s manual u17702ej1v0ud 19.11 extension code (1) when the higher 4 bits of the receive address are eit her 0000 or 1111, the extension code flag (excn) is set for extension code reception and an interrupt request signal (intiicn) is issued at the falling edge of the eighth clock. the local address stored in the svan register is not affected. (2) if 11110xx0 is set to the svan register by a 10-bit address transfer and 11110xx0 is transferred from the master device, the results are as follows. note that the int iicn signal occurs at the fa lling edge of the eighth clock. ? higher 4 bits of data match: iicsn.excn bit = 1 ? 7 bits of data match: iicsn.coin bit = 1 (3) since the processing after the intiicn signal occurs diffe rs according to the data that follows the extension code, such processing is performed by software. the slav e that has received an ext ension code is always under communication, even if the addresses mismatch. for example, when operation as a sl ave is not desired after the extension code is received, set the iiccn.lreln bit to 1 and the cpu will enter the next communication wait state. remark n = 0, 1 table 19-4. extension code bit definitions slave address r/w bit description 0000 000 0 general call address 0000 000 1 start byte 0000 001 x cbus address 0000 010 x address that is reserved for different bus format 1111 0xx x 10-bit slave address specification chapter 19 i 2 c bus preliminary user?s manual u17702ej1v0ud 635 19.12 arbitration when several master devices simultaneous ly generate a start condition (when the iiccn.sttn bit is set to 1 before the iicsn.stdn bit is set to 1), communication among the ma ster devices is performed as the number of clocks is adjusted until the data differs. this kind of operation is called arbitration (n = 0, 1). when one of the master devices loses in arbitration, an arbitration loss flag (iic sn.aldn bit) is set (1) via the timing by which the arbitration loss occurr ed, and the scln and sdan lines are both set for high impedance, which releases the bus. the arbitration loss is detec ted based on the timing of the next interrupt request signal (i ntiicn) (the eighth or ninth clock, when a stop condition is detec ted, etc.) and the aldn bit = 1 se tting that has been made by software. for details of interrupt request timing, refer to 19.7 i 2 c interrupt request signals (intiicn) . figure 19-12. arbitration timing example master 1 master 2 transfer lines scln sdan scln sdan scln sdan master 1 loses arbitration hi-z hi-z remark n = 0, 1 chapter 19 i 2 c bus 636 preliminary user?s manual u17702ej1v0ud table 19-5. status during arbitration and interrupt request generation timing status during arbitration inte rrupt request generation timing during address transmission read/write data after address transmission during extension code transmission read/write data after extension code transmission during data transmission during ack transfer period after data reception when restart condition is det ected during data transfer at falling edge of eighth or ninth clock following byte transfer note 1 when stop condition is detected duri ng data transfer when stop condition is generated (when iiccn.spien bit = 1) note 2 when the sdan pin is at low level while attempting to generate a restart condition at falling edge of eighth or ninth clock following byte transfer note 1 when stop condition is detected while attempting to generate a restart condition when stop condition is generated (when spien bit = 1) note 2 when the sdan pin is at low level while attempting to generate a stop condition when the scln pin is at low level while attempting to generate a restart condition at falling edge of eighth or ninth clock following byte transfer note 1 notes 1. when the iiccn.wtimn bit = 1, an interrupt request o ccurs at the falling edge of the ninth clock. when the wtimn bit = 0 and the extension code?s slave addr ess is received, an interrupt request occurs at the falling edge of the eighth clock. 2. when there is a possibility that arbitration will occur, set the spien bit = 1 for master device operation. remark n = 0, 1 19.13 wakeup function the i 2 c bus slave function is a function t hat generates an interrupt request signal (intiicn) when a local address or extension code has been received. this function makes processing more efficient by prev enting unnecessary interrupt requests from occurring when addresses do not match. when a start condition is detected, wa keup standby mode is set. this wak eup standby mode is in effect while addresses are transmitted due to the possi bility that an arbitration loss may change the master device (which has generated a start condition) to a slave device. however, when a stop condition is detect ed, the iiccn.spien bit is set regardl ess of the wake up function, and this determines whether interrupt requests are enabled or disabled (n = 0, 1). chapter 19 i 2 c bus preliminary user?s manual u17702ej1v0ud 637 19.14 communication reservation 19.14.1 when communication reservation func tion is enabled (iicfn.iicrsvn bit = 0) to start master device communications when not current ly using a bus, a communication reservation can be made to enable transmission of a start condition when the bus is re leased. there are two modes under which the bus is not used. ? when arbitration results in neit her master nor slave operation ? when an extension code is received and slave operation is disabled (ack is not returned and the bus was released when the iiccn.lreln bit was set to ?1?). if the iiccn.sttn bit is set (1) while the bus is not used, a start condition is automatic ally generated and wait status is set after the bus is released (after a stop condition is detected). a communication is automatically start ed as the master by setting the iiccn .spien bit to 1, detecting the bus release due to an interrupt request (intiicn) occurrence ( detecting a stop condition), and then writing the address to the iicn register. before detecting a stop condition, dat a written to the iicn register is set to invalid. when the sttn bit has been set (1), the operation mode (as start condition or as communication reservation) is determined according to the bus status. if the bus has been re leased .............................................. a start condition is generated if the bus has not been released (standby mode) .............. comm unication reservation to detect which operation mode has been dete rmined for the sttn bit, set the sttn bi t (1), wait for the wait period, then check the iicsn.mstsn bit. wait periods, which should be set via software, are listed in table 19-6. these wait periods can be set via the settings for the iicxn.clxn, iiccln.sm cn, iiccln.cln1, and iiccln.cln0 bits. table 19-6. wait periods clxn smcn cln1 cln0 selected clock wait period 0 0 0 0 f xx /2 46 clocks 0 0 0 1 f xx /2 86 clocks 0 0 1 0 f xx 43 clocks 0 0 1 1 f xx /3 102 clocks 0 1 0 1/0 f xx /2 30 clocks 0 1 1 0 f xx 15 clocks 0 1 1 1 f xx /3 36 clocks 1 1 0 1/0 f xx /2 18 clocks 1 1 1 0 f xx 9 clocks remark n = 0, 1 chapter 19 i 2 c bus 638 preliminary user?s manual u17702ej1v0ud the communication reservation timing is shown below. figure 19-13. communication reservation timing 2 1 3456 2 13456 789 scln sdan sttn=1 program processing hardware processing write to iicn set spdn and intiicn communication reservation set stdn generated by master with bus access iicn: iic shift register n sttn: bit 1 of iic control register n (iiccn) stdn: bit 1 of iic status register n (iicsn) spdn: bit 0 of iic status register n (iicsn) remark n = 0, 1 communication reservations are accepted via the following timing. after the iicsn.stdn bit is set to 1, a communication reservation can be made by setting the iiccn.sttn bit to 1 before a stop condi tion is detected (n = 0, 1). figure 19-14. timing for accep ting communication reservations scln sdan stdn spdn standby mode remark n = 0, 1 chapter 19 i 2 c bus preliminary user?s manual u17702ej1v0ud 639 the communication reservation flowchart is illustrated below. figure 19-15. communication reservation flowchart di sttn = 1 define communication reservation wait cancel communication reservation no yes iicn h ei mstsn = 0? (communication reservation) note (generate start condition) ; sets sttn flag (communication reservation). ; gets wait period set by software (refer to table 19-6 ). ; confirmation of communication reservation ; clear user flag. ; iicn write operation ; defines that communication reservation is in effect (defines and sets user flag to any part of ram). note the communication reservation oper ation executes a write to the iicn register when a stop condition interrupt request occurs. remark n = 0, 1 chapter 19 i 2 c bus 640 preliminary user?s manual u17702ej1v0ud 19.14.2 when communication reservation func tion is disabled (iicfn.iicrsvn bit = 1) when the iiccn.sttn bit is set when the bus is not us ed in a communication during bus communication, this request is rejected and a start condition is not generated. the followi ng two statuses are incl uded in the status where bus is not used. ? when arbitration results in nei ther master nor slave operation ? when an extension code is received and slave operation is disabled (ack is not returned and the bus was released when the iiccn.lreln bit was set to 1) to confirm whether the start conditi on was generated or request was rejected, check the iicfn.stcfn flag. the time shown in table 19-7 is required until the stcfn flag is set after setting the s ttn bit = 1. therefore, secure the time by software. table 19-7. wait periods cln1 cln0 selected clock wait period 0 0 f xx /2 6 clocks 0 1 f xx /2 6 clocks 1 0 f xx 3 clocks 1 1 f xx /3 9 clocks remark n = 0, 1 chapter 19 i 2 c bus preliminary user?s manual u17702ej1v0ud 641 19.15 cautions (1) when iicfn.stcenn bit = 0 immediately after i 2 cn operation is enabled, the bus communica tion status (iicfn.iicbsyn bit = 1) is recognized regardless of the actual bus status. to execute master comm unication in the status where a stop condition has not been detect ed, generate a stop condition and then releas e the bus before st arting the master communication. use the following sequence for generating a stop condition. <1> set the iiccln register. <2> set the iiccn.iicen bit. <3> set the iiccn.sptn bit. (2) when iicfn.stcenn bit = 1 immediately after i 2 cn operation is enabled, the bus released status (iicbsyn bit = 0) is recognized regardless of the actual bus status. to generate the first start condition (iiccn.sttn bit = 1), it is necessary to confirm that the bus has been released, so as to not disturb other communications. remark n = 0, 1 (3) when the iiccn.iicen bit of the v850es/kj2 is set to 1 while communications with other devices are in progress, the start condition may be detected depending on the status of the communication line. be sure to set the iiccn.iicen bit to 1 when the scln and sdan lines are high level. (4) determine the operation clock frequency by the ii ccln and iicxn registers bef ore enabling the operation (iiccn.iicen bit = 1). to change the operation clo ck frequency, clear the iiccn.iicen bit to 0 once. (5) after the iiccn.sttn and iiccn.sptn bits have been set to 1, they must not be re-set without being cleared to 0 first. (6) if transmission has been reserved, set the iiccn.spien bi t to 1 so that an interrupt request is generated by the detection of a stop condition. after an interrupt r equest has been generated, the wait state will be released by writing communication data to i 2 cn, then transferring will begin. if an interrupt is not generated by the detection of a stop condition, transmission will hal t in the wait state because an in terrupt request was not generated. however, it is not necessary to set the spien bit to 1 for the software to detect the iicsn.mstsn bit. remark n = 0 to 2 chapter 19 i 2 c bus 642 preliminary user?s manual u17702ej1v0ud 19.16 communication operations the following shows three operati on procedures with the flowchart. (1) master operation in single master system the flowchart when using the v850 es/kj2 as the master in a singl e master system is shown below. this flowchart is broadly divided into the initial setti ngs and communication processi ng. execute the initial settings at startup. if communica tion with the slave is required, pr epare the communication and then execute communication processing. (2) master operation in multimaster system in the i 2 cn bus multimaster system, whether the bus is released or used cannot be judged by the i 2 c bus specifications when the bus takes part in a communicati on. here, when data and clock are at a high level for a certain period (1 frame), the v850es/kj2 takes par t in a communication with bus released state. this flowchart is broadly divided into the initial setti ngs, communication waiting, and communication processing. the processing when the v850es/kj2 loos es in arbitration and is specified as the slave is omitted here, and only the processing as the master is shown. execute the initial setti ngs at startup to take part in a communication. then, wait for the co mmunication request as the master or wait for the spec ification as the slave. the actual communication is performed in the communication proce ssing, and it supports the transmission/reception with the slave and the arbitration wit h other masters. (3) slave operation an example of when the v850es/kj2 is used as the slave is shown below. when used as the slave, operation is st arted by an interrupt. execute the in itial settings at st artup, then wait for the intiicn interrupt occurrence (communication waiting). when the intiicn interrupt occurs, the communication status is judged and its result is pa ssed as a flag over to the main processing. by checking the flags, necessary communication processing is performed. remark n = 0, 1 chapter 19 i 2 c bus preliminary user?s manual u17702ej1v0ud 643 19.16.1 master operation in single master system figure 19-16. master operati on in single master system iicxn 0xh iiccln xxh iicfn 0xh set stcenn, iicrsvn = 0 iiccn xxh acken = wtimn = spien = 1 iicen = 1 set ports initialize i 2 c bus note sptn = 1 svan xxh write iicn write iicn sptn = 1 wreln = 1 start end read iicn acken = 0 wtimn = wreln = 1 no no yes no no no yes yes yes yes stcenn = 1? acken = 1 wtimn = 0 intiicn interrupt occurred? transfer completed? transfer completed? restarted? trcn = 1? ackdn = 1? ackdn = 1? refer to table 4-19 settings when port pins are used for alternate functions to set the i 2 c mode before this function is used. transfer clock selection local address setting start condition setting communication start preparation (start condition generation) communication start (address, transfer direction specification) waiting for ack detection waiting for data transmission transmission start communication processing initial settings reception start waiting for data reception no yes intiicn interrupt occurred? waiting for ack detection communication start preparation (stop condition generation) waiting for stop condition detection no yes yes no intiicn interrupt occurred? yes no intiicn interrupt occurred? yes no yes no yes no intiicn interrupt occurred? sttn = 1 note release the i 2 cn bus (scln, sdan pins = high level) in c onformity with the specif ications of the product in communication. for example, when the eeprom tm outputs a low level to the sdan pi n, set the scln pin to the output port and output clock pulses from t hat output port until when the sdan pin is constantly high level. remarks 1. for the transmission and reception formats, confo rm to the specifications of the product in communication. 2. n = 0, 1 chapter 19 i 2 c bus 644 preliminary user?s manual u17702ej1v0ud 19.16.2 master operation in multimaster system figure 19-17. master operation in multimaster system (1/3) iicxn 0xh iiccln xxh iicfn 0xh set stcen, iicrsvn = 0 iiccn xxh acken = wtimn = spien = 1 iicen = 1 set ports sptn = 1 svan xxh spien = 1 start slave operation slave operation bus release status for a certain period confirmation of bus status is in progress yes confirm bus status note master operation started? communication reservation enable communication reservation disable spdn = 1? stcenn = 1? iicrsvn = 0? a refer to table 4-19 settings when port pins are used for alternate functions to set the i 2 c mode before this function is used. transfer clock selection local address setting start condition setting (communication start request issued) (no communication start request) ? waiting for slave specification from another master ? waiting for communication start request (depending on user program) communication start preparation (stop condition generation) waiting for stop condition detection no yes yes no intiicn interrupt occurred? intiicn interrupt occurred? yes no yes no spdn = 1? yes no slave operation no intiicn interrupt occurred? yes no 1 b spien = 0 yes no waiting for communication request communication processing initial settings note confirm that the bus release status (iiccln.cldn bit = 1, iiccln.dadn bi t = 1) is for a certain period (1 frame, for example). when the sdan pin is const antly low level, determine whether to release the i 2 cn bus (scln, sdan pins = high level) or not conforming to the specifications of t he product in communication. remark n = 0, 1 chapter 19 i 2 c bus preliminary user?s manual u17702ej1v0ud 645 figure 19-17. master operation in multimaster system (2/3) sttn = 1 wait slave operation yes mstsn = 1? excn = 1 or coin =1? communication start preparation (start condition generation) securing wait time by software (refer to table 19-6 ) waiting for bus release (communication reserved) wait status after stop condition detection and start condition generation by communication reservation function no intiicn interrupt occurred? yes yes no no a c sttn = 1 wait slave operation yes iicbsyn = 0? excn = 1 or coin =1? communication start preparation (start condition generation) communication reservation disabled communication reservation enabled securing wait time by software (refer to table 19-7 ) waiting for bus release stop condition detection no no intiicn interrupt occurred? yes yes no yes stcfn = 0? no b d c d communication processing communication processing remark n = 0, 1 chapter 19 i 2 c bus 646 preliminary user?s manual u17702ej1v0ud figure 19-17. master operation in multimaster system (3/3) write iicn wtimn = 1 wreln = 1 read iicn acken = 1 wtimn = 0 wtimn = wreln = 1 acken = 0 write iicn yes trcn = 1? restarted? mstsn = 1? communication start (address, transfer direction specification) transmission start no yes waiting for data transmission reception start yes no intiicn interrupt occurred? yes no transfer completed? waiting for ack detection yes no intiicn interrupt occurred? waiting for data transmission not in communication yes no intiicn interrupt occurred? no yes ackdn = 1? no yes no c 2 yes mstsn = 1? no yes transfer completed? no yes ackdn = 1? no 2 yes mstsn = 1? no 2 waiting for ack detection yes no intiicn interrupt occurred? yes mstsn = 1? no c 2 yes excn = 1 or coin = 1? no 1 2 sptn = 1 sttn = 1 slave operation end communication processing communication processing remarks 1. for the transmission and reception formats, confo rm to the specificati ons of the product in communication. 2. when using the v850es/kj2 as t he master in the multimaster system, read the iicsn.mstsn bit for each intiicn interrupt occurrence to confirm the arbitration result. 3. when using the v850es/kj2 as t he slave in the multimaster system , confirm the status using the iicsn and iicfn registers for each intiicn interr upt occurrence to determine the next processing. 4. n = 0, 1 chapter 19 i 2 c bus preliminary user?s manual u17702ej1v0ud 647 19.16.3 slave operation the following shows the processing procedure of the slave operation. basically, the operation of the slave device is event-driven. therefore, processing by an intiicn interrupt (processing requiring a significant change of the operat ion status, such as st op condition detection during communication) is necessary. the following description assumes that data communication does not support extension codes. also, it is assumed that the intiicn interrupt servicing performs only status change processing and t hat the actual data communication is performed during the main processing. figure 19-18. software out line during slave operation i 2 c intiicn setting, etc. setting, etc. flag data main processing interrupt servicing therefore, the following three flags are prepared so that the data transfer processing can be performed by transmitting these flags to the main pr ocessing instead of the intiicn signal. (1) communication mode flag this flag indicates the following communication statuses. clear mode: data communication not in progress communication mode: data communication in progre ss (valid address detection stop condition detection, ack from master not detected, address mismatch) (2) ready flag this flag indicates that data communication is enabled. th is is the same status as an intiicn interrupt during normal data transfer. this flag is set in the interr upt processing block and cleared in the main processing block. the ready flag for the first data for transmission is not set in the interrupt processing block, so the first data is transmitted without clearance processing (the address match is regarded as a request for the next data). (3) communication direction flag this flag indicates the direction of communication and is the same as the value of the iicsn.trcn bit. the following shows the operati on of the main processing bl ock during slave operation. start i 2 cn and wait for the communication enabled status. when communication is enabled, perform transfer using the communication mode flag and ready flag (the processing of the stop condition and start condition is performed by interrupts, conditions are confirmed by flags). for transmission, repeat the transmission operation until the master device stops returning ack. when the master device stops returning ack, transfer is complete. chapter 19 i 2 c bus 648 preliminary user?s manual u17702ej1v0ud for reception, receive the required number of data and do not return ack for the next data immediately after transfer is complete. after that, the master device generates the stop condition or restart c ondition. this causes exit from communications. figure 19-19. slave operation flowchart (1) yes yes yes yes yes yes yes no no no no no no communication mode flag = 1? communication mode flag = 1? communication direction flag = 1? ready flag = 1? communication direction flag = 1? read iicn clear ready flag clear ready flag communication direction flag = 1? wreln = 1 ackdn = 1? clear communication mode flag wreln = 1 write iicn iiccn xxh acken = wtimn = 1 spien = 0, iicen = 1 svan xxh local address setting iicxn 0xh iiccln xxh set ports transfer clock selection iicfn 0xh set iicrsvn start condition setting transmission start reception start no yes no communication mode flag = 1? yes no ready flag = 1? refer to table 4-19 settings when port pins are used for alternate functions to set the i 2 c mode before this function is used. start initial settings communication processing chapter 19 i 2 c bus preliminary user?s manual u17702ej1v0ud 649 the following shows an example of the pr ocessing of the slave device by an int iicn interrupt (it is assumed that no extension codes are used here). during an intiicn interr upt, the status is confirm ed and the following steps are executed. <1> when a stop condition is detect ed, communication is terminated. <2> when a start condition is detected, the address is confirmed. if the address does not match, communication is terminated. if the address matches, the communica tion mode is set and wait is released, and operation returns from the interrupt (the ready flag is cleared). <3> for data transmission/reception, w hen the ready flag is set, operation retu rns from the interrupt while the i 2 cn bus remains in the wait status. remark <1> to <3> in the above correspond to <1> to <3> in figure 19-20 slave operation flowchart (2) . figure 19-20. slave operation flowchart (2) yes yes yes no no no intiicn occurred set ready flag interrupt servicing completed spdn = 1? stdn = 1? coin = 1? clear communication direction flag, ready flag, and communication mode flag <1> <2> <3> communication direction flag trcn set communication mode flag clear ready flag chapter 19 i 2 c bus 650 preliminary user?s manual u17702ej1v0ud 19.17 timing of data communication when using i 2 c bus mode, the master dev ice generates an address via the serial bus to select one of several slave devices as its communication partner. after outputting the slave address, the ma ster device transmits the iicsn.trcn bit that specifies the data transfer direction and then starts serial co mmunication with the slave device. the iicn register?s shift operation is synchronized with the falling edge of the se rial clock (scln pin). the transmit data is transferred to the so latch and is output (msb first) via the sdan pin. data input via the sdan pin is captured by the iicn register at the ri sing edge of the scln pin. the data communication timing is shown below. remark n = 0, 1 chapter 19 i 2 c bus preliminary user?s manual u17702ej1v0ud 651 figure 19-21. example of m aster to slave communication (when 9-clock wait is selected for both master and slave) (1/3) (a) start condition ~ address iicn ackdn stdn spdn wtimn h h l l l l h h h l l acken mstsn sttn sptn wreln intiicn trcn iicn ackdn stdn spdn wtimn acken mstsn sttn sptn wreln intiicn trcn scln sdan processing by master device transfer lines processing by slave device 123456789 4 3 2 1 ad6 ad5 ad4 ad3 ad2 ad1 ad0 w ack d4 d5 d6 d7 iicn address iicn data iicn ffh transmit start condition receive (when excn = 1) note note note to cancel slave wait, write ffh to iicn or set wreln. remark n = 0, 1 chapter 19 i 2 c bus 652 preliminary user?s manual u17702ej1v0ud figure 19-21. example of m aster to slave communication (when 9-clock wait is selected for both master and slave) (2/3) (b) data iicn ackdn stdn spdn wtimn h h l l l l l l h h h h l l l l l acken mstsn sttn sptn wreln intiicn trcn iicn ackdn stdn spdn wtimn acken mstsn sttn sptn wreln intiicn trcn scln sdan processing by master device transfer lines processing by slave device 1 9 8 23456789 3 2 1 d7 d0 d6 d5 d4 d3 d2 d1 d0 d5 d6 d7 iicn data iicn ffh note iicn ffh note iicn data transmit receive note note ack ack note to cancel slave wait, write ffh to iicn or set wreln. remark n = 0, 1 chapter 19 i 2 c bus preliminary user?s manual u17702ej1v0ud 653 figure 19-21. example of m aster to slave communication (when 9-clock wait is selected for both master and slave) (3/3) (c) stop condition iicn ackdn stdn spdn wtimn h h l l l l h h h l acken mstsn sttn sptn wreln intiicn trcn iicn ackdn stdn spdn wtimn acken mstsn sttn sptn wreln intiicn trcn scln sdan processing by master device transfer lines processing by slave device 123456789 2 1 d7 d6 d5 d4 d3 d2 d1 d0 ad5 ad6 iicn data iicn address iicn ffh note iicn ffh note stop condition start condition transmit note note (when spien = 1) receive (when spien = 1) ack note to cancel slave wait, write ffh to iicn or set wreln. remark n = 0, 1 chapter 19 i 2 c bus 654 preliminary user?s manual u17702ej1v0ud figure 19-22. example of sl ave to master communication (when 8-clock wait for master and 9-cl ock wait for slave are selected) (1/3) (a) start condition ~ address iicn ackdn stdn spdn wtimn h h l l l h l acken mstsn sttn l l sptn wreln intiicn trcn iicn ackdn stdn spdn wtimn acken mstsn sttn sptn wreln intiicn trcn scln sdan processing by master device transfer lines processing by slave device 123456789 4 56 3 2 1 ad6 ad5 ad4 ad3 ad2 ad1 ad0 r d4 d3 d2 d5 d6 d7 iicn address iicn ffh note note iicn data start condition ack note to cancel master wait, writ e ffh to iicn or set wreln. remark n = 0, 1 chapter 19 i 2 c bus preliminary user?s manual u17702ej1v0ud 655 figure 19-22. example of sl ave to master communication (when 8-clock wait for master and 9-cl ock wait for slave are selected) (2/3) (b) data iicn ackdn stdn spdn wtimn h h h l l l l l l l h h l l l l l acken mstsn sttn sptn wreln intiicn trcn iicn ackdn stdn spdn wtimn acken mstsn sttn sptn wreln intiicn trcn scln sdan processing by master device transfer lines processing by slave device 1 89 23456789 3 2 1 d7 d0 ack d6 d5 d4 d3 d2 d1 d0 ack d5 d6 d7 note note receive transmit iicn data iicn data iicn ffh note iicn ffh note note to cancel master wait, writ e ffh to iicn or set wreln. remark n = 0, 1 chapter 19 i 2 c bus 656 preliminary user?s manual u17702ej1v0ud figure 19-22. example of sl ave to master communication (when 8-clock wait for master and 9-cl ock wait for slave are selected) (3/3) (c) stop condition iicn ackdn stdn spdn wtimn h h l l l acken mstsn sttn sptn wreln intiicn trcn iicn ackdn stdn spdn wtimn acken mstsn sttn sptn wreln intiicn trcn scln sdan processing by master device transfer lines processing by slave device 12345678 9 1 d7 d6 d5 d4 d3 d2 d1 d0 ad6 iicn address iicn ffh note note iicn data stop condition start condition (when spien = 1) nack (when spien = 1) note to cancel master wait, writ e ffh to iicn or set wreln. remark n = 0, 1 preliminary user?s manual u17702ej1v0ud 657 chapter 20 dma function (dma controller) the v850es/kj2 includes a direct memory access (dma ) controller (dmac) that executes and controls dma transfer. the dmac controls data transfer between memory and i/o, between memo ries, or between i/os based on dma requests issued by the on-chip peripheral i/o (serial in terface, timer/counter, and a/d converter), interrupts from external input pins, or software triggers (memory refers to internal ram or external memory). 20.1 features ? 4 independent dma channels ? transfer unit: 8/16 bits ? maximum transfer count: 65,536 (2 16 ) ? transfer type: two-cycle transfer ? transfer mode: single transfer mode ? transfer requests ? request by interrupts from on-chip peripheral i/o (seria l interface, timer/counter, a/d converter) or interrupts from external input pin ? requests by software trigger ? transfer targets ? internal ram ? peripheral i/o ? peripheral i/o ? peripheral i/o ? internal ram ? external memory ? external memory ? peripheral i/o ? external memory ? external memory chapter 20 dma function (dma controller) preliminary user?s manual u17702ej1v0ud 658 20.2 configuration cpu internal ram on-chip peripheral i/o on-chip peripheral i/o bus internal bus data control address control count control channel control dmac v850es/kj2 bus interface external bus external ram external rom external i/o dma source address register n (dsanh/dsanl) dma transfer count register n (dbcn) dma channel control register n (dchcn) dma destination address register n (ddanh/ddanl) dma addressing control register n (dadcn) dma trigger factor register n (dtfrn) remark n = 0 to 3 chapter 20 dma function (dma controller) preliminary user?s manual u17702ej1v0ud 659 20.3 registers (1) dma source address registers 0 to 3 (dsa0 to dsa3) the dsa0 to dsa3 registers set the dma source addresse s (26 bits each) for dma channel n (n = 0 to 3). these registers are divided into two 16-bit registers, dsanh and dsanl. these registers can be read or written in 16-bit units. external memory or on-chip peripheral i/o internal ram irn 0 1 specification of dma transfer source set the address (a25 to a16) of the dma transfer source (default value is undefined). during dma transfer, the next dma transfer source address is held. when dma transfer is completed, the dma address set first is held. san25 to san16 set the address (a15 to a0) of the dma transfer source (default value is undefined). during dma transfer, the next dma transfer source address is held. when dma transfer is completed, the dma address set first is held. san15 to san0 after reset: undefined r/w address: dsa0h fffff082h, dsa1h fffff08ah, dsa2h fffff092h, dsa3h fffff09ah, dsa0l fffff080h, dsa1l fffff088h, dsa2l fffff090h, dsa3l fffff098h dsanl (n = 0 to 3) san15 san14 san13 san12 san6 san5 san4 san3 san2 san1 san0 san7 san8 san9 san10 san11 dsanh (n = 0 to 3) irn 000 san22 san21 san20 san19 san18 san17 san16 san23 san24 san25 0 0 cautions 1. be sure to clear bits 14 to 10 of the dsanh register to 0. 2. set the dsanh and dsanl registers at the following timing while dma is not in progress. ? period from after reset to start of first dma transfer ? period from after channel initialization by dchcn.initn bit to start of dma transfer ? period from after completion of dma transfer (dchcn.tcn bit = 1) to start of the next dma transfer 3. when the value of the dsan register is read, two 16-bit re gisters, dsanh and dsanl, are read. if reading and updating conflict, the valu e being updated may be read (refer to 20.13 cautions). chapter 20 dma function (dma controller) preliminary user?s manual u17702ej1v0ud 660 (2) dma destination address regi sters 0 to 3 (dda0 to dda3) the dda0 to dda3 registers set the dma destination addre ss (26 bits each) for dma channel n (n = 0 to 3). these registers are divided into two 16-bit registers, ddanh and ddanl. these registers can be read or written in 16-bit units. external memory or on-chip peripheral i/o internal ram irn 0 1 specification of dma transfer destination set an address (a25 to a16) of dma transfer destination (default value is undefined). during dma transfer, the next dma transfer destination address is held. when dma transfer is completed, the dma transfer source address set first is held. dan25 to dan16 set an address (a15 to a0) of dma transfer destination (default value is undefined). during dma transfer, the next dma transfer destination address is held. when dma transfer is completed, the dma transfer source address set first is held. dan15 to dan0 after reset: undefined r/w address: dda0h fffff086h, dda1h fffff08eh, da2h fffff096h, dda3h fffff09eh, dda0l fffff084h, dda1l fffff08ch, dda2l fffff094h, dda3l fffff09ch ddanl (n = 0 to 3) dan15 dan14 dan13 dan12 dan6 dan5 dan4 dan3 dan2 dan1 dan0 dan7 dan8 dan9 dan10 dan11 ddanh (n = 0 to 3) irn 000 dan22 dan21 dan20 dan19 dan18 dan17 dan16 dan23 dan24 dan25 0 0 cautions 1. be sure to clear bits 14 to 10 of the ddanh register to 0. 2. set the ddanh and ddanl registers at the following timing while dma is not in progress. ? period from after reset to start of first dma transfer ? period from after channel initialization by dchcn.initn bit to start of dma transfer ? period from after completion of dma transfer (dchcn.tcn bit = 1) to start of the next dma transfer 3. when the value of the ddan register is read, two 16-bit registers, ddanh and ddanl, are read. if reading and updating conflict, a valu e being updated may be read (refer to 20.13 cautions). chapter 20 dma function (dma controller) preliminary user?s manual u17702ej1v0ud 661 (3) dma byte count registers 0 to 3 (dbc0 to dbc3) the dbc0 to dbc3 registers are 16-bit registers that set the byte transfer c ount for dma channel n (n = 0 to 3). these registers hold the remaining tr ansfer count during dma transfer. these registers are decremented by 1 per one transfer regardless of the trans fer data unit (8/16 bits), and the transfer is terminated if a borrow occurs. these registers can be read or written in 16-bit units. byte transfer count 1 or remaining byte transfer count byte transfer count 2 or remaining byte transfer count : byte transfer count 65,536 (2 16 ) or remaining byte transfer count bcn15 to bcn0 0000h 0001h : ffffh byte transfer count setting or remaining byte transfer count during dma transfer after reset: undefined r/w address: dbc0 fffff0c0h, dbc1 fffff0c2h, dbc2 fffff0c4h, dbc3 fffff0c6h dbcn (n = 0 to 3) 15 bcn15 14 bcn14 13 bcn13 12 bcn12 11 bcn11 10 bcn10 9 bcn9 8 bcn8 7 bcn7 6 bcn6 5 bcn5 4 bcn4 3 bcn3 2 bcn2 1 bcn1 0 bcn0 the number of transfer data set first is held when dma transfer is complete. caution set the dbcn register at the follow ing timing while dma is not in progress. ? period from after reset to start of first dma transfer ? period from after channel initialization by dchcn.initn bit to start of dma transfer ? period from after completion of dma transfer ( dchcn.tcn bit = 1) to start of the next dma transfer chapter 20 dma function (dma controller) preliminary user?s manual u17702ej1v0ud 662 (4) dma addressing control registers 0 to 3 (dadc0 to dadc3) the dadc0 to dadc3 registers are 16-bit registers that control the dma transfer mode for dma channel n (n = 0 to 3). these registers can be read or written in 16-bit units. reset input clears these registers to 0000h. dadcn (n = 0 to 3) 8 bits 16 bits dsn0 0 1 setting of transfer data size increment decrement fixed setting prohibited sadn1 0 0 1 1 sadn0 0 1 0 1 setting of count direction of the transfer source address increment decrement fixed setting prohibited dadn1 0 0 1 1 dadn0 0 1 0 1 setting of count direction of the destination address after reset: 0000h r/w address: dadc0 fffff0d0h, dadc1 fffff0d2h, dadc2 fffff0d4h, dadc3 fffff0d6h sadn1 sadn0 dadn1 dadn0 0 0 0 0 0 dsn0 0 0 0 0 0 0 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 cautions 1. be sure to clear bits 15, 13 to 8, and 3 to 0 of the dadcn register to 0. 2. set the dadcn register at the foll owing timing while dma is not in progress. ? period from after reset to start of first dma transfer ? period from after channel initialization by dchcn.initn bit to start of dma transfer ? period from after completion of dma transfer (dchcn.tcn bit = 1) to start of the next dma transfer 3. the dsn0 bit specifies the si ze of the transfer data, and do es not control bus sizing. if 8- bit data (dsn0 bit = 0) is set, therefore, the lower data bus is not always used. 4. if the transfer data size is set to 16 bits (dsn0 bit = 1), transfer cannot be started from an odd address. transfer is always started from an address with the first bit of the lower address aligned to 0. 5. if dma transfer is executed on an on-chip pe ripheral i/o register (as the transfer source or destination), be sure to specify the same transfer size as the re gister size. for example, to execute dma transfer on an 8-bit register , be sure to specify 8-bit transfer. chapter 20 dma function (dma controller) preliminary user?s manual u17702ej1v0ud 663 (5) dma channel control registers 0 to 3 (dchc0 to dchc3) the dchc0 to dchc3 registers are 8-bit registers t hat control the dma transfer operating mode for dma channel n. these registers can be read or written in 8-bit or 1-bit units (however, bit 7 is read-only and bits 1 and 2 are write-only. if bit 1 or 2 is read, the read value is always 0). reset input clears these registers to 00h. dchcn (n = 0 to 3) dma transfer had not completed. dma transfer had completed. it is set to 1 on the last dma transfer and cleared to 0 when it is read. tcn note 1 0 1 status flag indicates whether dma transfer through dma channel n has completed or not dma transfer disabled dma transfer enabled dma transfer is enabled when the enn bit is set to 1. when dma transfer is completed (when a terminal count is generated), this bit is automatically cleared to 0. to abort dma transfer, clear the enn bit to 0 by software. to resume, set the enn bit to 1 again. when aborting or resuming dma transfer, however, be sure to observe the procedure described in 20.13 cautions . enn 0 1 setting of whether dma transfer through dma channel n is to be enabled or disabled this is a software startup trigger of dma transfer. if this bit is set to 1 in the dma transfer enable state (tcn bit = 0, enn bit = 1), dma transfer is started. stgn note 2 after reset: 00h r/w address: dchc0 fffff0e0h, dchc1 fffff0e2h, dchc2 fffff0e4h, dchc3 fffff0e6h tcn note 1 0 0 0 0 initn note 2 stgn note 2 enn <0> <1> <2> 3 4 5 6 <7> initn note 2 if the initn bit is set to 1 with dma transfer disabled (enn bit = 0), the dma transfer status can be initialized. when re-setting the dma transfer status (re-setting the ddanh, ddanl, dsanh, dsanl, dbcn, and dadcn registers) before dma transfer is completed (before the tcn bit is set to 1), be sure to initialize the dma channel. when initializing the dma controller, however, be sure to observe the procedure described in 20.13 cautions . notes 1. the tcn bit is read-only. 2. the initn and stgn bits are write-only. cautions 1. be sure to clear bits 6 to 3 of the dchcn register to 0. 2. when dma transfer is completed (when a terminal count is generated), the enn bit is cleared to 0 and then the tcn bit is set to 1. if the dchcn regist er is read while its bits are being updated, a value indicating ?transfer not co mpleted and transfer is disabled? (tcn bit = 0 and enn bit = 0) may be read. chapter 20 dma function (dma controller) preliminary user?s manual u17702ej1v0ud 664 (6) dma trigger factor registers 0 to 3 (dtfr0 to dtfr3) the dtfr0 to dtfr3 registers are 8-bit registers that control the dma transfer start trigger via interrupt request signals from on-chip peripheral i/o. the interrupt request signals set by these re gisters serve as dma transfer start factors. these registers can be read or written in 8-bit units. however, only t he dfn bit can be read or written in 1-bit units. reset input clears these registers to 00h. dtfrn (n = 0 to 3) no dma transfer request dma transfer request dfn note 0 1 dma transfer request flag after reset: 00h r/w address: dtfr0 fffff810h, dtfr1 fffff812h, dtfr2 fffff814h, dtfr3 fffff816h dfn 0 ifcn5 ifcn4 ifcn3 ifcn2 ifcn1 ifcn0 0 1 2 3 4 5 6 <7> note the dfn bit can write 0 only. write 0 to this bit to clear a dma transfer request if an interrupt that is specified as the cause of starting dma trans fer occurs while dma transfer is disabled. cautions 1. set the ifcn5 to if cn0 bits at the following timing while dma is not in progress. ? period from after reset to start of first dma transfer ? period from after channel initialization by dchcn.initn bit to start of dma transfer ? period from after completion of dma transfer (dchcn.tcn bit = 1) to start of the next dma transfer 2. an interrupt request that is generated in the standby mode (idle, stop, or sub-idle mode) does not start the dma transfer cy cle (nor is the dfn bit set to 1). 3. if a dma start factor is selected by the ifcn 5 to ifcn0 bits, the dfn bi t is set to 1 when an interrupt occurs from the selected on-chip pe ripheral i/o, regardless of whether the dma operation is enabled or disabled. if dma is enabled in this status, dma transfer is immediately started. remark for the ifcn5 to ifcn0 bits, refer to table 20-1 dma start factors . chapter 20 dma function (dma controller) preliminary user?s manual u17702ej1v0ud 665 table 20-1. dma start factors (1/2) ifcn5 ifcn4 ifcn3 ifcn2 ifcn1 ifcn0 interrupt source 0 0 0 0 0 0 dma request by interrupt disabled 0 0 0 0 0 1 intwdtm1 0 0 0 0 1 0 intp0 0 0 0 0 1 1 intp1 0 0 0 1 0 0 intp2 0 0 0 1 0 1 intp3 0 0 0 1 1 0 intp4 0 0 0 1 1 1 intp5 0 0 1 0 0 0 intp6 0 0 1 0 0 1 inttm000 0 0 1 0 1 0 inttm001 0 0 1 0 1 1 inttm010 0 0 1 1 0 0 inttm011 0 0 1 1 0 1 inttm50 0 0 1 1 1 0 inttm51 0 0 1 1 1 1 intcsi00 0 1 0 0 0 0 intcsi01 0 1 0 0 0 1 intsre0 0 1 0 0 1 0 intsr0 0 1 0 0 1 1 intst0 0 1 0 1 0 0 intsre1 0 1 0 1 0 1 intsr1 0 1 0 1 1 0 intst1 0 1 0 1 1 1 inttmh0 0 1 1 0 0 0 inttmh1 0 1 1 0 0 1 intcsia0 0 1 1 0 1 0 intiic0 note 0 1 1 0 1 1 intad 0 1 1 1 0 0 intkr 0 1 1 1 0 1 intwti 0 1 1 1 1 0 intwt 0 1 1 1 1 1 intbrg 1 0 0 0 0 0 inttm020 1 0 0 0 0 1 inttm021 1 0 0 0 1 0 inttm030 1 0 0 0 1 1 inttm031 1 0 0 1 0 0 intcsia1 1 0 0 1 0 1 inttm040 1 0 0 1 1 0 inttm041 1 0 0 1 1 1 inttm050 1 0 1 0 0 0 inttm051 1 0 1 0 0 1 intcsi02 1 0 1 0 1 0 intsre2 remark n = 0 to 3 chapter 20 dma function (dma controller) preliminary user?s manual u17702ej1v0ud 666 table 20-1. dma start factors (2/2) ifcn5 ifcn4 ifcn3 ifcn2 ifcn1 ifcn0 interrupt source 1 0 1 0 1 1 intsr2 1 0 1 1 0 0 intst2 1 0 1 1 0 1 intiic1 1 0 1 1 1 1 intp7 1 1 0 0 0 0 inttp0ov 1 1 0 0 0 1 inttp0cc0 1 1 0 0 1 0 inttp0cc1 other than above setting prohibited remark n = 0 to 3 20.4 transfer targets table 20-2 shows the relationship between the transfer targets ( : transfer enabled, : transfer disabled). table 20-2. relationship between transfer targets transfer destination internal rom on-chip peripheral i/o internal ram external memory on-chip peripheral i/o internal ram external memory source internal rom caution the operation is not guaranteed for combinat ions of transfer destination and source marked with ? ? in table 20-2. 20.5 transfer modes single transfer is supported as the transfer mode. in single transfer mode, the bus is released at each byte/hal fword transfer. if there is a subsequent dma transfer request, transfer is performed again once. this operation continues until a terminal count occurs. when the dmac has released the bus, if another higher priority dma transfer request is issued, the higher priority dma request always takes precedence. if a new transfer request of the same channel and a transfer request of another channel with a lower priority are generated in a transfer cycle, dma transfer of the channel with the lower priority is executed after the bus is released to the cpu (the new transfer request of the same channel is ignored in the transfer cycle). chapter 20 dma function (dma controller) preliminary user?s manual u17702ej1v0ud 667 20.6 transfer types as a transfer type, the 2-cycle transfer is supported. in two-cycle transfer, data transfer is performed in two cycles, a read cycle and a write cycle. in the read cycle, the transfer source address is output and reading is performed from the source to the dmac. in the write cycle, the transfer destination addr ess is output and writing is performed from the dmac to the destination. an idle cycle of one clock is always inserted between a read cycle and a write cycle. if the data bus width differs between the transfer source and destination for dma transfe r of two cycles, the operation is performed as follows. <16-bit data transfer> <1> transfer from 32-bit bus 16-bit bus a read cycle (the higher 16 bits are in a high-impedan ce state) is generated, followed by generation of a write cycle (16 bits). <2> transfer from 16-/32-bit bus to 8-bit bus a 16-bit read cycle is generated once, and then an 8-bit write cycle is generated twice. <3> transfer from 8-bit bus to 16-/32-bit bus an 8-bit read cycle is generated twice, and then a 16-bit write cycle is generated once. <4> transfer between 16-bit bus and 32-bit bus a 16-bit read cycle is generated once, and then a 16-bit write cycle is generated once. for dma transfer executed to an on-chip peripheral i/o register (transfer source /destination), be sure to specify the same transfer size as the register size. for example, for dma transfer to an 8-bit register, be sure to specify byte (8- bit) transfer. remark the bus width of each transfer target (tr ansfer source/destination) is as follows. ? on-chip peripheral i/o: 16-bit bus width ? internal ram: 32-bit bus width ? external memory: 8-bit or 16-bit bus width 20.7 dma channel priorities the dma channel priorities are fixed as follows. dma channel 0 > dma channel 1 > dma channel 2 > dma channel 3 the priorities are checked for every transfer cycle. chapter 20 dma function (dma controller) preliminary user?s manual u17702ej1v0ud 668 20.8 time related to dma transfer the time required to respond to a dma request, and the minimum number of clocks required for dma transfer are shown below. single transfer: dma response time (<1>) + transfer source memory access (<2>) + 1 note 1 + transfer destination memory access (<2>) dma cycle minimum number of execution clocks <1> dma request response time 4 clocks (min.) + noise elimination time note 2 external memory access depends on connected memory. internal ram access 2 clocks note 3 <2> memory access peripheral i/o register access 3 clocks + number of wait cycles specified by vswc register note 4 notes 1. one clock is always inserted between a read cycle and a write cycle in dma transfer. 2. if an external interrupt (intpn) is specified as the tr igger to start dma transfer, noise elimination time is added (n = 0 to 7). 3. two clocks are required for a dma cycle. 4. more wait cycles may be necessary for accessing a special register described in 3.4.8 (1) (b) . chapter 20 dma function (dma controller) preliminary user?s manual u17702ej1v0ud 669 20.9 dma transfer start factors there are two types of dma transfe r start factors, as shown below. (1) request by software if the dchcn.stgn bit is set to 1 while the dchcn.tcn bit = 0 and dchcn.enn bit = 1 (dma transfer enabled), dma transfer is started. to request the next dma transfer cycle immediately after that, confirm, by using th e dbcn register, that the preceding dma transfer cycle has been completed, and set the stgn bit to 1 again (n = 0 to 3). tcn bit = 0, enn bit = 1 stgn bit = 1 ? starts the first dma transfer. confirm that the contents of the dbcn register have been updated. stgn bit = 1 ? starts the second dma transfer. : generation of terminal count ? enn bit = 0, tc n bit = 1, and intdman signal is generated. (2) request by on-chip peripheral i/o if an interrupt request is generated fr om the on-chip peripheral i/o set by the dtfrn register when the tcn bit = 0 and enn bit = 1 (dma transfer enabled), dma transfer is started. cautions 1. two start factors (software trigger a nd hardware trigger) cannot be used for one dma channel. if two start factors are simultane ously generated for one dma channel, only one of them is valid. the start factor that is valid cannot be identified. 2. a new transfer request that is generate d after the preceding dma transfer request was generated or in the preceding dma tran sfer cycle is ignored (cleared). 3. the transfer request inte rval of the same dma channel varies depending on the setting of bus wait in the dma transfer cycle, the start status of the other channels, or the external bus hold request. in particular, as described in caution 2, a new transfer request that is generated for the same channel before the dma transfer cycle or during the dma transfer cycle is ignored. therefore, the transfer re quest intervals for the same dma channel must be sufficiently secured by the system. when the software tr igger is used, completion of the dma transfer cycle that was generated before can be checked by updating the dbcn register. chapter 20 dma function (dma controller) preliminary user?s manual u17702ej1v0ud 670 20.10 dma abort factors dma transfer is aborted if a bus hold occurs. the same applies if transfer is ex ecuted between the intern al memory/on-chip peripheral i/o and internal memory/on-chip peripheral i/o. when the bus hold is cleared, dma transfer is resumed. 20.11 end of dma transfer when dma transfer has been completed the number of ti mes set to the dbcn register and when the dchcn.enn bit is cleared to 0 and tcn bit is set to 1, a dma transfer end interrupt request signal (intdman) is generated for the interrupt controller (intc) (n = 0 to 3). the v850es/kj2 does not output a terminal count signal to an external device. therefore, confirm completion of dma transfer by using the dma transfer end interrupt or polling the tcn bit. 20.12 operation timing the operation timing of dma is as follows. chapter 20 dma function (dma controller) preliminary user?s manual u17702ej1v0ud 671 figure 20-1. priority of dma (1) read write idle write read dma0 transfer request system clock dma1 transfer request dma2 transfer request dma transfer mode of processing df0 bit df1 bit df2 bit idle dma2 processing cpu processing dma1 processing cpu processing cpu processing dma0 processing read preparation for transfer end processing preparation for transfer preparation for transfer end processing remarks 1. transfer in the order of dma0 dma1 dma2 2. in the case of transfer between external memory spaces (multiplex bus, no wait) chapter 20 dma function (dma controller) preliminary user?s manual u17702ej1v0ud 672 figure 20-2. priority of dma (2) preparation for transfer read write idle dma0 transfer request system clock dma1 transfer request dma2 transfer request dma transfer mode of processing df0 bit df1 bit df2 bit cpu processing dma0 processing cpu processing dma1 processing cpu processing dma0 processing read write idle end processing read preparation for transfer preparation for transfer end processing remarks 1. transfer in the order of dma0 dma1 dma0 (dma2 is held pending.) 2. in the case of transfer between external memory spaces (multiplex bus, no wait) chapter 20 dma function (dma controller) preliminary user?s manual u17702ej1v0ud 673 figure 20-3. period in which dma transfer request is ignored (1) preparation for transfer read cycle write cycle idle end processing dma transfer mode of processing dfn bit system clock transfer request generated after this can be acknowledged dma0 processing cpu processing cpu processing note 2 note 2 dman transfer request note 1 note 2 notes 1. interrupt from on-chip peripheral i/o, or software trigger (dchcn.stgn bit) 2. new dma request of the same channel is i gnored between when the transfer request is generated and the end processing is complete. remark in the case of transfer between external memory spaces (multiplex bus, no wait) chapter 20 dma function (dma controller) preliminary user?s manual u17702ej1v0ud 674 figure 20-4. period in which dma transfer request is ignored (2) read write idle write read dma0 transfer request system clock dma1 transfer request dma2 transfer request dma transfer mode of processing df0 bit df1 bit df2 bit idle <1> <2> <3> <4> cpu processing dma0 processing cpu processing dma1 processing cpu processing read preparation for transfer dma0 processing end processing preparation for transfer preparation for transfer end processing <1> dma0 transfer request <2> new dma0 transfer request is generated during dma0 transfer. a dma transfer request of the same channel is ignored during dma transfer. <3> requests for dma0 and dma1 are generated at the same time. dma0 request is ignored (a dma transfer request of the same channel during transfer is ignored). dma1 request is acknowledged. <4> requests for dma0, dma1, and dma2 are generated at the same time. dma1 request is ignored (a dma transfer request of the same channel during transfer is ignored). dma0 request is acknowledged according to priority. dma2 request is held pending (transfer of dma2 occurs next). chapter 20 dma function (dma controller) preliminary user?s manual u17702ej1v0ud 675 20.13 cautions (1) caution for vswc register when using the dmac, be sure to set an appropriate val ue, in accordance with the operating frequency, to the vswc register. when the default value (77h) of the vsw c register is used, or if an inappr opriate value is set to the vswc register, the operation is not correctly perform ed (for details of the vswc register, refer to 3.4.8 (1) (a) system wait control register (vswc) ). (2) caution for dma transfer executed on internal ram when executing the following instructions located in th e internal ram, do not ex ecute a dma transfer that transfers data to/from the internal ram (transfer source/destination), because the cpu may not operate correctly afterward. ? data access instruction to misaligned address located in internal ram conversely, when executing a dma transfer to tran sfer data to/from the in ternal ram (transfer source/destination), do not exec ute the above instruction. (3) caution for reading dchcn .tcn bit (n = 0 to 3) the tcn bit is cleared to 0 when it is read, but it is not automatically cleared to 0 even if it is read at a specific timing. to accurately clear the tcn bit, add the following processing. (a) when waiting for completion of dma transfer by polling tcn bit confirm that the tcn bit has been set to 1 (after tcn bit = 1 is read), and then read the tcn bit three more times. (b) when reading tcn bit in interrupt servicing routine execute reading the tcn bit three times. chapter 20 dma function (dma controller) preliminary user?s manual u17702ej1v0ud 676 (4) dma transfer initialization pr ocedure (setting dchcn.initn bit to 1) even if the initn bit is set to 1 when the channel exec uting dma transfer is to be initialized, the channel may not be initialized. to accurately initialize the c hannel, execute either of the following two procedures. (a) temporarily stop transf er of all dma channels initialize the channel executing dma transfer using the procedure in <1> to <7> below. note, however, that tcn bit is cleared to 0 when st ep <5> is executed. make sure that the other processing programs do not expect that the tcn bit is 1. <1> disable interrupts (di). <2> read the dchcn.enn bit of dma channels other t han the one to be forcibly terminated, and transfer the value to a general-purpose register. <3> clear the enn bit of the dma channels used (including the channel to be forcibly terminated) to 0. to clear the enn bit of the last dma channel, execute t he clear instruction twice. if the target of dma transfer (transfer source/destination) is the inte rnal ram, execute the instruction three times. example: execute instructions in the fo llowing order if channels 0, 1, and 2 are used (if the target of transfer is not the internal ram). ? clear dchc0.e00 bit to 0. ? clear dchc1.e11 bit to 0. ? clear dchc2.e22 bit to 0. ? clear dchc2.e22 bit to 0 again. <4> set the initn bit of the channel to be forcibly terminated to 1. <5> read the tcn bit of each channel not to be forcib ly terminated. if both the tcn bit and the enn bit read in <2> are 1 (logical product (and) is 1), clear the saved enn bit to 0. <6> after the operation in <5>, write the enn bit value to the dchcn register. <7> enable interrupts (ei). caution be sure to execute step <5> above to pr event illegal setting of the enn bit of the channels whose dma transfer has been normally completed between <2> and <3>. chapter 20 dma function (dma controller) preliminary user?s manual u17702ej1v0ud 677 (b) repeatedly execute setting initn bit until transfer is forcibly terminated correctly <1> suppress a request from the dma request source of the channel to be forcibly terminated (stop operation of the on-ch ip peripheral i/o). <2> check that the dma transfer requ est of the channel to be forcibly terminated is not held pending, by using the dtfrn.dfn bit. if a dma transfer reques t is held pending, wait until execution of the pending dma transfer request is completed. <3> when it has been confirmed that t he dma request of the channel to be forcibly terminated is not held pending, clear the enn bit to 0. <4> again, clear the enn bit of the channel to be forcibly terminated to 0. if the target of transfer for the channel to be forc ibly terminated (transfer source/destination) is the internal ram, execute th is operation once more. <5> copy the initial number of trans fers of the channel to be forcibly terminated to a general-purpose register. <6> set the initn bit of the channel to be forcibly terminated to 1. <7> read the value of the dbcn regist er of the channel to be forcibly terminated, and compare it with the value copied in <5>. if the two values do not match, repeat operations <6> and <7>. remarks 1. when the value of the dbcn regist er is read in <7>, the initial number of transfers is read if forced termination has been correctly completed. if not, the remaining number of transfers is read. 2. note that method (b) may take a long time if the application frequently uses dma transfer for a channel other than the dma channel to be forcibly terminated. (5) procedure of temporarily stoppi ng dma transfer (clearing enn bit) stop and resume the dma transfer under ex ecution using the following procedure. <1> suppress a transfer request from the dma request s ource (stop the operation of the on-chip peripheral i/o). <2> check the dma transfer request is not held pending , by using the dfn bit (check if the dfn bit = 0). if a request is held pending, wait until execution of the pending dma transfer request is completed. <3> if it has been confirmed that no dma transfer requ est is held pending, clear the enn bit to 0 (this operation stops dma transfer). <4> set the enn bit to 1 to resume dma transfer. <5> resume the operation of the dma request source that has been stopped (start the operation of the on- chip peripheral i/o). (6) memory boundary the operation is not guaranteed if th e address of the transfer source or destination exceeds the area of the dma target (external memory, internal ram, or on-chip peripheral i/o) during dma transfer. (7) transferring misaligned data dma transfer of misaligned data with a 16-bit bus width is not supported. if an odd address is specified as the trans fer source or destination, the leas t significant bit of the address is forcibly assumed to be 0. chapter 20 dma function (dma controller) preliminary user?s manual u17702ej1v0ud 678 (8) bus arbitration for cpu because the dma controller has a higher priority bus ma stership than the cpu, a cpu access that takes place during dma transfer is held pending unt il the dma transfer cycle is complete d and the bus is released to the cpu. however, the cpu can access the external memory, on- chip peripheral i/o, and inte rnal ram to/from which dma transfer is not being executed. ? the cpu can access the internal ram when dma transfer is being executed between the external memory and on-chip peripheral i/o. ? the cpu can access the internal ram and on-chip peripheral i/o when dma transfer is being executed between the external memory and external memory. (9) registers/bits that must not be rewritten during dma operation set the following registers at the following ti ming when a dma operation is not under execution. [registers] ? dsanh, dsanl, ddanh, ddanl, dbcn, and dadcn registers ? dtfrn.ifcn5 to dtfrn.ifcn0 bits [timing of setting] ? period from after reset to start of the first dma transfer ? time after channel initializ ation to start of dma transfer ? period from after completion of dma transfer (tcn bit = 1) to start of the next dma transfer (10) be sure to set the foll owing register bits to 0. ? bits 14 to 10 of dsanh register ? bits 14 to 10 of ddanh register ? bits 15, 13 to 8, and 3 to 0 of dadcn register ? bits 6 to 3 of dchcn register (11) dma start factor do not start two or more dma channels with the same st art factor. if two or more channels are started with the same factor, a dma channel with a lower priority may be acknowledged earlier than a dma channel with a higher priority. chapter 20 dma function (dma controller) preliminary user?s manual u17702ej1v0ud 679 (12) read values of dsan and ddan registers values in the middle of updating may be read from t he dsan and ddan registers during dma transfer (n = 0 to 3). for example, if the dsanh regist er and then the dsanl register ar e read when the dma transfer source address (dsan register) is 0000ffffh and the count direction is incremental (dadcn.sad1 and dadcn.sad0 bits = 00), the value of the dsanl regi ster differs as follows, depending on whether dma transfer is executed immediately after the dsanh register is read. (a) if dma transfer does not occu r while dsan register is read <1> read value of dsanh register: dsanh register = 0000h <2> read value of dsanl register: dsanl register = ffffh (b) if dma transfer occurs while dsan register is read <1> read value of dsanh register: dsanh register = 0000h <2> occurrence of dma transfer <3> incrementing dsan register: dsan register = 00100000h <4> read value of dsanl register: dsanl register = 0000h preliminary user?s manual u17702ej1v0ud 680 chapter 21 interrupt/except ion processing function 21.1 overview the v850es/kj2 is provided with a dedica ted interrupt controller (intc) fo r interrupt servicing and realize an interrupt function that can service interrupt requests from a total of 56 sources. an interrupt is an event that occurs independently of program execution, and an ex ception is an event whose occurrence is dependent on program execution. the v850es/kj2 can process interrupt requests from t he on-chip peripheral hardware and external sources. moreover, exception processing can be star ted by the trap instruction (software exception) or by generation of an exception event (fetching of an illegal op code) (exception trap). 21.1.1 features interrupt source v850es/kj2 external 1 channel (nmi pin) non-maskable interrupt internal 2 channels (wdt1, wdt2) external 8 channels (all edge detection interrupts) wdt1 1 channel tmp 3 channels tm0 12 channels tmh 2 channels tm5 2 channels wt 2 channels brg 1 channel uart 9 channels csi0 3 channels csia 2 channels iic 2 channels kr 1 channel ad 1 channel dma 4 channels interrupt function maskable interrupt internal total 45 channels 16 channels (trap00h to trap0fh) software exception 16 channels (trap10h to trap1fh) exception function exception trap 2 channels (ilgop/dbg0) table 21-1 lists the interrupt/exception sources. chapter 21 interrupt/exception processing function preliminary user?s manual u17702ej1v0ud 681 table 21-1. interrupt source list (1/3) type classification default priority name trigger interrupt source exception code handler address restored pc interrupt control register reset pin input pin reset interrupt ? reset internal reset input from wdt1, wdt2 wdt1 wdt2 0000h 00000000h u ndefined ? ? nmi nmi pin valid edge input pin 0010h 00000010h nextpc ? ? intwdt1 wdt1 overflow (when non- maskable interrupt selected) wdt1 0020h 00000020h note 1 ? non- maskable interrupt ? intwdt2 wdt2 overflow (when non- maskable interrupt selected) wdt2 0030h 00000030h note 1 ? ? trap0n note 2 trap instruction ? 004nh note 2 00000040h nextpc ? software exception exception ? trap1n note 2 trap instruction ? 005nh note 2 00000050h nextpc ? exception trap exception ? ilgop/ dbg0 illegal op code/dbtrap instruction ? 0060h 00000060h nextpc ? 0 intwdtm1 wdt1 overflow (when interval timer selected) wdt1 0080h 00000080h nextpc wdt1ic 1 intp0 intp0 pin valid edge input pin 0090h 00000090h nextpc pic0 2 intp1 intp1 pin valid edge input pin 00a0h 000000a0h nextpc pic1 3 intp2 intp2 pin valid edge input pin 00b0h 000000b0h nextpc pic2 4 intp3 intp3 pin valid edge input pin 00c0h 000000c0h nextpc pic3 5 intp4 intp4 pin valid edge input pin 00d0h 000000d0h nextpc pic4 6 intp5 intp5 pin valid edge input pin 00e0h 000000e0h nextpc pic5 7 intp6 intp6 pin valid edge input pin 00f0h 000000f0h nextpc pic6 8 inttm000 tm00 and cr000 match tm00 0100h 00000100h nextpc tm0ic00 9 inttm001 tm00 and cr001 match tm00 0110h 00000110h nextpc tm0ic01 10 inttm010 tm01 and cr010 match tm01 0120h 00000120h nextpc tm0ic10 11 inttm011 tm01 and cr011 match tm01 0130h 00000130h nextpc tm0ic11 12 inttm50 tm50 and cr50 match tm50 0140h 00000140h nextpc tm5ic0 13 inttm51 tm51 and cr51 match tm51 0150h 00000150h nextpc tm5ic1 14 intcsi00 csi00 transfer completion csi00 0160h 00000160h nextpc csi0ic0 15 intcsi01 csi01 transfer completion csi01 0170h 00000170h nextpc csi0ic1 16 intsre0 uart0 reception error occurrence uart0 0180h 00000180h nextpc sreic0 17 intsr0 uart0 reception completion uart0 0190h 00000190h nextpc sric0 18 intst0 uart0 transmission completion uart0 01a0h 000001ah nextpc stic0 19 intsre1 uart1 reception error occurrence uart1 01b0h 000001b0h nextpc sreic1 20 intsr1 uart1 reception completion uart1 01c0h 000001c0h nextpc sric1 maskable interrupt 21 intst1 uart1 transmission completion uart1 01d0h 000001d0h nextpc stic1 notes 1. for restoration in the case of intwdt1 and intwdt2, refer to 21.10 cautions . 2. n = 0 to fh chapter 21 interrupt/exception processing function preliminary user?s manual u17702ej1v0ud 682 table 21-1. interrupt source list (2/3) type classification default priority name trigger interrupt source exception code handler address restored pc interrupt control register 22 inttmh0 tmh0 and cmp00/cmp01 match tmh0 01e0h 000001e0h nextpc tmhic0 23 inttmh1 tmh1 and cmp10/cmp11 match tmh1 01f0h 000001f0h nextpc tmhic1 24 intcsia0 csia0 transfer completion csia0 0200h 00000200h nextpc csiaic0 25 intiic0 i 2 c0 transfer completion i 2 c0 0210h 00000210h nextpc iicic0 26 intad a/d conversion completion a/d 0220h 00000220h nextpc adic 27 intkr key return interrupt kr 0230h 00000230h nextpc kric 28 intwti watch timer interval wt 0240h 00000240h nextpc wtiic 29 intwt watch timer reference time wt 0250h 00000250h nextpc wtic 30 intbrg 8-bit counter of prescaler 3 and prscm match prescaler 3 0260h 00000260h nextpc brgic 31 inttm020 tm02 and cr020 match tm02 0270h 00000270h nextpc tm0ic20 32 inttm021 tm02 and cr021 match tm02 0280h 00000280h nextpc tm0ic21 33 inttm030 tm03 and cr030 match tm03 0290h 00000290h nextpc tm0ic30 34 inttm031 tm03 and cr031 match tm03 02a0h 000002a0h nextpc tm0ic31 35 intcsia1 csia1 transfer completion csia1 02b0h 000002b0h nextpc csiaic1 36 inttm040 tm04 and cr040 match tm04 02c0h 000002c0h nextpc tm0ic40 37 inttm041 tm04 and cr041 match tm04 02d0h 000002d0h nextpc tm0ic41 38 inttm050 tm05 and cr050 match tm05 02e0h 000002e0h nextpc tm0ic50 39 inttm051 tm05 and cr051 match tm05 02f0h 000002f0h nextpc tm0ic51 40 intcsi02 csi02 transfer completion csi02 0300h 00000300h nextpc csi0ic2 41 intsre2 uart2 reception error occurrence uart2 0310h 00000310h nextpc sreic2 42 intsr2 uart2 reception completion uart2 0320h 00000320h nextpc sric2 43 intst2 uart2 transmission completion uart2 0330h 00000330h nextpc stic2 44 intiic1 i 2 c1 transfer completion i 2 c1 0340h 00000340h nextpc iicic1 45 intp7 intp7 pin valid edge input pin 0390h 00000390h nextpc pic7 maskable interrupt 46 inttp0ov tmp0 overflow tmp 03a0h 000003a0h nextpc tpovic chapter 21 interrupt/exception processing function preliminary user?s manual u17702ej1v0ud 683 table 21-1. interrupt source list (3/3) type classification default priority name trigger interrupt source exception code handler address restored pc interrupt control register 47 inttp0cc0 tmp0 capture 0/ compare 0 match tmp 03b0h 000003b0h nextpc tpccic0 48 inttp0cc1 tmp0 capture 1/ compare 1 match tmp 03c0h 000003c0h nextpc tpccic1 49 intdma0 dma0 transfer completion dmac 03d0h 000003d0h nextpc dmaic0 50 intdma1 dma1 transfer completion dmac 03e0h 000003e0h nextpc dmaic1 51 intdma2 dma2 transfer completion dmac 03f0h 000003f0h nextpc dmaic2 maskable interrupt 52 intdma3 dma3 transfer completion dmac 0400h 00000400h nextpc dmaic3 remarks 1. default priority: the priority order when two or more maskable interrupt requests with the same priority level are generated at the sa me time. the highest priority is 0. the priority of non-maskable interrupt request is as follows. intwdt2 > intwdt1 > nmi restored pc: the value of the program counter (pc) saved to eipc, fepc, or dbpc when interrupt/exception processing is started. the restored pc when a non-maskable or maskable interrupt is acknowledged while either of the following instructions is being executed does not become nextpc (when an interrupt is acknowledged during the execution of an instruction, the execution of that in struction is stopped and is resumed following completion of interrupt servicing). ? load instructions (sld.b, sld.bu, sld.h, sld.hu, sld.w) ? divide instructions (div, divh, divu, divhu) ? prepare, dispose instructions (only w hen an interrupt occurs before stack pointer update) nextpc: the pc value at which processing is st arted following interrupt/exception processing. 2. the execution address of the illegal op code when an illegal op code exception occurs is calculated with (restored pc ? 4). chapter 21 interrupt/exception processing function preliminary user?s manual u17702ej1v0ud 684 21.2 non-maskable interrupts non-maskable interrupt request signals are acknowledged unconditionally, even when interrupts are disabled (di state). non-maskable interrupts (nmi) are not subject to pr iority control and take precedence over all other interrupt request signals. the following three types of non-maskable interrupt request signals are available in the v850es/kj2. ? nmi pin input (nmi) ? non-maskable interrupt request signal (intwdt1) due to overflow of watchdog timer 1 ? non-maskable interrupt request signal (intwdt2) due to overflow of watchdog timer 2 there are four choices for the valid edge of an nmi pin, namely: rising edge, falling edge, both edges, and no edge detection. the non-maskable interrupt request signal (intwdt1) due to overflow of watchdog timer 1 functions by setting the wdtm1.wdtm14 and wdtm1.wdtm13 bits to 10. the non-maskable interrupt request signal (intwdt2) due to overflow of watchdog timer 2 functions by setting the wdtm2.wdm21 and wdtm2.wdm20 bits to 01. when two or more non-maskable interrupts occur simultane ously, they are processed in a sequence determined by the following priority order (the interrupt requ est signals with low priority level are ignored). intwdt2 > intwdt1 > nmi if during nmi processing, an nmi, intwdt1, or intwdt2 r equest signal newly occurs, processing is performed as follows. (1) if an nmi request signal newly occurs during nmi processing the new nmi request signal is held pending regard less of the value of the psw.np bit. the nmi request signal held pending is acknowledged upon completi on of processing of the nm i currently being executed (following reti instruction execution). (2) if an intwdt1 request signal newly occurs during nmi processing if the np bit remains set (to 1) during nmi processing, the new intwdt1 request signal is held pending. the intwdt1 request signal held pending is acknowledged upon completion of processing of the nmi currently being executed (following re ti instruction execution). if the np bit is cleared (to 0) during nmi processing, a newly generated intwdt1 request signal is executed (nmi processing is interrupted). (3) if an intwdt2 request signal newly occurs during nmi processing a newly generated intwdt2 request signal is executed re gardless of the value of the np bit (nmi processing is interrupted). caution for non-maskable interrupt servicing from non-maskable interrupt re quest signals (intwdt1, intwdt2), refer to 21.10 cautions. chapter 21 interrupt/exception processing function preliminary user?s manual u17702ej1v0ud 685 figure 21-1. acknowledging non-maskab le interrupt request signals (1/2) (a) if two or more nmi request si gnals are simultan eously generated main routine system reset nmi, intwdt2 request (simultaneously generated) intwdt2 processing nmi and intwdt2 requests simultaneously generated main routine system reset nmi, intwdt1 request (simultaneously generated) intwdt1 processing nmi and intwdt1 requests simultaneously generated main routine system reset nmi, intwdt1, intwdt2 requests (simultaneously generated) intwdt2 processing nmi, intwdt1, and intwdt2 requests simultaneously generated main routine system reset intwdt1, intwdt2 request (simultaneously generated) intwdt2 processing intwdt1 and intwdt2 requests simultaneously generated chapter 21 interrupt/exception processing function preliminary user?s manual u17702ej1v0ud 686 figure 21-1. acknowledging non-maskab le interrupt request signals (2/2) (b) if a new non-maskable interr upt request signal is generated during a non-maskable interrupt servicing non-maskable interrupt currently being serviced non-maskable interrupt request newly generated during non-maskable interrupt servicing nmi intwdt1 intwdt2 nmi generation of nmi request during nmi processing generation of intwdt1 request during nmi processing (np = 1 state prior to intwdt1 request is maintained) generation of intwdt1 request during nmi processing (set np = 0 before intwdt1 request) generation of intwdt1 request during nmi processing (set np = 0 after intwdt1 request) generation of intwdt2 request during nmi processing main routine nmi request nmi processing (held pending) nmi processing nmi request (hold pending) main routine system reset nmi request nmi request nmi processing intwdt1 processing (hold pending) main routine system reset nmi request nmi request nmi processing intwdt1 processing intwdt1 request np = 0 np = 0 main routine system reset intwdt2 request nmi processing intwdt2 processing generation of intwdt2 request during intwdt1 processing main routine system reset intwdt1 request intwdt1 processing intwdt2 processing intwdt2 request main routine system reset nmi processing intwdt1 processing intwdt1 (hold pending) request intwdt1 (invalid) request generation of intwdt1 request during intwdt1 processing main routine system reset intwdt1 processing generation of nmi request during intwdt1 processing intwdt1 intwdt2 main routine system reset intwdt1 request intwdt1 request intwdt1 processing nmi request (invalid) nmi request (invalid) generation of intwdt2 request during intwdt2 processing generation of intwdt1 request during intwdt2 processing main routine system reset intwdt2 processing main routine system reset intwdt2 processing generation of nmi request during intwdt2 processing main routine system reset intwdt2 request intwdt2 request intwdt2 processing intwdt1 (invalid) request intwdt2 (invalid) request intwdt1 request chapter 21 interrupt/exception processing function preliminary user?s manual u17702ej1v0ud 687 21.2.1 operation upon generation of a non-maskable interrupt request si gnal, the cpu performs the following processing and transfers control to a handler routine. <1> saves the restored pc to fepc. <2> saves the current psw to fepsw. <3> writes the exception code (0010h, 0020h, 0030h ) to the higher halfword (fecc) of ecr. <4> sets the psw.np and psw.id bits to 1 and clears the psw.ep bit to 0. <5> loads the handler address (00000010h, 00000020h, 00000030h) of the non-maskable interrupt to the pc and transfers control. figure 21-2 shows the servicing flow for non-maskable interrupts. figure 21-2. non-maskable interrupt servicing nmi input non-maskable interrupt request interrupt servicing interrupt request held pending fepc fepsw ecr. fecc psw. np psw. ep psw. id pc restored pc psw exception code 1 0 1 handler address intc acknowledged cpu processing psw. np 1 0 chapter 21 interrupt/exception processing function preliminary user?s manual u17702ej1v0ud 688 21.2.2 restore execution is restored from non-maskable inte rrupt servicing by the reti instruction. (1) in case of nmi restore from nmi processing is done with the reti instruction. when the reti instruction is executed , the cpu performs the following processing and transfers control to the address of the restored pc. (i) loads the values of the restored pc and psw from fepc and fepsw , respectively, because the psw.ep bit and the psw.np bit are 0 and 1, respectively. (ii) transfers control back to the load ed address of the restored pc and psw. figure 21-3 shows the processing fl ow of the reti instruction. figure 21-3. reti instruction processing psw.ep reti instruction pc psw eipc eipsw psw.np original processing restored pc psw fepc fepsw 1 1 0 0 caution when the ep bit and the np bit are changed by the ldsr instruction dur ing non-maskable interrupt servicing, in order to restore the pc and psw correctly during restoring by the reti instruction, it is necessary to clear the ep bit back to 0 and set the np bit back to 1 using the ldsr instruction immediately be fore the reti instruction. remark the solid line shows the cpu processing flow. (2) in case of intwdt1 and intwdt2 signals for non-maskable interrupt servicing by the non-maskabl e interrupt request signals (intwdt1, intwdt2), refer to 21.10 cautions . chapter 21 interrupt/exception processing function preliminary user?s manual u17702ej1v0ud 689 21.2.3 np flag the np flag is a status flag that indicates that non-maskable interrupt servicing is in progress. this flag is set when a non-maskable interrupt request has been acknowledged, and masks all non-maskable requests to prevent multiple interrupts. 0 np ep id sat cy ov s z psw no non-maskable interrupt servicing non-maskable interrupt serving in progress np 0 1 nmi servicing status after reset: 00000020h chapter 21 interrupt/exception processing function preliminary user?s manual u17702ej1v0ud 690 21.3 maskable interrupts maskable interrupt request signals can be masked by interrupt control register s. the v850es/kj2 has 53 maskable interrupt sources (refer to 21.1.1 features ). if two or more maskable interrupt request signals are generated at the same time, they are acknowledged according to the default priority. in addition to the default pr iority, eight levels of interrupt priorities can be specified by using the interrupt control registers, allowing programmable priority control. when an interrupt request signal has been acknowledged, the interrupt disabled (di) status is set and the acknowledgment of other maskable inte rrupt request signals is disabled. when the ei instruction is executed in an interrupt servicing routine, the interr upt enabled (ei) status is set, which enables acknowledgment of interrupt request signals having a priority higher than that of the interrupt request signal currently in progress. note that only interrupt request signals with a higher priority have this capability; interrupt request signals with the same priority level cannot be nested. to use multiple interrupts, it is neces sary to save eipc and eipsw to memory or a register befor e executing the ei instruction, and restore eipc and eipsw to the original values by executing the di instruction before the reti instruction. when the wdtm1.wdtm14 bit is cleared to 0, the watchdog timer 1 overflow interrupt functions as a maskable interrupt (intwdtm1). 21.3.1 operation if a maskable interrupt request signal is generated, t he cpu performs the following processing and transfers control to a handler routine. <1> saves the restored pc to eipc. <2> saves the current psw to eipsw. <3> writes an exception code to t he lower halfword of ecr (eicc). <4> sets the psw.id bit to 1 and clears the psw.ep bit to 0. <5> loads the corresponding handler addr ess to the pc and transfers control. the maskable interrupt request signal masked by intc and the maskable interrupt request signal that occurs while another interrupt is being serviced (when psw.np bit = 1 or id bit = 1) are held pending internally. when the interrupts are unmasked, or when the np bit = 0 and the id bit = 0 by using the reti and ldsr instructions, a new maskable interrupt servicing is started in accordance with th e priority of the pending maskable interrupt request signal. figure 21-4 shows the servicing flow for maskable interrupts. chapter 21 interrupt/exception processing function preliminary user?s manual u17702ej1v0ud 691 figure 21-4. maskable interrupt servicing maskable interrupt request interrupt servicing eipc eipsw ecr. eicc psw. ep psw. id ispr. corresponding- bit note pc intc acknowledged cpu processing interrupt mask released? priority higher than that of interrupt currently being serviced? interrupt request pending psw. np psw. id interrupt request pending no no no no 1 0 1 0 int input yes yes yes yes priority higher than that of other interrupt requests? highest default priority of interrupt requests with the same priority? restored pc psw exception code 0 1 1 handler address note for the ispr register, refer to 21.3.6 in-service prio rity register (ispr) . chapter 21 interrupt/exception processing function preliminary user?s manual u17702ej1v0ud 692 21.3.2 restore execution is restored from maskable interrupt servicing by the reti instruction. when the reti instruction is execut ed, the cpu performs the following processing and transfers control to the address of the restored pc. (1) loads the values of the restored pc and psw fr om eipc and eipsw because the psw.ep bit and the psw.np bit are both 0. (2) transfers control to the loaded address of the restored pc and psw. figure 21-5 shows the processing fl ow of the reti instruction. figure 21-5. reti instruction processing reti instruction original processing restored pc psw ispr. corresponding -bit note eipc eipsw 0 psw. ep 1 0 1 0 pc psw fepc fepsw psw. np note for the ispr register, refer to 21.3.6 in-service prio rity register (ispr) . caution when the ep bit and the np bit are ch anged by the ldsr instruction during maskable interrupt servicing, in order to restore the pc and psw correctly during restoring by the reti instruction, it is necessary to clear the ep bit back to 0 and the np bit back to 0 using the ldsr instruction immediately be fore the reti instruction. remark the solid line shows the cpu processing flow. chapter 21 interrupt/exception processing function preliminary user?s manual u17702ej1v0ud 693 21.3.3 priorities of maskable interrupts intc provides a multiple interrupt servicing in which an interrupt can be acknowledged while another interrupt is being serviced. multiple interrupts can be controlled by priority levels. there are two types of priority leve l control: control based on the default pr iority levels, and control based on the programmable priority levels specified by the interrupt priority level specificat ion bit (xxicn.xxprn bit). when two or more interrupts having the same priority level specifi ed by xxprn are generated at the same time, interrupts are serviced in order depending on the priority level allocated to each interrupt request (default priority level) beforehand. for more information, refer to table 21-1 interrupt source list . programmable priority control divides interrupt requests into eight levels by setting the priority level specification flag. note that when an interrupt request signal is acknowledged , the psw.id flag is automatically set (1). therefore, when multiple interrupts are to be used, clear (0) the id flag bef orehand (for example, by plac ing the ei instruction into the interrupt service program) to enable interrupts. remark xx: identifying name of eac h peripheral unit (refer to table 21-2 interrupt control registers (xxicn) ) n: peripheral unit number (refer to table 21-2 interrupt control registers (xxicn) ) chapter 21 interrupt/exception processing function preliminary user?s manual u17702ej1v0ud 694 figure 21-6. example of interrupt nesting (1/2) main routine ei ei interrupt request a (level 3) servicing of a servicing of b interrupt request b (level 2) servicing of c interrupt request c (level 3) interrupt request d (level 2) servicing of d servicing of e ei interrupt request e (level 2) interrupt request f (level 3) servicing of f ei servicing of g interrupt request g (level 1) interrupt request h (level 1) servicing of h interrupt request h is held pending even if interrupts are enabled because its priority is the same as that of g. interrupt request f is held pending even if interrupts are enabled because its priority is lower than that of e. interrupt request b is acknowledged because the priority of b is higher than that of a and interrupts are enabled. although the priority of interrupt request d is higher than that of c, d is held pending because interrupts are disabled. caution the values of eipc and eipsw must be saved before executing multiple interrupts. remarks 1. a to u in the figure are the names of interrupt request signals shown for the sake of explanation. 2. the default priority in the figure indicates the re lative priority between two interrupt request signals. chapter 21 interrupt/exception processing function preliminary user?s manual u17702ej1v0ud 695 figure 21-6. example of interrupt nesting (2/2) main routine ei interrupt request i (level 2) servicing of i servicing of k interrupt request j (level 3) servicing of j interrupt request l (level 2) ei ei ei ei interrupt request o (level 3) interrupt request s (level 1) interrupt request k (level 1) servicing of l servicing of n servicing of m servicing of s servicing of u servicing of t interrupt request m (level 3) interrupt request n (level 1) servicing of o interrupt request p (level 2) interrupt request q (level 1) interrupt request r (level 0) interrupt request u (level 2) note 2 interrupt request t (level 2) note 1 servicing of p servicing of q servicing of r ei if levels 3 to 0 are acknowledged interrupt request j is held pending because its priority is lower than that of i. k that occurs after j is acknowledged because it has the higher priority. interrupt requests m and n are held pending because servicing of l is performed in the interrupt disabled status. pending interrupt requests are acknowledged after servicing of interrupt request l. at this time, interrupt requests n is acknowledged first even though m has occurred first because the priority of n is higher than that of m. pending interrupt requests t and u are acknowledged after processing of s. because the priorities of t and u are the same, u is acknowledged first because it has the higher default priority, regardless of the order in which the interrupt requests have been generated. notes 1. lower default priority 2. higher default priority chapter 21 interrupt/exception processing function preliminary user?s manual u17702ej1v0ud 696 figure 21-7. example of servicing simultan eously generated inte rrupt request signals main routine ei interrupt request a (level 2) interrupt request b (level 1) note 1 interrupt request c (level 1) note 2 servicing of interrupt request b servicing of interrupt request c servicing of interrupt request a interrupt requests b and c are acknowledged first according to their priorities. because the priorities of b and c are the same, b is acknowledged first because it has the higher default priority. notes 1. higher default priority 2. lower default priority chapter 21 interrupt/exception processing function preliminary user?s manual u17702ej1v0ud 697 21.3.4 interrupt control register (xxlcn) an interrupt control register is assigned to each maska ble interrupt and sets the control conditions for each maskable interrupt request. the interrupt control registers can be read or written in 8-bit or 1-bit units. reset sets this register to 47h. caution be sure to read the xxicn. xxifn bit while interrupts are disabled (d i). if the xxifn bit is read while interrupts are enabled (e i), an incorrect value may be read if there is a conflict between acknowledgment of the interrupt and reading of the bit. xxifn interrupt request not generated interrupt request generated xxifn 0 1 interrupt request flag note xxicn xxmkn 0 0 0 xxprn2 xxprn1 xxprn0 enables interrupt servicing disables interrupt servicing (pending) xxmkn 0 1 interrupt mask flag specifies level 0 (highest) specifies level 1 specifies level 2 specifies level 3 specifies level 4 specifies level 5 specifies level 6 specifies level 7 (lowest) xxprn2 0 0 0 0 1 1 1 1 interrupt priority specification bit xxprn1 0 0 1 1 0 0 1 1 xxprn0 0 1 0 1 0 1 0 1 after reset: 47h r/w address: fffff110h to fffff168h < > < > note automatically reset by hardware when interrupt request is acknowledged. remark xx: identifying name of eac h peripheral unit (refer to table 21-2 interrupt control registers (xxicn) ) n: peripheral unit number (refer to table 21-2 interrupt control registers (xxicn) ) following tables list the addresses and bits of the interrupt control registers. chapter 21 interrupt/exception processing function preliminary user?s manual u17702ej1v0ud 698 table 21-2. interrupt cont rol registers (xxlcn) (1/2) bits address register <7> <6> 5 4 3 2 1 0 fffff110h wdt1ic wdt1if wdt1mk 0 0 0 wdt1pr2 wdt1pr1 wdt1pr0 fffff112h pic0 pif0 pmk0 0 0 0 ppr02 ppr01 ppr00 fffff114h pic1 pif1 pmk1 0 0 0 ppr12 ppr11 ppr10 fffff116h pic2 pif2 pmk2 0 0 0 ppr22 ppr21 ppr20 fffff118h pic3 pif3 pmk3 0 0 0 ppr32 ppr31 ppr30 fffff11ah pic4 pif4 pmk4 0 0 0 ppr42 ppr41 ppr40 fffff11ch pic5 pif5 pmk5 0 0 0 ppr52 ppr51 ppr50 fffff11eh pic6 pif6 pmk6 0 0 0 ppr62 ppr61 ppr60 fffff120h tm0ic00 tm0if00 tm0mk00 0 0 0 tm0pr002 tm0pr001 tm0pr000 fffff122h tm0ic01 tm0if01 tm0mk01 0 0 0 tm0pr012 tm0pr011 tm0pr010 fffff124h tm0ic10 tm0if10 tm0mk10 0 0 0 tm0pr102 tm0pr101 tm0pr100 fffff126h tm0ic11 tm0if11 tm0mk11 0 0 0 tm0pr112 tm0pr111 tm0pr110 fffff128h tm5ic0 tm5if0 tm5mk0 0 0 0 tm5pr02 tm5pr01 tm5pr00 fffff12ah tm5ic1 tm5if1 tm5mk1 0 0 0 tm5pr12 tm5pr11 tm5pr10 fffff12ch csi0ic0 csi0if0 csi0mk0 0 0 0 csi0pr02 csi0pr01 csi0pr00 fffff12eh csi0ic1 csi0if1 csi0mk1 0 0 0 csi0pr12 csi0pr11 csi0pr10 fffff130h sreic0 sreif0 sremk0 0 0 0 srepr02 srepr01 srepr00 fffff132h sric0 srif0 srmk0 0 0 0 srpr02 srpr01 srpr00 fffff134h stic0 stif0 stmk0 0 0 0 stpr02 stpr01 stpr00 fffff136h sreic1 sreif1 sremk1 0 0 0 srepr12 srepr11 srepr10 fffff138h sric1 srif1 srmk1 0 0 0 srpr12 srpr11 srpr10 fffff13ah stic1 stif1 stmk1 0 0 0 stpr12 stpr11 stpr10 fffff13ch tmhic0 tmhif0 tmhmk0 0 0 0 tmhpr02 tmhpr01 tmhpr00 fffff13eh tmhic1 tmhif1 tmhmk1 0 0 0 tmhpr12 tmhpr11 tmhpr10 fffff140h csiaic0 csiaif0 csiamk0 0 0 0 csiapr02 csiapr01 csiapr00 fffff142h iicic0 iicif0 iicmk0 0 0 0 iicpr02 iicpr01 iicpr00 fffff144h adic adif admk 0 0 0 adpr2 adpr1 adpr0 fffff146h kric krif krmk 0 0 0 krpr2 krpr1 krpr0 fffff148h wtiic wtiif wtimk 0 0 0 wtipr2 wtipr1 wtipr0 fffff14ah wtic wtif wtmk 0 0 0 wtpr2 wtpr1 wtpr0 fffff14ch brgic brgif brgmk 0 0 0 brgpr2 brgpr1 brgpr0 fffff14eh tm0ic20 tm0if20 tm0mk20 0 0 0 tm0pr202 tm0pr201 tm0pr200 fffff150h tm0ic21 tm0if21 tm0mk21 0 0 0 tm0pr212 tm0pr211 tm0pr210 fffff152h tm0ic30 tm0if30 tm0mk30 0 0 0 tm0pr302 tm0pr301 tm0pr300 fffff154h tm0ic31 tm0if31 tm0mk31 0 0 0 tm0pr312 tm0pr311 tm0pr310 fffff156h csiaic1 csiaif1 csiamk1 0 0 0 csiapr12 csiapr11 csiapr10 fffff158h tm0ic40 tm0if40 tm0mk40 0 0 0 tm0pr402 tm0pr401 tm0pr400 fffff15ah tm0ic41 tm0if41 tm0mk41 0 0 0 tm0pr412 tm0pr411 tm0pr410 fffff15ch tm0ic50 tm0if50 tm0mk50 0 0 0 tm0pr502 tm0pr501 tm0pr500 fffff15eh tm0ic51 tm0if51 tm0mk51 0 0 0 tm0pr512 tm0pr511 tm0pr510 fffff160h csi0ic2 csi0if2 csi0mk2 0 0 0 csi0pr22 csi0pr21 csi0pr20 chapter 21 interrupt/exception processing function preliminary user?s manual u17702ej1v0ud 699 table 21-2. interrupt cont rol registers (xxlcn) (2/2) bits address register <7> <6> 5 4 3 2 1 0 fffff162h sreic2 sreif2 sremk2 0 0 0 srepr22 srepr21 srepr20 fffff164h sric2 srif2 srmk2 0 0 0 srpr22 srpr21 srpr20 fffff166h stic2 stif2 stmk2 0 0 0 stpr22 stpr21 stpr20 fffff168h iicic1 iicif1 iicmk1 0 0 0 iicpr12 iicpr11 iicpr10 fffff172h pic7 pif7 pmk7 0 0 0 ppr72 ppr71 ppr70 fffff174h tp0ovic tp0ovif tp0ovmk 0 0 0 tp0ovpr2 tp0ovpr1 tp0ovpr0 fffff176h tp0ccic0 tp0ccif0 tp0ccmk0 0 0 0 tp0ccpr02 tp0ccpr01 tp0ccpr00 fffff178h tp0ccic1 tp0ccif1 tp0ccmk1 0 0 0 tp0ccpr12 tp0ccpr11 tp0ccpr10 fffff17ah dmaic0 dmaif0 dmamk0 0 0 0 dmapr02 dmapr01 dmapr00 fffff17ch dmaic1 dmaif1 dmamk1 0 0 0 dmapr12 dmapr11 dmapr10 fffff17eh dmaic2 dmaif2 dmamk2 0 0 0 dmapr22 dmapr21 dmapr20 fffff180h dmaic3 dmaif3 dmamk3 0 0 0 dmapr32 dmapr31 dmapr30 chapter 21 interrupt/exception processing function preliminary user?s manual u17702ej1v0ud 700 21.3.5 interrupt mask register s 0 to 3 (imr0 to imr3) these registers set the interrupt mask status for maskable in terrupts. the xxmkn bit of the imr0 to imr3 registers and the xxmkn bit of the xxlcn regist er are respectively linked. the imrm register can be read or written in 16-bit units (m = 0 to 3). when the higher 8 bits of the imrm r egister are used as the imrmh register and the lower 8 bits of the imrm register as the imrml register, they can be read or written in 8-bit or 1-bit units (m = 0 to 2). caution in the device file, th e xxmkn bit of the xxicn register is de fined as a reserved word. therefore, if bit manipulation is performed using the name xxm kn, the xxicn register, not the imrm register, is rewritten (as a result, the imrm register is also rewritten). chapter 21 interrupt/exception processing function preliminary user?s manual u17702ej1v0ud 701 csi0mk1 pmk6 imr0 (imr0h note ) (imr0l) csi0mk0 pmk5 tm5mk1 pmk4 tm5mk0 pmk3 tm0mk11 pmk2 tm0mk10 pmk1 tm0mk01 pmk0 tm0mk00 wdt1mk after reset: ffffh r/w address: imr0 fffff100h, imr0l fffff100h, imr0h fffff101h after reset: ffffh r/w address: imr1 fffff102h, imr1l fffff102h, imr1h fffff103h after reset: ffffh r/w address: imr2 fffff104h, imr2l fffff104h, imr2h fffff105h tm0mk20 tmhmk1 imr1 (imr1h note ) (imr1l) brgmk tmhmk0 wtmk stmk1 wtimk srmk1 krmk sremk1 admk stmk0 iicmk0 srmk0 csiamk0 sremk0 1 tm0mk51 xxmkn 0 1 enables interrupt servicing disables interrupt servicing imr2 (imr2h note ) (imr2l) 1 tm0mk50 1 tm0mk41 iicmk1 tm0mk40 stmk2 csiamk1 srmk2 tm0mk31 sremk2 tm0mk30 csi0mk2 tm0mk21 8 9 10 11 12 13 14 15 1 2 3 4 5 6 7 0 8 9 10 11 12 13 14 15 1 2 3 4 5 6 7 0 8 9 10 11 12 13 interrupt mask flag setting 14 15 1 2 3 4 5 6 7 0 after reset: ffffh r/w address: imr3 fffff106h, imr3l fffff106h, imr3h fffff107h 1 dmamk2 imr3 (imr3h note ) (imr3l) 1 dmamk1 1 dmamk0 1 tp0ccmk1 1 tp0ccmk2 1 tp0ovfmk 1 pmk7 dmamk3 1 8 9 10 11 12 13 14 15 1 2 3 4 5 6 7 0 note when reading from or writing to bits 8 to 15 of the imr0 to imr3 registers in 8-bit or 1-bit units, specify these bits as bits 0 to 7 of the imr0h to imr3h registers. caution set bits 15 to 13 of the imr2 register and bits 15 to 9 and 0 of the imr3 register to 1. the operation is not guaran teed if their value is changed. remark xx: identifying name of eac h peripheral unit (refer to table 21-2 interrupt control registers (xxicn) ) n: peripheral unit number (refer to table 21-2 interrupt control registers (xxicn) ) chapter 21 interrupt/exception processing function preliminary user?s manual u17702ej1v0ud 702 21.3.6 in-service priority register (ispr) this register holds the priority level of the maskable in terrupt currently being ackno wledged. when the interrupt request signal is acknowledged, the bit of this register corres ponding to the priority level of that interrupt request signal is set (1) and remains set while the interrupt is being serviced. when the reti instruction is executed, t he bit among those that are set (1) in t he ispr register that corresponds to the interrupt request signal having the highest priority is aut omatically cleared (0) by hardw are. however, it is not cleared (0) when execution is returned from non-maskab le interrupt servicing or exception processing. this register is read-only in 8-bit or 1-bit units. reset sets this register to 00h. caution if an interrupt is acknowledged while the ispr register is being read in the interrupt enabled (ei) status, the value of the ispr register after th e bits of the register have been set to 1 by acknowledging the interrupt may be read. to accura tely read the value of the ispr register before an interrupt is acknowledge d, read the register while inte rrupts are disabled (di status). ispr7 interrupt request with priority n is not acknowledged interrupt request with priority n is being acknowledged isprn 0 1 priority of interrupt currently being acknowledged ispr ispr6 ispr5 ispr4 ispr3 ispr2 ispr1 ispr0 after reset: 00h r address: fffff1fah < > < > < > < > < > < > < > < > remark n = 0 to 7 (priority level) chapter 21 interrupt/exception processing function preliminary user?s manual u17702ej1v0ud 703 21.3.7 id flag the interrupt disable flag (id) is allocated to the psw and controls the maskable inte rrupt?s operating state, and stores control information regarding enabling/disa bling reception of interrupt request signals. reset sets this flag to 00000020h. 0 np ep id sat cy ov s z psw maskable interrupt request signal acknowledgment enabled maskable interrupt request signal acknowledgment disabled id 0 1 maskable interrupt servicing specification note after reset: 00000020h note interrupt disable flag (id) function id is set (1) by the di instruction and cleared (0) by the ei instruction. its value is also modified by the reti instruction or ld sr instruction when referencing the psw. non-maskable interrupt request signals and e xceptions are acknowledged regardless of this flag. when a maskable interrupt reques t signal is acknowledged, the id flag is automatically set (1) by hardware. an interrupt request signal generated during t he acknowledgment disabled period (id flag = 1) can be acknowledged when the xxicn.xxifn bit is set (1), and the id flag is cleared (0). chapter 21 interrupt/exception processing function preliminary user?s manual u17702ej1v0ud 704 21.3.8 watchdog timer mode register 1 (wdtm1) this register is a special register that can be written to only in a s pecial sequence. to generate a maskable interrupt (intwdt1), clear the wdtm14 bit to 0. this register can be read or written in 8- bit or 1-bit units (for details, refer to chapter 12 watchdog timer functions ). run1 stop count operation clear counter and start count operation run1 0 1 watchdog timer operation mode selection note 1 wdtm1 0 0 wdtm14 wdtm13 0 0 0 after reset: 00h r/w address: fffff6c2h interval timer mode (generate maskable interrupt intwdtm1 when overflow occurs) watchdog timer mode 1 note 3 (generate non-maskable interrupt intwdt1 when overflow occurs) watchdog timer mode 2 (start wdtres2 reset operation when overflow occurs) wdtm14 0 0 1 1 wdtm13 0 1 0 1 watchdog timer operation mode selection note 2 < > notes 1. once the run1 bit has been set (1), it cannot be cleared (0) by software. therefore, once counting starts, it cannot be stopped except reset. 2. once the wdtm14 and wdtm13 bits have bee n set (1), they cannot be cleared (0) by software. reset is the only way to clear these bits. 3. for non-maskable interrupt servicing due to a non-maskable interrupt request signal (intwdt1), refer to 21.10 cautions . chapter 21 interrupt/exception processing function preliminary user?s manual u17702ej1v0ud 705 21.4 external interrupt request i nput pins (nmi, intp0 to intp7) 21.4.1 noise elimination (1) noise elimination for nmi pin the nmi pin includes a noise eliminator that operates using analog delay. therefore, a signal input to the nmi pin is not detected as an edge unless it maintains its input level for a cert ain period. the edge is detected only after a certain period has elapsed. the nmi pin is used for releasing the stop mode. in the stop mode, noise elim ination using the system clock is not performed because the internal system clock is stopped. (2) noise elimination for intp0 to intp2 and intp4 to intp7 pins the intp0 to intp2 and intp4 to intp7 pins include a noise eliminator that operat es using analog delay. therefore, a signal input to each pin is not detected as an edge unless it ma intains its input level for a certain period. the edge is detected only after a certain period has elapsed. (3) noise elimination for intp3 pin the intp3 pin has a digital/analog noise eliminat or that can be selected by the nfc.nfen bit. the number of times the digital noise eliminator samp les signals can be selected by the nfc.nfsts bit from three or two. the sampling clock can be selected by the nfc.nfc2 to nfc.nfc0 bits from f xx /64, f xx /128, f xx /256, f xx /512, f xx /1024, and f xt . if the sampling clock is set to f xx /64, f xx /128, f xx /256, f xx /512, or f xx /1024, the sampling clock stops in the idle/stop mode. it c annot therefore be used to release the standby mode. to release the standby mode, select f xt as the sampling clock or select the analog noise eliminator. chapter 21 interrupt/exception processing function preliminary user?s manual u17702ej1v0ud 706 (a) digital noise eliminat ion control register (nfc) the nfc register controls elimination of noise on the intp3 pin. if f xt is used as the noise elimination clock, the external interrupt function of the in tp3 pin can be used even in the idle/stop mode. this register can be read or written in 8-bit or 1-bit units. reset sets this register to 00h. nfen analog noise elimination digital noise elimination nfen 0 1 setting of intp3 pin noise elimination nfc nfsts 0 0 0 nfc2 nfc1 nfc0 number of samplings = 3 times number of samplings = 2 times nfsts 0 1 setting of number of samplings of digital noise elimination after reset: 00h r/w address: fffff318h f xx /64 f xx /128 f xx /256 f xx /512 f xx /1024 f xt nfc2 0 0 0 0 1 1 nfc1 0 0 1 1 0 0 nfc0 0 1 0 1 0 1 selection of sampling clock setting prohibited other than above remark f xx : main clock frequency f xt : subclock frequency chapter 21 interrupt/exception processing function preliminary user?s manual u17702ej1v0ud 707 chapter 21 interrupt/exception processing function preliminary user?s manual u17702ej1v0ud 708 (1) external interrupt rising and falling e dge specification registers 0 (intr0, intf0) these are 8-bit registers t hat specify detection of the rising and fa lling edges of the nmi and intp0 to intp3 pins. these registers can be read or wri tten in 8-bit or 1-bit units. reset sets these registers to 00h. caution when switching to the port function from th e external interrupt functi on (alternate function), edge detection may be performe d. therefore, set the port m ode after setting the intf0n and intr0n bits = 00. 0 intr0 intr06 intr05 intr04 intr03 intr02 intp2 intp1 intp0 nmi 00 after reset: 00h r/w address: intr0 fffffc20h, intf0 fffffc00h intp2 intp1 intp0 nmi intp3 intp3 0 intf0 intf06 intf05 intf04 intf03 intf02 0 0 remark for specification of the valid edge, refer to table 21-3 . table 21-3. nmi and intp0 to in tp3 pins valid edge specification intf0n intr0n valid edge specification (n = 2 to 6) 0 0 no edge detection 0 1 rising edge 1 0 falling edge 1 1 both edges remark n = 2: control of nmi pin n = 3 to 6: control of intp0 to intp3 pins chapter 21 interrupt/exception processing function preliminary user?s manual u17702ej1v0ud 709 (2) external interrupt rising and falling e dge specification registers 3 (intr3, intf3) these are 8-bit registers that s pecify detection of the rising and fall ing edges of the intp7 pin. these registers can be read or wri tten in 8-bit or 1-bit units. reset sets these registers to 00h. caution when switching to the port function from th e external interrupt functi on (alternate function), edge detection may be performe d. therefore, set the port m ode after setting the intf31 and intr31 bits = 00. 0 intr3 0 0 0 0 0 intr31 0 after reset: 00h r/w address: intr3 fffffc26h, intf3 fffffc06h intp7 intp7 0 intf3 0 0 0 0 0 intf31 0 remark for specification of the valid edge, refer to table 21-4 . table 21-4. intp7 pin valid edge specification intf31 intr31 valid edge specification 0 0 no edge detection 0 1 rising edge 1 0 falling edge 1 1 both edges chapter 21 interrupt/exception processing function preliminary user?s manual u17702ej1v0ud 710 (3) external interrupt rising and falling edge specification registers 9h (intr9h, intf9h) these are 8-bit registers that s pecify detection of the rising edge of the intp4 to intp6 pins. these registers can be read or wri tten in 8-bit or 1-bit units. reset sets these registers to 00h. caution when switching to the port function from th e external interrupt functi on (alternate function), edge detection may be performe d. therefore, set the port m ode after setting the intf9n and intr9n bits = 00. intr915 intr9h intr914 intr913 0 0 0 0 0 after reset: 00h r/w address: intr9h fffffc33h, intf9h fffffc13h intp5 intp4 intp6 intp5 intp4 intp6 intf915 intf9h intf914 intf913 0 0 0 0 0 remark for specification of the valid edge, refer to table 21-5 . table 21-5. intp4 to intp6 pins valid edge specification intf9n intr9n valid edge specification (n = 13 to 15) 0 0 no edge detection 0 1 rising edge 1 0 falling edge 1 1 both edges remark n = 13 to 15: control of intp4 to intp6 pins chapter 21 interrupt/exception processing function preliminary user?s manual u17702ej1v0ud 711 21.5 software exceptions a software exception is generated when the cpu executes the trap instruction. software exceptions can always be acknowledged. 21.5.1 operation if a software exception occurs, the cpu performs the fo llowing processing and transfers control to a handler routine. <1> saves the restored pc to eipc. <2> saves the current psw to eipsw. <3> writes an exception code to the lower 16 bits (eicc) of ecr (interrupt source). <4> sets the psw.ep and psw.id bits to 1. <5> loads the handler address (00000040h or 00000050h) for the software exception routine to the pc and transfers control. figure 21-8 shows the software exception processing flow. figure 21-8. software exception processing trap instruction note eipc eipsw ecr.eicc psw.ep psw.id pc restored pc psw exception code 1 1 handler address cpu processing exception processing note trap instruction format: trap vector (however, vector = 00h to 1fh) the handler address is determined by the operand (vector) of the trap instructio n. if the vector is 00h to 1fh, the handler address is 00000040h, and if the vector is 10h to 1fh, the handler address is 00000050h. chapter 21 interrupt/exception processing function preliminary user?s manual u17702ej1v0ud 712 21.5.2 restore execution is restored from software exceptio n processing by the reti instruction. when the reti instruction is execut ed, the cpu performs the following processing and transfers control to the address of the restored pc. <1> loads the restored pc and psw from ei pc and eipsw because the psw.ep bit is 1. <2> transfers control to the address of the restored pc and psw. figure 21-9 shows the processing fl ow of the reti instruction. figure 21-9. reti instruction processing psw.ep reti instruction pc psw eipc eipsw psw.np original processing restored pc psw fepc fepsw 1 1 0 0 caution when the ep bit and the np bit are ch anged by the ldsr instruction during software exception processing, in order to restore the pc and psw correctly during restoring by the reti instruction, it is necessary to set th e ep bit back to 1 using the ldsr instruction immediately before th e reti instruction. remark the solid line shows the cpu processing flow. chapter 21 interrupt/exception processing function preliminary user?s manual u17702ej1v0ud 713 21.5.3 ep flag the ep flag is a status flag that indica tes that exception processing is in progress. it is set when an exception occurs. 0 np ep id sat cy ov s z psw exception processing not in progress exception processing in progress ep 0 1 exception processing status after reset: 00000020h chapter 21 interrupt/exception processing function preliminary user?s manual u17702ej1v0ud 714 21.6 exception trap the exception trap is an interrupt that is requested when t he illegal execution of an instruction takes place. in the v850es/kj2, an illegal op code trap (ilgop: illegal op code trap) is considered as an exception trap. 21.6.1 illegal op code an illegal op code is defined as an instruction with inst ruction op code (bits 10 to 5) = 111111b, sub-op code (bits 26 to 23) = 0111b to 1111b, and sub-op code (bit 16) = 0b. when such an instruction is executed, an exception trap is generated. 15 16 23 22 xxxxxx0 x x x x x x x x x x 1 1 1 1 1 1 x x x x x 27 26 31 0 4 5 10 11 1 1 1 1 1 1 0 1 x: don?t care caution it is recommended not to use illegal op code because instruct ions may newly be assigned in the future. (1) operation upon generation of an exception trap, the cpu performs the following processing and transfers control to a handler routine. <1> saves the restored pc to dbpc. <2> saves the current psw to dbpsw. <3> sets the psw.np, psw.ep, and psw.id bits. <4> loads the handler address (00000060h) for the except ion trap routine to the pc and transfers control. figure 21-10 shows the exception trap processing flow. chapter 21 interrupt/exception processing function preliminary user?s manual u17702ej1v0ud 715 figure 21-10. exception trap processing exception trap (ilgop) occurs dbpc dbpsw psw.np psw.ep psw.id pc restored pc psw 1 1 1 00000060h exception processing cpu processing (2) restore execution is restored from exception trap processing by the dbret instruction. when the dbret instruction is executed, the cpu performs the fo llowing processing and transfers cont rol to the address of the restored pc. <1> loads the restored pc and psw from dbpc and dbpsw. <2> transfers control to the loaded address of the restored pc and psw. figure 21-11 shows the processing flow for re store from exception trap processing. figure 21-11. processing flow fo r restore from exception trap dbret instruction pc psw dbpc dbpsw jump to restored pc address chapter 21 interrupt/exception processing function preliminary user?s manual u17702ej1v0ud 716 21.6.2 debug trap a debug trap is an exception that occurs upon execution of the dbtrap inst ruction and that can be acknowledged at all times. when a debug trap occurs, the cpu performs the following processing. (1) operation <1> saves the restored pc to dbpc. <2> saves the current psw to dbpsw. <3> sets the psw.np, psw.ep, and psw.id bits to 1. <4> sets the handler address (00000060h) for the debug trap routine to the pc and transfers control. figure 21-12 shows the debug trap processing flow. figure 21-12. debug trap processing dbtrap instruction dbpc dbpsw psw.np psw.ep psw.id pc restored pc psw 1 1 1 00000060h debug monitor routine processing cpu processing chapter 21 interrupt/exception processing function preliminary user?s manual u17702ej1v0ud 717 (2) restore execution is restored from debug trap pr ocessing by the dbret instruction. when the dbret instruction is executed, the cpu performs the following processing and tr ansfers control to the address of the restored pc. <1> loads the restored pc and psw from dbpc and dbpsw. <2> transfers control to the loaded address of the restored pc and psw. figure 21-13 shows the processing flow fo r restore from debug trap processing. figure 21-13. processing flow for restore from debug trap dbret instruction pc psw dbpc dbpsw jump to restored pc address chapter 21 interrupt/exception processing function preliminary user?s manual u17702ej1v0ud 718 21.7 multiple interru pt servicing control multiple interrupt servicing control is a function that st ops an interrupt service routine currently in progress if a higher priority interrupt request signal is generated, and processes the acknowledgm ent operation of the higher priority interrupt request signal. if an interrupt request signal with a lower or equal priority is generated and a service routi ne is currently in progress, the later interrupt request signal will be held pending. multiple interrupt servicing control is performed when inte rrupts are enabled (psw.id bit = 0). even in an interrupt servicing routine, multiple interrupt control must be performed while interrupts are enabled (id bit = 0). if a maskable interrupt or software exception is generated in a maskable interrupt or software exception service program, eipc and eipsw must be saved. the following example illustrates the procedure. (1) to acknowledge maskable interrupt re quest signals in service program service program for maskable interrupt or exception ? ? ? eipc saved to memory or register ? eipsw saved to memory or register ? ei instruction (enables interrupt acknowledgment) ? ? acknowledges maskable interrupt ? ? ? di instruction (disables interrupt acknowledgment) ? saved value restored to eipsw ? saved value restored to eipc ? reti instruction chapter 21 interrupt/exception processing function preliminary user?s manual u17702ej1v0ud 719 (2) to generate exception in service program service program for maskable interrupt or exception ? ? ? eipc saved to memory or register ? eipsw saved to memory or register ? ? trap instruction acknowledges exceptions su ch as trap instruction. ? ? saved value restored to eipsw ? saved value restored to eipc ? reti instruction priorities 0 to 7 (0 is the highest) can be set for each maskable interrupt request in multiple interrupt servicing control by software. to set a priority level, wr ite values to the xxicn.xxp rn0 to xxicn.xxprn2 bits corresponding to each maskable interrupt request. after reset, interrupt requests are masked by the xxicn.xxmkn bit, and the priority is set to level 7 by the xxprn0 to xxprn2 bits. priorities of maskable interrupts are as follows. (high) level 0 > level 1 > level 2 > level 3 > level 4 > level 5 > level 6 > level 7 (low) interrupt servicing that has been suspend ed as a result of multiple interrupt servicing control is resumed after the interrupt servicing of the higher priority has been completed and the reti inst ruction has been executed. a pending interrupt request signal is acknowledged a fter the current interrupt servicing has been completed and the reti instruction has been executed. caution in a non-maskable interrupt servicing rout ine (in the time until the reti instruction is executed), maskable interrupts are not acknowledged and held pending. chapter 21 interrupt/exception processing function preliminary user?s manual u17702ej1v0ud 720 21.8 interrupt response time except in the following cases, the cpu interrupt response ti me is a minimum of 4 clocks. if inputting consecutive interrupt request signals, at least 4 clocks must be placed between each interrupt request signal. ? idle/stop mode ? external bus access ? consecutive interrupt request non- sample instruction (refer to 21.9 periods in which interrupts are not acknowledged by cpu ) ? access to interrupt control register ? access to peripheral i/o register figure 21-14. pipeline operati on during interrupt request si gnal acknowledgment (outline) (1) minimum interrupt response time if id ex internal clock instruction 1 instruction 2 interrupt acknowledgment operation instruction (first instruction of interrupt servicing routine) interrupt request if id ex mem wb ifx idx int1 int2 int3 int4 4 system clocks (2) maximum interrupt response time if id ex internal clock instruction 1 instruction 2 interrupt acknowledgment operation instruction (first instruction of interrupt servicing routine) interrupt request if id ex mem mem mem wb ifx idx int1 int2 int3 int3 int3 int4 6 system clocks remark int1 to int4: interrupt acknowledgment processing ifx: invalid instruction fetch idx: invalid instruction decode interrupt response time (internal system clock) internal interrupt external interrupt condition min. 4 4 + analog delay max. 6 6 + analog delay the following cases are excluded. ? idle/stop mode ? external bus access ? consecutive interrupt request non-sample instruction ? access to interrupt control register ? access to peripheral i/o register chapter 21 interrupt/exception processing function preliminary user?s manual u17702ej1v0ud 721 21.9 periods in which interrupts are not acknowledged by cpu interrupts are acknowledged by the cpu while an instru ction is being executed. however, no interrupt is acknowledged (interrupts are held pending) between an in terrupt request non-sample instruction and the next instruction. the following instructions are interrupt request non-sample instructions. ? ei instruction ? di instruction ? ldsr reg2, 0x5 instructions (vs. psw) ? store instruction for the prcmd register ? store instruction and set1, not1, clr1 manipu lation instructions for the following registers ? interrupt-related registers: interrupt control register (xxlcn), interr upt mask registers 0 to 3 (imr0 to imr3) ? power save control register (psc) ? on-chip debug mode register (ocdm) 21.10 cautions design the system so that restoring by the reti instructi on is as follows after a non-maskable interrupt triggered by a non-maskable interrupt request signal (intwdt1/intwdt2) is serviced. figure 21-15. restoring by reti instruction generation of intwdt1/intwdt2 intwdt1/intwdt2 servicing routine software reset processing routine fepc software reset processing address fepsw value so that np bit =1, ep bit = 0 reti ten reti instructions (fepc and fepsw note must be set) psw initial set value of psw initialization processing note fepsw value to set np bit = 1, ep bit = 0 preliminary user?s manual u17702ej1v0ud 722 chapter 22 key interrupt function 22.1 function a key interrupt request signal (intkr) can be generated by inputting a falling edge to the eight key input pins (kr0 to kr7) by setting the krm register. caution if any of the kr0 to kr7 pins is at low l evel, the intkr signal is not generated even if a falling edge is input to another pin. table 22-1. assignment of key return detection pins flag pin description krm0 controls kr0 signal in 1-bit units krm1 controls kr1 signal in 1-bit units krm2 controls kr2 signal in 1-bit units krm3 controls kr3 signal in 1-bit units krm4 controls kr4 signal in 1-bit units krm5 controls kr5 signal in 1-bit units krm6 controls kr6 signal in 1-bit units krm7 controls kr7 signal in 1-bit units figure 22-1. key re turn block diagram intkr key return mode register (krm) krm7 krm6 krm5 krm4 krm3 krm2 krm1 krm0 kr7 kr6 kr5 kr4 kr3 kr2 kr1 kr0 chapter 22 key interrupt function preliminary user?s manual u17702ej1v0ud 723 22.2 register (1) key return mode register (krm) the krm register controls the krm0 to krm7 bits using the kr0 to kr7 signals. this register can be read or writt en in 8-bit or 1-bit units. reset sets this register to 00h. krm7 does not detect key return signal detects key return signal krmn 0 1 key return mode control krm krm6 krm5 krm4 krm3 krm2 krm1 krm0 after reset: 00h r/w address: fffff300h caution if the krm register is changed, an interrupt request signal (intkr) may be generated. to prevent this, change th e krm register after disabling interrupts (di), and then enable interrupts (ei) a fter clearing the interrupt request flag (kric.krif bit) to 0. remark for the alternate-function pin settings, refer to table 4-19 settings when port pins are used for alternate functions . preliminary user?s manual u17702ej1v0ud 724 chapter 23 standby function 23.1 overview the power consumption of the system can be effectively reduced by using t he standby modes in combination and selecting the appropriate mode for the application. the available standby modes are listed in table 23-1. table 23-1. standby modes mode functional outline halt mode mode to stop only the operating clock of the cpu idle mode mode to stop all the operations of the internal circuits except the oscillator note 1 stop mode mode to stop all the operations of the internal circuits except the subclock oscillator note 2 subclock operation mode mode to use the subclock as the internal system clock sub-idle mode mode to stop all the operations of the internal circuits, except the oscillator, in the subclock operation mode notes 1. the pll does not stop. to realize low power consum ption, stop the pll and then shift to the idle mode. 2. change to the clock-through mode, stop the pll, t hen shift to the stop mode. for details, refer to chapter 6 clock generation function . chapter 23 standby function preliminary user?s manual u17702ej1v0ud 725 figure 23-1. status transition (1/2) normal operation mode (operation with main clock) wait for stabilization of oscillation wait for stabilization of oscillation wait for stabilization of oscillation end of oscillation stabilization time count end of oscillation stabilization time count end of oscillation stabilization time count setting of halt mode interrupt request note 3 setting of stop mode idle mode halt mode stop mode reset note 5 interrupt request note 2 setting of idle mode interrupt request note 4 reset note 1 reset note 5 notes 1. reset by reset pin input, watchdog timer 1 overflow (wdtres1), or watchdog timer 2 overflow (wdtres2). 2. non-maskable interrupt request signal (nmi, intw dt1, intwdt2) or unmasked maskable interrupt request signal. 3. non-maskable interrupt request signal (nmi pin input, intwdt2 (when the cpu is operating on the subclock)), unmasked external interrupt request si gnal (intp0 to intp7 pin input), or unmasked internal interrupt request signal from peripheral functions operable in idle mode. 4. non-maskable interrupt request signal (nmi pin input, intwdt2 (when the cpu is operating on the subclock)), unmasked external interrupt request si gnal (intp0 to intp7 pin input), or unmasked internal interrupt request signal from peripheral functions operable in stop mode. 5. reset by reset pin input or watchdog timer 2 (when the cpu is operating on the subclock) overflow (wdtres2). chapter 23 standby function preliminary user?s manual u17702ej1v0ud 726 figure 23-1. status transition (2/2) normal operation mode (operation with main clock) subclock operation mode (operation with subclock) wait for stabilization of oscillation wait for stabilization of oscillation end of oscillation stabilization time count setting of subclock operation mode setting of normal operation mode end of oscillation stabilization time count sub-idle mode reset note 1 interrupt request note 2 setting of idle mode reset note 1 notes 1. reset by reset pin input or watchdog timer 2 overflow (wdtres2). 2. non-maskable interrupt request signal (nmi pin input, intwdt2 (when the cpu is operating on the subclock)), unmasked external interrupt request si gnal (intp0 to intp7 pin input), or unmasked internal interrupt request signal from peripheral functions operable in sub-idle mode. chapter 23 standby function preliminary user?s manual u17702ej1v0ud 727 23.2 registers (1) power save control register (psc) this is an 8-bit register that controls the standby function. the stp bit of this register is used to specify the standby mode. the psc register is a special register that can be written to only in a special sequence (refer to 3.4.7 special registers ). this register can be read or written in 8-bit or 1-bit units. after reset, psc is cleared to 00h. nmi2m psc 0 nmi0m intm 0 0 stp 0 releasing standby mode note by intwdt2 signal enabled releasing standby mode note by intwdt2 signal disabled nmi2m 0 1 control of releasing standby mode note by intwdt2 signal releasing standby mode note by nmi pin input enabled releasing standby mode note by nmi pin input disabled nmi0m 0 1 control of releasing standby mode note by nmi pin input releasing standby mode note by maskable interrupt request signals enabled releasing standby mode note by maskable interrupt request signals disabled intm 0 1 control of releasing standby mode note by maskable interrupt request signals normal mode standby mode note stp 0 1 standby mode note setting after reset: 00h r/w address: fffff1feh < > < > < > < > note in this case, standby mode means the idle/s top mode; it does not in clude the halt mode. cautions 1. if the nmi2m, nmi0m, and intm bits, and the stp bit are set to 1 at the same time, the setting of nmi2m, nmi0m, and intm bits b ecomes invalid. if th ere is an unmasked interrupt request signal being held pending when the idle/stop mode is set, set the bit corresponding to the interrupt request signal (n mi2m, nmi0m, or intm) to 1, and then set the stp bit to 1. 2. when the idle/stop mode is set, set the psmr.psm bit and then set the stp bit. chapter 23 standby function preliminary user?s manual u17702ej1v0ud 728 (2) power save mode register (psmr) this is an 8-bit register that cont rols the operation status in the st andby mode and the clock operation. this register can be read or written in 8-bit or 1-bit units. after reset, psmr is cleared to 00h. xtstp subclock oscillator used subclock oscillator not used xtstp 0 1 specification of subclock oscillator use psmr 0 0 0 0 0 0 psm idle mode stop mode psm 0 1 specification of operation in standby mode after reset: 00h r/w after reset: fffff820h < > cautions 1. be sure to clear the xtstp bi t to 0 during subclock resonator connection. 2. be sure to clear bits 1 to 6 of the psmr register to 0. 3. the psm bit is valid only when the psc.stp bit is 1. chapter 23 standby function preliminary user?s manual u17702ej1v0ud 729 (3) oscillation stabilization time selection register (osts) the wait time until the oscill ation stabilizes after the stop mode is releas ed is controlled by the osts register. the osts register can be read or written in 8-bit units. after reset, osts is set to 01h. 0 osts 0 0 0 0 osts2 osts1 osts0 2 13 /f x 2 15 /f x 2 16 /f x 2 17 /f x 2 18 /f x 2 19 /f x 2 20 /f x 2 21 /f x osts2 0 0 0 0 1 1 1 1 selection of oscillation stabilization time osts1 0 0 1 1 0 0 1 1 osts0 0 1 0 1 0 1 0 1 5 mhz 10 mhz 0.819 ms 3.277 ms 6.554 ms 13.11 ms 26.21 ms 52.43 ms 104.9 ms 209.7 ms 4 mhz 2.048 ms 8.192 ms 16.38 ms 32.77 ms 65.54 ms 131.1 ms 262.1 ms 524.3 ms 1.638 ms 6.554 ms 13.11 ms 26.21 ms 52.43 ms 104.9 ms 209.7 ms 419.4 ms f x after reset: 01h r/w address: fffff6c0h cautions 1. the wait time following release of the stop mode does not include the time until the clock oscillation starts (?a? in the figure below) following release of the stop mode, regardless of whether the stop mode is released by re set or the occurrence of an interrupt request signal. a stop mode release voltage waveform of x1 pin v ss 2. be sure to clear bits 3 to 7 to 0. 3. the oscillation stabilization ti me following reset release is 2 15 /f x (because the initial value of the osts register = 01h). 4. the oscillation stabilization time is also inserted during external clock input. remark f x : main clock oscillation frequency chapter 23 standby function preliminary user?s manual u17702ej1v0ud 730 23.3 halt mode 23.3.1 setting and operation status the halt mode is set when a dedicated instruction (halt) is executed in the normal operation mode. in the halt mode, the clock oscillator continues operating. only clock s upply to the cpu is stopped; clock supply to the other on-chip peripheral functions continues. as a result, program execution is stopped, and the inte rnal ram retains the contents before the halt mode was set. the on-chip peripheral functions that are independent of instruction processing by the cpu continue operating. table 23-3 shows the operation status in the halt mode. the average power consumption of the system can be reduc ed by using the halt mode in combination with the normal operation mode for intermittent operation. cautions 1. insert five or more nop in structions after the halt instruction. 2. if the halt instruction is executed with an unmasked interrupt request signal held pending, the system shift to the halt mode, but the ha lt mode is immediately released by the pending interrupt request signal. 23.3.2 releasing halt mode the halt mode is released by a non-maskable interrupt request signal (nmi pin input, intwdt1, intwdt2 signal), an unmasked maskable interrupt request signal, and reset signal (reset pin input, wdtres1, wdtres2 signal). after the halt mode has been released, the normal operation mode is restored. (1) releasing halt mode by non-maskable interrupt request si gnal or unmasked maskable interrupt request signal the halt mode is released by a non-maskable interr upt request signal or an unmasked maskable interrupt request signal, regardless of the prio rity of the interrupt request. if the halt mode is set in an interrupt servicing routine, however, an interrupt request that is issued later is serviced as follows. (a) if an interrupt request signal with a priority lower th an that of the interrupt r equest currently being serviced is issued, only the halt mode is released, and that interrupt request signal is not acknowledged. the interrupt request signal itself is retained. (b) if an interrupt request with a priority higher than that of the interrupt request signal currently being serviced is issued (including a non-maskable interrupt request signal), the halt mode is released and that interrupt request signal is acknowledged. table 23-2. operation after releasing halt mode by interr upt request signal release source interrupt enabled (ei) st atus interrupt disabled (di) status non-maskable interrupt request signal ex ecution branches to the handler address maskable interrupt request signal execution branches to the handler address or the next instruction is executed the next instruction is executed (2) releasing halt mode by reset the same operation as the normal reset operation is performed. chapter 23 standby function preliminary user?s manual u17702ej1v0ud 731 table 23-3. operation status in halt mode when cpu is operating with main clock setting of halt mode item when subclock is not used when subclock is used cpu stops operation main clock oscillator oscillation enabled subclock oscillator ? oscillation enabled interrupt controller operable timer p (tmp0) operable 16-bit timers (tm00 to tm05) operable 8-bit timers (tm50, tm51) operable timer h (tmh0, tmh1) operable watch timer operable when main clock output is selected as count clock operable watchdog timer 1 operable watchdog timer 2 operable when main clock is selected as count clock operable csi00 to csi02 operable csia0, csia1 operable i 2 c0, i 2 c1 operable serial interface uart0 to uart2 operable key interrupt function operable a/d converter operable d/a converter operable when real-time output mode is selected real-time output operable dma operable regulator operable port function retains status before halt mode was set. external bus interface refer to 2.2 pin status . internal data the cpu registers, statuses, data, and all other internal data such as the contents of the internal ram are retained as they were before the halt mode was set. chapter 23 standby function preliminary user?s manual u17702ej1v0ud 732 23.4 idle mode 23.4.1 setting and operation status the idle mode is set by clearing the psmr.psm bit to 0 and setting the psc.stp bit to 1 in the normal operation mode. in the idle mode, the clock oscillator continues operati on but clock supply to the cpu and other on-chip peripheral functions stops. as a result, program execution stops and the contents of the internal ram before the idle mode was set are retained. the cpu and other on-chip peripheral functions st op operating. however, the on -chip peripheral functions that can operate with the subclock or an external clock continue operating. table 23-5 shows the operation status in the idle mode. the idle mode can reduce the power consumption more than the halt m ode because it stops the operation of the on-chip peripheral functions. the main clock oscill ator does not stop, so the normal operation mode can be restored without waiting for the oscillation stabilization ti me after the idle mode has been released, in the same manner as when the halt mode is released. caution insert five or more nop instru ctions after the instruction that st ores data in the psc register to set the idle mode. chapter 23 standby function preliminary user?s manual u17702ej1v0ud 733 23.4.2 releasing idle mode the idle mode is released by a non-maskable interrupt request signal (nmi pin input, intwdt2 signal (when the cpu is operating on the subclock)), unmasked external inte rrupt request signal (intp0 to intp7 pin input), unmasked internal interrupt request signal from the peripheral function s operable in the idle mode, or reset (reset pin input, wdtres2 signal (when the cpu is operating on the subclock)). after the idle mode has been released, th e normal operation mode is restored. (1) releasing idle mode by non-maskable interrupt request si gnal or unmasked maskable interrupt request signal the idle mode is released by a non-maskable interru pt request signal or an unmasked maskable interrupt request signal, regardless of the priority of the interr upt request. if the idle mode is set in an interrupt servicing routine, however, an interrupt request that is issued later is processed as follows. (a) if an interrupt request signal with a priority lower th an that of the interrupt r equest currently being serviced is issued, only the idle mode is released, and that interrupt request signal is not acknowledged. the interrupt request signal itself is retained. (b) if an interrupt request signal with a priority higher than that of the interrupt request currently being serviced is issued (including a non-maskable interrupt request signal), the idle mode is released and that interrupt request signal is acknowledged. table 23-4. operation after releasing id le mode by interr upt request signal release source interrupt enabled (ei) st atus interrupt disabled (di) status non-maskable interrupt request signal ex ecution branches to the handler address maskable interrupt request signal execution branches to the handler address or the next instruction is executed the next instruction is executed caution the interrupt request signal that is disabled by setting the psc.nmi2m, psc.nmi0m, and psc.intm bits to 1 (interrupt disabled) become s invalid and the idle mode is not released. (2) releasing idle mode by reset the same operation as the normal reset operation is performed. chapter 23 standby function preliminary user?s manual u17702ej1v0ud 734 table 23-5. operation status in idle mode when cpu is operating with main clock setting of idle mode item when subclock is not used when subclock is used cpu stops operation main clock oscillator oscillation enabled subclock oscillator ? oscillation enabled interrupt controller stops operation timer p (tmp0) stops operation 16-bit timers (tm00 to tm05) tm00, tm02 to tm05: stop operation tm01: operable when intwt is selected as count clock and f brg is selected as count clock of wt tm00, tm02 to tm05: stop operation tm01: operable when intwt is selected as count clock 8-bit timers (tm50, tm51) ? operable when ti5m is selected as count clock ? operable when inttm010 is selected as count clock and tm01 is enabled in idle mode timer h (tmh0) stops operation timer h (tmh1) stops operation operable when f xt is selected as count clock watch timer operable when main clock is selected as count clock operable watchdog timer 1 stops operation watchdog timer 2 stops operation operable when f xt is selected as count clock csi00 to csi02 operable when sck0n input clock is selected as operation clock csia0, csia1 stops operation i 2 c0, i 2 c1 stops operation uart0 operable when asck0 is selected as count clock serial interface uart1, uart2 stops operation key interrupt function operable a/d converter stops operation note d/a converter operable however, the dacsn register cannot be updated because the cpu is stopped. regulator operation continues real-time output operable when inttm5m is selected as real-time output trigger and tm5m is enabled in idle mode. however, the rtbhm and rtblm registers cannot be updated because the cpu is stopped. dma stops operation regulator operation continues port function retains status before idle mode was set. external bus interface refer to 2.2 pin status . internal data the cpu registers, statuses, data, and all other internal data such as the contents of the internal ram are retained as they were before the idle mode was set. note by setting the adm.adcs and adm.adcs2 bits to 00 b before the idle mode is set, power consumption can be reduced. remark m = 0, 1 n = 0 to 2 chapter 23 standby function preliminary user?s manual u17702ej1v0ud 735 23.5 stop mode 23.5.1 setting and operation status the stop mode is set when the psmr.psm bit is set to 1 and the psc.stp bit is set to 1 in the normal operation mode. in the stop mode, the subclock oscillat or continues operating but the main cl ock oscillator stops. clock supply to the cpu and the on-chip peri pheral functions is stopped. as a result, program execution is st opped, and the contents of the inter nal ram before the stop mode was set are retained. the on-chip peripheral f unctions that operate with the clock oscilla ted by the subclock oscillator or an external clock continue operating. table 23-7 shows the operation status in the stop mode. because the stop stops operati on of the main clock oscillator, it reduces the power consumption to a level lower than the idle mode. if the subclock o scillator and external clock are not used, the power consumption can be minimized with only leakage current flowing. caution insert five or more nop instru ctions after the instruction that st ores data in the psc register to set the stop mode. chapter 23 standby function preliminary user?s manual u17702ej1v0ud 736 23.5.2 releasing stop mode the stop mode is released by a non-maskable interrupt request signal (nmi pin input, intwdt2 signal (when the cpu is operating on the subclock)), unmasked external inte rrupt request signal (intp0 to intp7 pin input), unmasked internal interrupt request signal from the peripheral functions operable in the stop mode, or reset (reset pin input, wdtres2 signal (when the cpu is operating on the subclock)). after the stop mode has been released, the normal operat ion mode is restored after the oscillation stabilization time has been secured. (1) releasing stop mode by non-maskable interrupt request si gnal or unmasked maskable interrupt request signal the stop mode is released by a non-maskable interrupt request signal or an unmasked maskable interrupt request signal, regardless of the prio rity of the interrupt request. if the software stop mode is set in an interrupt servicing routine, however, an interrupt r equest that is issued later is serviced as follows. (a) if an interrupt request signal with a priority lower th an that of the interrupt r equest currently being serviced is issued, only the stop mode is released, and that interrupt request signal is not acknowledged. the interrupt request signal itself is retained. (b) if an interrupt request signal with a priority higher than that of the interrupt request currently being serviced is issued (including a non-maskable interrupt request signal), the stop mode is released and that interrupt request signal is acknowledged. table 23-6. operation after releasing st op mode by interrupt request signal release source interrupt enabled (ei) st atus interrupt disabled (di) status non-maskable interrupt request signal ex ecution branches to the handler address maskable interrupt request signal execution branches to the handler address or the next instruction is executed the next instruction is executed caution the interrupt request signal that is disabled by setting the psc.nmi2m, psc.nmi0m, and psc.intm bits to 1 (interrupt disabled) become s invalid and the stop mode is not released. (2) releasing stop mode by reset the same operation as the normal reset operation is performed. chapter 23 standby function preliminary user?s manual u17702ej1v0ud 737 table 23-7. operation status in stop mode when cpu is operating with main clock setting of stop mode item when subclock is not used when subclock is used cpu stops operation main clock oscillator oscillation stops subclock oscillator ? oscillation enabled interrupt controller stops operation timer p (tmp0) stops operation 16-bit timers (tm00 to tm05) stops operation tm00, tm02 to tm05: stop operation tm01: operable when intwt is selected as count clock and f xt is selected as count clock of wt 8-bit timers (tm50, tm51) operabl e when ti5m is selected as count clock operable when ti5m is selected as count clock or when inttm010 is selected as count clock and tm01 is enabled in stop mode timer h (tmh0) stops operation timer h (tmh1) stops operation operable when f xt is selected as count clock watch timer stops operation operable when f xt is selected as count clock watchdog timer 1 stops operation watchdog timer 2 stops operation operable when f xt is selected as count clock csi00 to csi02 operable when sck0n input clock is selected as operation clock csia0, csia1 stops operation i 2 c0, i 2 c1 stops operation uart0 operable when asck0 is selected as count clock serial interface uart1, uart2 stops operation key interrupt function operable a/d converter stops operation note d/a converter operable however, the dacsn register cannot be updated because the cpu is stopped. real-time output operable when inttm5m is selected as real-time output trigger and tm5m is enabled in stop mode. however, the rtbhm and rtblm registers cannot be updated because the cpu is stopped. dma stops operation regulator stops operation port function retains status before stop mode was set. external bus interface refer to 2.2 pin status . internal data the cpu registers, statuses, data, and all other internal data such as the contents of the internal ram are retained as they were before the stop mode was set. note by setting the adm.adcs and adm.adcs2 bits to 00b before the stop mode is set, power consumption can be reduced. remark m = 0, 1 n = 0 to 2 chapter 23 standby function preliminary user?s manual u17702ej1v0ud 738 23.5.3 securing oscillation stabilization time when stop mode is released when the stop mode is released, only the oscillation stabilization time set by the osts register elapses. if the stop mode has been released by reset, however, the reset value of the osts register, 2 15 /f x (8.192 ms at f x = 4 mhz) elapses. the operation performed when the stop mode is releas ed by an interrupt request signal is shown below. figure 23-2. oscillation stabilization time oscillated waveform main clock oscillator stops oscillation stabilization time count main clock stop mode status interrupt request caution for details of the osts register, refer to 23.2 (3) oscillation stabilization time selection register (osts). chapter 23 standby function preliminary user?s manual u17702ej1v0ud 739 23.6 subclock operation mode 23.6.1 setting and operation status the subclock operation mode is set when the pcc.ck3 bit is set to 1 in the normal operation mode. when the subclock operation mode is set, t he internal system clock is changed from the main clock to the subclock. when the pcc.mck bit is set to 1, the op eration of the main clock oscillator is stopped. as a result, the system operates only with the subclock. table 23-8 shows the operation stat us in subclock operation mode. in the subclock operation mode, the power consumption can be reduced to a level lower than in the normal operation mode because the subclock is used as the internal system clock. in addition, the power consumption can be further reduced to the level of the stop mode by st opping the operation of t he main clock oscillator. cautions 1. when manipulating the ck3 bit, do no t change the set values of the pcc.ck2 to pcc.ck0 bits (using a bit manipulation instruction to ma nipulate the bit is recommended). for details, refer to 6.3 (1) processor cl ock control register (pcc). 2. if the following conditions are not satisfied, change the ck2 to ck0 bits so that the conditions are satisfied and set the subclock operation mode. internal system clock (f clk ) > subclock (f xt : 32.768 khz) 4 remark internal system clock (f clk ): clock generated from the main clock (f xx ) by setting bits ck2 to ck0 23.6.2 releasing subclock operation mode the subclock operation mode is released when the ck3 bit is cleared to 0 or by reset (reset pin input, wdtres1, wdtres2 signal). if the main clock is stopped (mc k bit = 1), set the mck bit to 1, secure the oscillation stabilization time of the main clock by software, and clear the ck3 bit to 0. the normal operation mode is restored when the subclock operation mode is released. caution when manipulating the ck3 bit, do not change the set values of the ck2 to ck0 bits (using a bit manipulation instruction to manipulate the bit is recommended). for deta ils, refer to 6.3 (1) processor clock control register (pcc). chapter 23 standby function preliminary user?s manual u17702ej1v0ud 740 table 23-8. operation status in subclock operation mode operation status setting of subclock operation item mode when main clock is oscillati ng when main clock is stopped cpu operable subclock oscillator oscillation enabled interrupt controller operable timer p (tmp0) operable stops operation 16-bit timers (tm00 to tm05) operable tm00, tm02 to tm05: stop operation tm01: operable when intwt is selected as count clock and f xt is selected as count clock of wt 8-bit timers (tm50, tm51) operable ? operable when ti5m is selected as count clock ? operable when inttm010 is selected as count clock and when tm01 is enabled in subclock operation mode timer h (tmh0) operable stops operation timer h (tmh1) operable operable when f xt is selected as count clock watch timer operable operable when f xt is selected as count clock watchdog timer 1 stops operation watchdog timer 2 operable operable when f xt is selected as count clock csi00 to csi02 operable operable when sck0n input clock is selected as operation clock csia0, csia1 operable stops operation i 2 c0, i 2 c1 operable stops operation uart0 operable operable when asck0 is selected as count clock serial interface uart1, uart2 operable stops operation key interrupt function operable a/d converter operable stops operation d/a converter operable real-time output operable operable when inttm5m is selected as real-time output trigger and ti5m is selected as count clock of tm5m dma operable regulator operation continues port function settable external bus interface operable internal data settable remark m = 0, 1 n = 0 to 2 chapter 23 standby function preliminary user?s manual u17702ej1v0ud 741 23.7 sub-idle mode 23.7.1 setting and operation status the sub-idle mode is set when the psmr.psm bit is cleared to 0 and the psc.stp bit is set to 1 in the subclock operation mode. in this mode, the clock oscillator continues operation bu t clock supply to the cpu and the other on-chip peripheral functions is stopped. as a result, program execution is st opped and the contents of the internal ram before the sub-idle mode was set are retained. the cpu and t he other on-chip peripheral functions are st opped. however, the on-chip peripheral functions that can operate with the subclock or an extern al clock continue operating. table 23-10 shows the operation status in the sub-idle mode. because the sub-idle mode stops oper ation of the cpu and other on-chip per ipheral functions, it can reduce the power consumption more than the subc lock operation mode. if the sub-idle mode is set after the main clock has been stopped, the power consumption can be reduced to a level as lo w as that in the stop mode. caution following the store instructi on to set the psc register to the sub-idle mode, insert five or more nop instructions. chapter 23 standby function preliminary user?s manual u17702ej1v0ud 742 23.7.2 releasing sub-idle mode the sub-idle mode is released by a non-maskable interrupt request signal (nmi pin input, intwdt2 signal (when the cpu is operating on the subclock)), unmasked external interrupt request signal (intp0 to intp7 pin input), unmasked internal interrupt request signal from the peri pheral functions operable in the sub-idle mode, or reset (reset pin input, wdtres2 signal (when t he cpu is operating on the subclock)). when the sub-idle mode is released by an interrupt requ est signal, the subclock operation mode is set. if it is released by reset, the normal operation mode is restored. (1) releasing sub-idle m ode by non-maskable interrupt request signal or unmasked maskable interrupt request signal the sub-idle mode is released by a non-maskable interrupt request signal or an unmasked maskable interrupt request signal, regardless of the priority of t he interrupt request. if the sub-idle mode is set in an interrupt servicing routine, however, an interrupt request signal that is issued later is serviced as follows. (a) if an interrupt request signal with a priority lower th an that of the interrupt r equest currently being serviced is issued, only the sub-idle mode is released, and that interrupt request signal is not acknowledged. the interrupt request signal itself is retained. (b) if an interrupt request signal with a priority higher than that of the interrupt request currently being serviced is issued (including a non-maskable interrupt request signal), the sub-idle mode is released and that interrupt request signal is acknowledged. table 23-9. operation after releasing sub- idle mode by interrupt request signal release source interrupt enabled (ei) st atus interrupt disabled (di) status non-maskable interrupt request signal ex ecution branches to the handler address maskable interrupt request signal execution branches to the handler address or the next instruction is executed the next instruction is executed caution the interrupt request signal that is disabled by setting the psc.nmi2m, psc.nmi0m, and psc.intm bits to 1 (interrupt disabled) beco mes invalid and the sub-idle mode is not released. (2) releasing sub-id le mode by reset the same operation as the normal reset operation is performed. chapter 23 standby function preliminary user?s manual u17702ej1v0ud 743 table 23-10. operation status in sub-idle mode operation status setting of sub-idle item mode when main clock is oscillati ng when main clock is stopped cpu stops operation subclock oscillator oscillation enabled interrupt controller stops operation timer p (tmp0) stops operation 16-bit timers (tm00 to tm05) tm00, tm02 to tm05: stop operation tm01: operable when intwt is selected as count clock tm00, tm02 to tm05: stop operation tm01: operable when intwt is selected as count clock and f xt is selected as count clock of wt 8-bit timers (tm50, tm51) ? operable when ti5m is selected as count clock ? operable when inttm010 is selected as count clock and when tm01 is enabled in sub-idle mode timer h (tmh0) stops operation timer h (tmh1) operable when f xt is selected as count clock watch timer operable operable when f xt is selected as count clock watchdog timer 1 stops operation watchdog timer 2 operable when f xt is selected as count clock csi00 to csi02 operable when sck0n input clock is selected as operation clock csia0, csia1 stops operation i 2 c0, i 2 c1 stops operation uart0 operable when asck0 is selected as count clock serial interface uart1, uart2 stops operation key interrupt function operable a/d converter stops operation note d/a converter operable however, the dacsn register cannot be updated because the cpu is stopped. real-time output operable when inttm5m is selected as real-time output trigger and tm5m is set to the operable conditions of the sub-idle mode dma stops operation regulator stops operation port function retains status before sub-idle mode was set. external bus interface refer to 2.2 pin status . internal data the cpu registers, statuses, data, and all other internal data such as the contents of the internal ram are retained as they were before the sub-idle mode was set. note by setting the adm.adcs and adm.adcs2 bits to 00b be fore the sub-idle mode is set, power consumption can be reduced. remark m = 0, 1 n = 0 to 2 preliminary user?s manual u17702ej1v0ud 744 chapter 24 reset function 24.1 overview the following reset functions are available. ? reset function by reset pin input ? reset function by overflow of watchdog timer 1 (wdtres1) ? reset function by overflow of watchdog timer 2 (wdtres2) if the reset pin goes high, the reset stat us is released, and the cpu starts ex ecuting the program. initialize the contents of each register in the program as necessary. the reset pin has a noise e liminator that operat es by analog delay to prevent malfunction caused by noise. 24.2 configuration figure 24-1. reset block diagram reset count clock count clock analog delay circuit reset controller watchdog timer 1 watchdog timer 2 wdtres1 issued due to overflow reset signal to cpu reset signal to cg reset signal to other peripheral macros wdtres2 issued due to overflow chapter 24 reset function preliminary user?s manual u17702ej1v0ud 745 24.3 operation the system is reset, initializing each hardware unit, when a lo w level is input to the reset pin or if watchdog timer 1 or watchdog timer 2 overflows (wdtres1 or wdtres2). while a low level is being input to the reset pin, the ma in clock oscillator stops. t herefore, the overall power consumption of the system can be reduced. if the reset pin goes high or if the wdtres1 or wdtres2 signal is received, the reset status is released. if the reset status is released by reset pin input or the wdtres2 signal, the oscillation stabilization time elapses (reset value of osts register: 2 15 /f xx ) and then the cpu starts program execution. if the reset status is released by the wdtres1 signal, t he oscillation stabilization ti me is not inserted because the main system clock oscill ator does not stop. chapter 24 reset function preliminary user?s manual u17702ej1v0ud 746 table 24-1. hardware status on reset pi n input or occurrence of wdtres2 signal item during reset after reset main clock oscillator (f x ) oscillation stops oscillation starts subclock oscillator (f xt ) oscillation continues peripheral clock (f xx to f xx /1024) operation stops operation starts after securing oscillation stabilization time internal system clock (f clk ) operation stops operation starts after securing oscillation stabilization time (initialized to f xx /8) cpu clock (f cpu ) operation stops operation starts after securing oscillation stabilization time (initialized to f xx /8) watchdog timer 1 clock (f xw ) operation stops operation starts cpu initialized program execution starts after securing oscillation stabilization time internal ram undefined if power-on reset or writing data to ram (by cpu or dma) and reset input conflict (data is damaged). otherwise value imm ediately before reset input is retained. i/o lines high impedance on-chip peripheral i/o registers initialized to specified status watchdog timer 2 operation stops operation starts after securing oscillation stabilization time other on-chip peripheral fu nctions operation stops operation can be started after securing oscillation stabilization time table 24-2. hardware status on occurrence of wdtres1 signal item during reset after reset main clock oscillator (f x ) oscillation continues subclock oscillator (f xt ) oscillation continues peripheral clock (f xx to f xx /1024) operation stops operation starts internal system clock (f clk ) oscillation continues (initialized to f xx /8) cpu clock (f cpu ) oscillation continues (initialized to f xx /8) watchdog timer 1 clock (f xw ) operation continues internal ram undefined if writing data to ram (by cpu or dma) and reset input conflict (data is damaged). otherwise value imm ediately before reset input is retained. i/o lines high impedance on-chip peripheral i/o registers initialized to specified status watchdog timer 2 operation stops operation starts other on-chip peripheral fu nctions operation stops o peration can be started chapter 24 reset function preliminary user?s manual u17702ej1v0ud 747 figure 24-2. hardware status on reset input figure 24-3. operation on power application oscillation stabilization time count initialized to f xx /8 operation overflow of timer for oscillation stabilization internal system reset signal analog delay reset f x v dd f clk oscillation stabilization time count initialized to f xx /8 operation overflow of timer for oscillation stabilization internal system reset signal analog delay (eliminated as noise) analog delay analog delay (eliminated as noise) reset f x f clk analog delay chapter 24 reset function preliminary user?s manual u17702ej1v0ud 748 figure 24-4. timing of reset operation by watchdog timer 1 initialized to f xx /8 operation f clk : 12-clock width internal system reset signal (active low) wdtres1 signal (active low) f x f clk figure 24-5. timing of reset operation by watchdog timer 2 oscillation stabilization time count initialized to f xx /8 operation overflow of oscillation stabilization time counter internal system reset signal (active low) wdtres2 signal (active low) f x f clk analog delay preliminary user?s manual u17702ej1v0ud 749 chapter 25 regulator 25.1 overview the v850es/kj2 includes a regulator to re duce the power consumption and noise. this regulator supplies a stepped-down v dd power supply voltage to the oscillator block and internal logic circuits (except the a/d converter, d/a converte r, and output buffer). the regulator out put voltage is set to 3.6 v (typ.). caution when using the regulator (regc = 10 f, the external clock cannot be input to the main clock oscillator or subclock oscillator. figure 25-1. regulator ev dd i/o buffer (normal port) 2.7 to 5.5 v bidirectional level shifter bv dd i/o buffer 2.7 to 5.5 v regulator a/d converter 2.7 to 5.5 v d/a converter 2.7 to 5.5 v bv dd av ref0 av ref1 v pp v dd ev dd regc flash memory main/sub oscillator internal digital circuits 3.6 v (typ.) caution use the regulator with a setting of v dd = ev dd = av ref0 = av ref1 bv dd . 25.2 operation the regulator stops operat ing in the following modes and the supply voltage to the oscillator is v dd (but only when regc = 10 f). ? during reset ? in stop mode ? in sub-idle mode when using the regulator, be sure to connect a capacitor (10 f) to the regc pin to stabilize the regulator output. a diagram of the regulator pin connections is shown below. chapter 25 regulator preliminary user?s manual u17702ej1v0ud 750 figure 25-2. regc pin connection (a) when regc = v dd reg input voltage = 2.7 to 5.5 v voltage supply to oscillator/internal logic = 2.7 to 5.5 v v dd regc (b) when connecting regc pin to v ss via a capacitor reg input voltage = 4.0 to 5.5 v voltage supply to oscillator/internal logic = 3.6 v v dd regc 10 f preliminary user?s manual u17702ej1v0ud 751 chapter 26 flash memory caution for the electrical specifications related to the flash memory rewriting, refer to chapter 28 electrical specifications (target). flash memory versions are commonly used in the following development environments and mass production applications. { for altering software after the v850es/ kj2 is soldered onto the target system. { for data adjustment when starting mass production. { for differentiating software according to the specif ication in small scale production of various models. { for facilitating inventory management. { for updating software after shipment. 26.1 features { 4-byte/1-clock access (when instruction is fetched) { capacity: 256/128 kb { write voltage: erase/write with a single power supply { rewriting method ? rewriting by communication with dedicated flash programmer via serial interface (on-board/off-board programming) ? rewriting flash memory by user program (self programming) { flash memory write prohibit f unction supported (security function) { safe rewriting of entire flash memory area by self programming using boot swap function { interrupts can be acknowledged during self programming. chapter 26 flash memory preliminary user?s manual u17702ej1v0ud 752 26.2 memory configuration the 256/128 kb internal flash memory area is divided in to 128/64 blocks and can be programmed/erased in block units. all the blocks can also be erased at once. when the boot swap function is used, the physical memory (blocks 0 to 3) located at the addresses of boot area 0 is replaced by the physical memory (blocks 4 to 7) locate d at the addresses of boot area 1. for details of the boot swap function, refer to 26.5 rewriting by self programming . figure 26-1. flash memory mapping block 0 (2 kb) block 1 (2 kb) block 2 (2 kb) block 3 (2 kb) block 5 (2 kb) block 6 (2 kb) block 7 (2 kb) block 8 (2 kb) block 4 (2 kb) block 63 (2 kb) block 125 (2 kb) block 127 (2 kb) block 126 (2 kb) block 0 (2 kb) block 1 (2 kb) block 2 (2 kb) block 3 (2 kb) block 5 (2 kb) block 6 (2 kb) block 7 (2 kb) block 8 (2 kb) block 4 (2 kb) block 63 (2 kb) 00007ffh 0000800h 0000fffh 0001000h 00027ffh 0002800h 0002fffh 0003000h 00037ffh 0003800h 0003fffh 0004000h 00047ffh 0004800h 001ffffh 0020000h 001f7ffh 001f800h 003ffffh 003f800h 003f7ffh 003f000h 003efffh 003e800h 003e7ffh 00017ffh 0001800h 0001fffh 0002000h 0000000h 3ffffffh 3ff0000h 3feffffh 3fec000h 3febfffh 1000000h 0ffffffh 0100000h 00fffffh 0200000h 01fffffh 0000000h use prohibited external memory area (14 mb) external memory area (1 mb) internal flash memory area (256/128 kb) use prohibited boot area 0 note (8 kb) internal ram area (60 kb) on-chip peripheral i/o area (4 kb) boot area 1 note (8 kb) note boot area 0 (blocks 0 to 3): boot area boot area 1 (blocks 4 to 7): area used to replace boot area via boot swap function chapter 26 flash memory preliminary user?s manual u17702ej1v0ud 753 26.3 functional outline the internal flash memory of the v850es/kj2 can be rewrit ten by using the rewrite f unction of the dedicated flash programmer, regardless of whether the v850es/kj2 has already been mounted on the target system or not (on- board/off-board programming). in addition, a security function that prohi bits rewriting the user program written to the internal flash memory is also supported, so that the program c annot be changed by an unauthorized person. the rewrite function using the user program (self programmi ng) is ideal for an application where it is assumed that the program is changed after production/sh ipment of the target syst em. a boot swap function t hat rewrites the entire flash memory area safely is also supported. in addition, interrupt servicing is supported during self programming, so that the flash memory can be rewritten und er various conditions, such as while communicating with an external device. table 26-1. rewrite method rewrite method functional outline operation mode on-board programming flash memory can be rewritten after the device is mounted on the target system, by using a dedicated flash programmer. off-board programming flash memory can be rewritten before the device is mounted on the target system, by using a dedicated flash programmer and a dedicated program adapter board (fa series). flash memory programming mode self programming flash memory can be rewritten by executing a user program that has been written to the flash memory in advance by means of on-board/off- board programming. (during self-programming, instructions cannot be fetched from or data access cannot be made to the internal flash memory area. therefore, the rewrite program must be transferred to the internal ram or external memory in advance). normal operation mode remark the fa series is a product of na ito densei machida mfg. co., ltd. chapter 26 flash memory preliminary user?s manual u17702ej1v0ud 754 table 26-2. basic functions support ( { : supported, : not supported) function functional outline on-board/off-board programming self programming block erasure the contents of specified memory blocks are erased. { { chip erasure the contents of the entire memory area are erased all at once. { write writing to specified addresses, and a verify check to see if write level is secured are performed. { { verify/checksum data read from the flash memory is compared with data transferred from the flash programmer. { (can be read by user program) blank check the erasure status of the entire memory is checked. { { security setting use of the block erase command, chip erase command, and program command can be prohibited. { (supported only when setting is changed from enable to disable) the following table lists the security functions. the bl ock erase command prohibit, chip erase command prohibit, and program command prohibit functions are enabled by default after shipment, and security can be set by rewriting via on-board/off-board programming. each security function can be used in combination with the others at the same time. table 26-3. security functions rewriting operation when prohibited ( { : executable, : not executable) function function outline on-board/off-board programming self programming block erase command prohibit execution of a block erase command on all blocks is prohibited. setting of prohibition can be initialized by execution of a chip erase command. block erase command: chip erase command: { program command: { chip erase command prohibit execution of block erase and chip erase commands on all the blocks is prohibited. once prohibition is set, setting of prohibition cannot be initialized because the chip erase command cannot be executed. block erase command: chip erase command: program command: { program command prohibit write and block erase commands on all the blocks are prohibited. setting of prohibition can be initialized by execution of the chip erase command. block erase command: chip erase command: { program command: can always be rewritten regardless of setting of prohibition chapter 26 flash memory preliminary user?s manual u17702ej1v0ud 755 26.4 rewriting by dedicated flash programmer the flash memory can be rewritten by using a dedicat ed flash programmer after the v850es/kj2 is mounted on the target system (on-board pr ogramming). the flash memory can also be re written before the device is mounted on the target system (off-board progr amming) by using a dedicated program adapter (fa series). 26.4.1 programming environment the following shows the environment required for writi ng programs to the flash memory of the v850es/kj2. figure 26-2. environment required fo r writing programs to flash memory host machine rs-232c dedicated flash programmer v850es/kj2 flmd1 v dd v ss reset uart0/csi00 pg-fp4 (flash pro4) cxxxxxx bxxxxx axxxx xxx yyy x x x x x x x x x x x x x x x xxxx yyyy s tat v e flmd0 usb a host machine is required for controlling the dedicated flash programmer. uart0 or csi00 is used for the in terface between the dedicated flas h programmer and the v850es/kj2 to perform writing, erasing, etc. a dedicated program adapter (fa series) is required for off-board writing. remark the fa series is a product of na ito densei machida mfg. co., ltd. chapter 26 flash memory preliminary user?s manual u17702ej1v0ud 756 26.4.2 communication mode communication between the dedicated flash progra mmer and the v850es/kj2 is performed by serial communication using the uart0 or csi 00 interfaces of the v850es/kj2. (1) uart0 transfer rate: 9,600 to 153,600 bps figure 26-3. communication with dedicated flash programmer (uart0) dedicated flash programmer v850es/kj2 v dd v ss reset txd0 rxd0 flmd1 flmd1 flmd0 flmd0 v dd gnd reset rxd txd x1 x2 clk pg-fp4 (flash pro4) cxxxxxx bxxxxx axxxx xxx yyy x x x x x x x x x x x x x x x xxxx yyyy statve (2) csi00 serial clock: 2.4 khz to 2.5 mhz (msb first) figure 26-4. communication with de dicated flash programmer (csi00) dedicated flash programmer v850es/kj2 flmd1 v dd v ss reset so00 si00 sck00 flmd1 flmd0 flmd0 v dd gnd reset si so sck pg-fp4 (flash pro4) cxxxxxx bxxxxx axxxx x xx y yy x x x x x x x x x x x x x x x xxxx y yyy statve x1 x2 clk chapter 26 flash memory preliminary user?s manual u17702ej1v0ud 757 (3) csi00 + hs serial clock: 2.4 khz to 2.5 mhz (msb first) figure 26-5. communication with dedi cated flash programmer (csi00 + hs) dedicated flash programmer v850es/kj2 v dd v ss reset so00 si00 sck00 pcm0 v dd flmd1 flmd1 flmd0 flmd0 gnd reset si so sck hs pg-fp4 (flash p ro4) cxxxxxx bxxxxx axxxx x x x y y y x x x x x x x x x x x x x x x x x x x y y y y statve x1 x2 clk the dedicated flash programmer outputs the transfer clock, and the v850es/kj2 operates as a slave. when the pg-fp4 is used as the d edicated flash programmer, it gener ates the following signals to the v850es/kj2. for details, refer to the pg-fp4 user?s manual (u15260e) . table 26-4. signal connections of dedicated flash programmer (pg-fp4) pg-fp4 v850es/kj2 pr ocessing for connection signal name i/o pin function pin name uart0 csi00 csi00 + hs flmd0 output write enable/disable flmd0 flmd1 output write enable/disable flmd1 note 1 note 1 note 1 vdd ? v dd voltage generation/voltage monitor v dd gnd ? ground v ss clk output clock output to v850es/kj2 x1, x2 note 2 note 2 note 2 reset output reset signal reset si/rxd input receive signal so00 so/txd output transmit signal si00 sck output transfer clock sck00 hs input handshake signal for csi00 + hs communication pcm0 notes 1. wire the pin as shown in figure 26-6, or connect it to gnd on board via a pull-down resistor. 2. connect these pins to supply a clock from the pg -fp4 (wire as shown in figure 26-6, or create an oscillator on board and supply the clock). remark : must be connected. : does not have to be connected. chapter 26 flash memory preliminary user?s manual u17702ej1v0ud 758 table 26-5. wiring between v850es/kj2 and pg-fp4 pin configuration of flash programmer (pg-fp 4) with csi00-hs with csi00 with uart0 signal name i/o pin function pin name on fa board pin name pin no. pin name pin no. pin name pin no. si/r x d input receive signal si p41/ so00 23 p41/so00 23 p30/txd0 25 so/t x d output transmit signal so p40/si00 22 p40/si00 22 p31/rxd0 26 sck output transfer clock sck p42/sck00 24 p42/sck00 24 not needed not needed x1 x1 12 x1 12 x1 12 clk output clock to v850es/kj2 x2 x2 note 13 x2 note 13 x2 note 13 /reset output reset signal /r eset reset 14 reset 14 reset 14 flmd0 input write voltage flmd0 flmd0 8 flmd0 8 flmd0 8 flmd1 input write voltage flmd1 pdl5/ad5/ flmd1 110 pdl5/ad5/ flmd1 110 pdl5/ad5/ flmd1 110 hs input handshake signal for csi00 + hs communication reserve /hs pcm0/ wait 85 not needed not needed not needed not needed v dd 9 v dd 9 v dd 9 bv dd 104 bv dd 104 bv dd 104 ev dd 34 ev dd 34 ev dd 34 av ref0 1 av ref0 1 av ref0 1 vdd ? v dd voltage generation/voltage monitor vdd av ref1 5 av ref1 5 av ref1 5 v ss 11 v ss 11 v ss 11 av ss 2 av ss 2 av ss 2 bv ss 103 bv ss 69 bv ss 69 gnd ? ground gnd ev ss 33 ev ss 33 ev ss 33 note when using the clock out of the flash programmer, c onnect clk of the programmer to x1, and connect its inverse signal to x2. cautions 1. be sure to connect the regc pin in either of the following ways. ? connect to gnd via a 10 f capacitor ? directly connect to v dd 2. when connecting the regc pin to gnd via a 10 f capacitor, the clock cannot be supplied from the clk pin of the flash programmer. supply the clock by creating an oscillator on the board. chapter 26 flash memory preliminary user?s manual u17702ej1v0ud 759 figure 26-6. wiring example of v850es/kj2 flash writing adapter (fa-144gj-uen-a) (1/2) pd70f3733, pd70f3734 vdd gnd gnd vdd gnd vdd vdd gnd connect to vdd. connect to gnd. 23 24 25 26 22 11 12 13 14 33 2 104 103 85 34 j1 vdd2 vdd 1 110 note 1 5 89 so sck si /reset v pp reserve/hs clkout so sck si x1 x2 /reset clkin vpp reserve/hs rfu-3 rfu-2 rfu-1 flmd1 flmd0 vde 10 note 2 note 4 note 3 chapter 26 flash memory preliminary user?s manual u17702ej1v0ud 760 figure 26-6. wiring example of v850es/kj2 flash writing adapter (fa-144gj-uen-a) (2/2) notes 1. wire the flmd1 pin as shown in the figure, or c onnect it to gnd on board via a pull-down resistor. 2. be sure to connect the regc pin in either of the following ways. ? connect to gnd via a 10 f capacitor. ? directly connect to v dd . when connecting the regc pin to gnd via a 10 f capacitor, the clock cannot be supplied from the clk pin of the flash programmer. supply the clock by creating an oscillator on the board. 3. the above figure shows an example of wiring when the clock is supplied from the pg-fp4. be sure to set and connect as follows when the clock is supplied from the pg-fp4. ? set j1 of the flash adapter (fa) to the vdd side. ? connect clkout of fa to clkin of fa. ? connect x1 of fa to x1 of the device. ? connect x2 of fa to x2 of the device. if an oscillator is created on the flash adapter and a clock is supplied, the above setting and connections will not necessary. the following shows a circuit example. x1 x2 4. corresponding pin when using uart0 remarks 1. handle the pins not described above in accord ance with the specified handling of unused pins (refer to 2.3 pin i/o circuits and recomme nded connection of unused pins). when connecting to v dd via a resistor, use of a resistor of 1 k ? to 10 k ? is recommended. 2. this adapter is for a 144-pin plastic lqfp (fine pitch) package. 3. this diagram shows the wiring when using a handshake-supporting csi. chapter 26 flash memory preliminary user?s manual u17702ej1v0ud 761 26.4.3 flash memory control the following shows the procedure for manipulating the flash memory. figure 26-7. procedure for manipulating flash memory start select communication system manipulate flash memory end? yes supplies flmd0 pulse no end switch to flash memory programming mode chapter 26 flash memory preliminary user?s manual u17702ej1v0ud 762 26.4.4 selection of communication mode in the v850es/kj2, the communication mode is selected by inputting pulses (12 pulses max.) to the flmd0 pin after switching to the flash memory programming mode. the flmd0 pulse is generated by the dedicated flash programmer. the following shows the relationship between the number of pulses and the communication mode. figure 26-8. selection of communication mode v dd v dd reset (input) flmd1 (input) flmd0 (input) rxd0 (input) txd0 (output) v ss v dd v ss v dd v ss v dd v ss v dd v ss v dd v ss (note) power on oscillation stabilized communication mode selected flash control command communication (erasure, write, etc.) reset released note the number of clocks is as follows depending on the communication mode. flmd0 pulse communication mode remarks 0 uart0 communication rate: 9600 bps (after reset), lsb first 8 csi00 v850es/kj2 performs slave operation, msb first 11 csi00 + hs v850es/kj2 performs slave operation, msb first other rfu setting prohibited caution when uart0 is selected, the receive clock is calculate d based on the reset command sent from the dedicated flash programme r after receiving the flmd0 pulse. chapter 26 flash memory preliminary user?s manual u17702ej1v0ud 763 26.4.5 communication commands the v850es/kj2 communicates with the dedicated flash programmer by means of commands. the signals sent from the dedicated flash programmer to the v850es/kj2 are ca lled ?commands?. the respon se signals sent from the v850es/kj2 to the dedicated flash prog rammer are called ?response commands?. figure 26-9. communication commands dedicated flash programmer v850es/kj2 command response command pg-fp4 (flash pro4) cxxxxxx bxxxxx axxxx xxx yyy x x x x x x x x x x x x x x x xxxx yyyy statve the following shows the commands for flash memory cont rol in the v850es/kj2. all of these commands are issued from the dedicated flash programmer, and the v8 50es/kj2 performs the processing corresponding to the commands. table 26-6. flash memory control commands support classification command name csi00 csi00 + hs uart0 function blank check block blank check command { { { checks if the contents of the memory in the specified block have been correctly erased. chip erase command { { { erases the contents of the entire memory. erase block erase command { { { erases the contents of the memory of the specified block. write write command { { { writes the specified address range, and executes a contents verify check. verify command { { { compares the contents of memory in the specified address range with data transferred from the flash programmer. verify checksum command { { { reads the checksum in the specified address range. silicon signature command { { { reads silicon signature information. system setting, control security setting command { { { disables the chip erase command, enables the block erase command, and disables the write command. chapter 26 flash memory preliminary user?s manual u17702ej1v0ud 764 26.4.6 pin connection when performing on-board writing, mount a connector on t he target system to conne ct to the dedicated flash programmer. also, incorporate a function on-board to s witch from the normal operation mode to the flash memory programming mode. in the flash memory programming mode, all the pins not used for flash memory programming become the same status as that immediately after rese t. therefore, pin handling is required when the external device does not acknowledge the status immediately after a reset. (1) flmd0 pin in the normal operation mode, input a voltage of v ss level to the flmd0 pin. in the flash memory programming mode, supply a write voltage of v dd level to the flmd0 pin. because the flmd0 pin serves as a write protection pin in the self programming mode, a voltage of v dd level must be supplied to the flmd0 pin via port control, etc., before writing to the flash memory. for details, refer to 26.5.5 (1) flmd0 pin . figure 26-10. flmd0 pin connection example v850es/kj2 flmd0 dedicated flash programmer connection pin pull-down resistor (r flmd0 ) chapter 26 flash memory preliminary user?s manual u17702ej1v0ud 765 (2) flmd1 pin when 0 v is input to the flmd0 pin, t he flmd1 pin does not function. when v dd is supplied to the flmd0 pin, the flash memory programming mode is entered, so 0 v must be input to the flmd1 pin. the following shows an example of the connection of the flmd1 pin. figure 26-11. flmd1 pin connection example flmd1 pull-down resistor (r flmd1 ) other device v850es/kj2 caution if the v dd signal is input to the flmd1 pin from another device during on-board writing and immediately after reset, isolate this signal. table 26-7. relationship between flmd0 and flmd1 pi ns and operation mode wh en reset is released flmd0 flmd1 operation mode 0 don?t care normal operation mode v dd 0 flash memory programming mode v dd v dd setting prohibited chapter 26 flash memory preliminary user?s manual u17702ej1v0ud 766 (3) serial interface pin the following shows the pins used by each serial interface. table 26-8. pins used by serial interfaces serial interface pins used uart0 txd0, rxd0 csi00 so00, si00, sck00 csi00 + hs so00, si00, sck00, pcm0 when connecting a dedicated flash programmer to a serial interface pin that is connected to another device on-board, care should be taken to avoid conflict of signals and malfunction of the other device. (a) conflict of signals when the dedicated flash programmer (output) is connec ted to a serial interface pin (input) that is connected to another device (output), a conflict of signals occurs. to avoid the conflict of signals, isolate the connection to the other device or set the other device to the output high-impedance status. figure 26-12. conflict of signals (serial interface input pin) v850es/kj2 input pin conflict of signals dedicated flash programmer connection pins other device output pin in the flash memory programming mode, the signal that the dedicated flash programmer sends out conflicts with signals another device outputs. therefore, isolate the signals on the other device side. chapter 26 flash memory preliminary user?s manual u17702ej1v0ud 767 (b) malfunction of other device when the dedicated flash programmer (output or input) is connected to a serial interface pin (input or output) that is connected to another device (input), the signal is output to the other device, causing the device to malfunction. to avoid this, isolate the connection to the other device. figure 26-13. malfunction of other device v850es/kj2 pin dedicated flash programmer connection pin other device input pin in the flash memory programming mode, if the signal the v850es/kj2 outputs affects the other device, isolate the signal on the other device side. v850es/kj2 pin dedicated flash programmer connection pin other device input pin in the flash memory programming mode, if the signal the dedicated flash programmer outputs affects the other device, isolate the signal on the other device side. chapter 26 flash memory preliminary user?s manual u17702ej1v0ud 768 (4) reset pin when the reset signals of the dedicated flash programmer are connected to the reset pin that is connected to the reset signal generator on-board, a conflict of signal s occurs. to avoid the conflict of signals, isolate the connection to the reset signal generator. when a reset signal is input from the user system in the flash memory programming mode, the programming operation will not be performed correctly. therefore, do not input signals other than the reset signals from the dedicated flash programmer. figure 26-14. conflict of signals (reset pin) v850es/kj2 reset dedicated flash programmer connection pin reset signal generator conflict of signals output pin in the flash memory programming mode, the signal the reset signal generator outputs conflicts with the signal the dedicated flash programmer outputs. therefore, isolate the signals on the reset signal generator side. (5) port pins (including nmi) when the system shifts to the flash memory programmi ng mode, all the pins that are not used for flash memory programming are in the same st atus as that immediately after rese t. if the external device connected to each port does not recognize the st atus of the port immediately after reset, pins require appropriate processing, such as connecting to v dd via a resistor or connecting to v ss via a resistor. (6) other signal pins connect x1, x2, xt1, xt2, and regc in the same status as that in t he normal operation mode. (7) power supply supply the same power (v dd , v ss , ev dd , ev ss , av ss , bv dd , bv ss , av ref0 , av ref1 ) as in normal operation mode. chapter 26 flash memory preliminary user?s manual u17702ej1v0ud 769 26.5 rewriting by self programming 26.5.1 overview the v850es/kj2 supports a flash macro serv ice that allows the user program to rewrite the internal flash memory by itself. by using this interface and a self programming library that is used to rewrit e the flash memory with a user application program, the flash memory can be rewritten by a user application transferred in advance to the internal ram or external memory. consequently, the user program c an be upgraded and constant data can be rewritten in the field. figure 26-15. concept of self programming application program self programming library flash macro service flash memory flash function execution flash information erase, write chapter 26 flash memory preliminary user?s manual u17702ej1v0ud 770 26.5.2 features (1) secure self programming (boot swap function) the v850es/kj2 supports a boot swap function that can exchange the physica l memory (blocks 0 to 3) of boot area 0 with the physical memory (blocks 4 to 7) of boot area 1. by writing the start program to be rewritten to boot area 1 in advance and then swapping the physical me mory, the entire area can be safely rewritten even if a power failure occurs during rewriting because the co rrect user program always exists in boot area 0. figure 26-16. rewriting entire memory area (boot swap) block n block 8 block 7 block 6 block 5 block 4 block 3 block 2 block 1 block 0 block n block n boot swap rewriting boot areas 0 and 1 block 8 block 7 block 6 block 5 block 4 block 3 block 2 block 1 block 0 block 8 block 7 block 6 block 5 block 4 block 3 block 2 block 1 block 0 remark 256 kb products: n = 127 128 kb products: n = 63 (2) interrupt support instructions cannot be fetched from the flash memory during self programming. c onventionally, therefore, a user handler written to the flash me mory could not be used even if an inte rrupt occurred. therefore, in the v850es/kj2, to use an interrupt dur ing self programming, processing tr ansits to the specific address note in the internal ram. allocate the jump instru ction that transits processi ng to the user interrupt se rvicing at the specific address note in the internal ram. note nmi interrupt: start address of internal ram maskable interrupt: start address of internal ram + 4 addresses chapter 26 flash memory preliminary user?s manual u17702ej1v0ud 771 26.5.3 standard self programming flow the entire processing to rewrite the flash memory by flash self programming is illustrated below. figure 26-17. standard self programming flow (a) rewriting at once (b) rewriting in block units flash environment initialization processing erase processing write processing flash information setting processing note 1 internal verify processing boot area swapping processing note 2 flash environment end processing flash memory manipulation end of processing flash environment initialization processing erase processing write processing flash information setting processing note 1 internal verify processing boot area swapping processing note 2 flash environment end processing flash memory manipulation end of processing all blocks end? yes no ? disable accessing flash area ? disable setting of stop mode ? disable stopping clock ? disable accessing flash area ? disable setting of stop mode ? disable stopping clock notes 1. if a security setting is not performed, flash in formation setting processing does not have to be executed. 2. if boot swap is not used, flash information setting processing and boot area swap processing do not have to be executed. chapter 26 flash memory preliminary user?s manual u17702ej1v0ud 772 26.5.4 flash functions table 26-9. main flash function list function name outline support flashenv initialization of flash control macro flashblockerase erasure of only specified one block flashwordwrite writing from specified address flashblockiverify internal verification of specified block flashblockblankcheck blank check of specified block flashflmdcheck check of flmd pin flashgetinfo reading of flash information flashsetinfo setting of flash information flashbootswap swapping of boot area flashwordread reading data from specified address remark for details, refer to the v850 series flash memory self programming (single power supply flash memory) user?s manual . contact an nec electronics sales representative for the above manual. 26.5.5 pin processing (1) flmd0 pin the flmd0 pin is used to set the operation mode when re set is released and to protect the flash memory from being written during self rewriting. it is therefore necessary to keep the voltage applied to the flmd0 pin at 0 v when reset is released and a normal operation is exec uted. it is also necessary to apply a voltage of v dd level to the flmd0 pin during the self programming m ode period via port control before the memory is rewritten. when self programming has been completed, the volt age on the flmd0 pin must be returned to 0 v. figure 26-18. mode change timing reset signal flmd0 pin v dd 0 v v dd 0 v self programming mode normal operation mode normal operation mode caution make sure that the flmd0 pin is at 0 v when reset is released. chapter 26 flash memory preliminary user?s manual u17702ej1v0ud 773 26.5.6 internal resources used the following table lists the internal resources used for se lf programming. these internal resources can also be used freely for purposes ot her than self programming. table 26-10. internal resources used resource name description entry ram area (internal ram/external ram size: 136 bytes) routines and parameters used for the flash macr o service are located in this area. the entry program and default parameters are copied by calling a library initialization function. stack area (stack size: 600 bytes) an extension of the stack us ed by the user is used by the library (can be used in both the internal ram and external ram). library code (code size: approx. 1600 bytes) program entity of library (can be used anywhere other than the flash memory block to be manipulated). application program executed as user application. calls flash functions. maskable interrupt can be used in user application execut ion status or self programming status. to use this interrupt in the self-programming status, sinc e the processing transits to the address of the internal ram start address + 4 addresses note 1 , allocate the jump instruction that transits the processing to the user interrupt se rvicing at the address of the internal ram start address + 4 addresses note 1 in advance. nmi interrupt can be used in user application execution status or self programming status. to use this interrupt in the self-programming status, sinc e the processing transits to the address of the internal ram start address note 2 , allocate the jump instruction that transits the processing to the user interrupt servic ing at the internal ram start address note 2 in advance. tm50, tm51 because tm50 and tm51 are used in the flash macro service, do not use them in the self programming status. when using tm50 and tm51 after self programming, set them again. notes 1. pd70f3733: 3ffd804h pd70f3734: 3ffb004h 2. pd70f3733: 3ffd800h pd70f3734: 3ffb000h remark for details, refer to the v850 series flash memory self pr ogramming (single power supply flash memory) user?s manual . contact an nec electronics sales representative for the above manual. preliminary user?s manual u17702ej1v0ud 774 chapter 27 on-chip debug function the v850es/kj2 has an on-chip debug function that uses the jtag (joint test acti on group) interface (drst, dck, dms, ddi, and ddo pins) and that can be used via an on-chip debug emulator (minicube ? ). caution the on-chip debug functi on is provided only in the pd70f3734. it is not provided in the pd70f3733, but an on-chip debug mode register is provided. 27.1 features { hardware break function: 2 points { software break function: 4 points { real-time ram monitor function: memory cont ents can be read during program execution. { dynamic memory modification function (dmm function): ram contents can be rewritten during program execution. { mask function: reset, nmi, hldrq, wait { rom security function: 10-byte id code authentication caution the following func tions are not supported. ? trace function ? event function ? debug interrupt inte rface function (dbint) chapter 27 on-chip debug function preliminary user?s manual u17702ej1v0ud 775 27.2 connection circuit example minicube pd70f3734 vdd dck dms ddi ddo drst reset flmd0 gnd ev dd dck dms ddi ddo drst note 2 reset flmd0 note 3 flmd1/pdl5 ev ss note 1 status target power notes 1. example of pin processing when minicube is not connected 2. a pull-down resistor is provided on chip. 3. for flash memory rewriting 27.3 interface signals the interface signals are described below. (1) drst this is a reset input signal for the on-chip debug un it. it is a negative-logic signal that asynchronously initializes the debug control unit. minicube raises the drst signal when it detects v dd of the target system after the integrated debugger is started, and starts the on-chip debug unit of the device. when the drst signal goes high, a reset signal is also generated in the cpu. when starting debugging by starti ng the integrated debugger, a cpu reset is always generated. (2) dck this is a clock input signal. it supplies a 20 mhz cl ock from minicube. in the on-chip debug unit, the dms and ddi signals are sampled at the rising edge of the dck signal, and the data ddo is output at its falling edge. chapter 27 on-chip debug function preliminary user?s manual u17702ej1v0ud 776 (3) dms this is a transfer mode select signal. the transfer st atus in the debug unit changes depending on the level of the dms signal. (4) ddi this is a data input signal. it is sampled in the on-chip debug unit at the rising edge of dck. (5) ddo this is a data output signal. it is output from the on- chip debug unit at the falling edge of the dck signal. (6) ev dd this signal is used to detect vdd of the target system. if vdd from t he target system is not detected, the signals output from minicube (drst, dck, dms, ddi, flmd0, and reset) go into a high-impedance state. (7) flmd0 the flash self programming function is used for the function to download data to the flash memory via the integrated debugger. during flash self programming, the flmd0 pin must be kept high. in addition, connect a pull-down resistor to the flmd0 pin. the flmd0 pin can be controlled in either of the following two ways. <1> to control from minicube connect the flmd0 signal of minicube to the flmd0 pin. in the normal mode, nothing is dr iven by minicube (high impedance). during a break, minicube raises the flmd0 pin to the high level when the download function of the integrated debugger is executed. <2> to control from port connect any port of the device to the flmd0 pin. the same port as the one used by the user program to realize the fl ash self programming function may be used. on the console of the integrated debugger, make a setting to raise the port pin to high level before executing the download function, or lower the port pin after executing the download function. for details, refer to the id850qb ver. 3.10 integrated de bugger operation user?s manual (u17435e) . (8) reset this is a system reset input pin. if the drst pin is made invalid by the value of the ocdm.ocdm0 bit set by the user program, on-chip debugging cannot be executed. t herefore, reset is effe cted by minicube, using the reset pin, to make the drs t pin valid (ini tialization). chapter 27 on-chip debug function preliminary user?s manual u17702ej1v0ud 777 27.4 register (1) on-chip debug m ode register (ocdm) the ocdm register is used to sele ct the normal operation mode or on-chip debug mode. this register is a special register and can be written only in a combination of specific sequences (see 3.4.7 special registers ). this register is also used to specify whether a pi n provided with an on-chip debug function is used as an on- chip debug pin or as an ordinary port/peripheral function pin. it also is used to disconnect the internal pull- down resistor of the p05 pin. the ocdm register can be written only while a low level is input to the p05 pin. this register can be read or written in 8-bit or 1-bit units. chapter 27 on-chip debug function preliminary user?s manual u17702ej1v0ud 778 0 ocdm0 0 1 operation mode ocdm 0 0 0 0 0 0 ocdm0 after reset: 01h note r/w address: fffff9fch when p05 pin is low: normal operation mode (in which a pin that functions alternately as an on-chip debug function pin is used as a port/peripheral function pin) when p05 pin is high: on-chip debug mode (in which a pin that functions alternately as an on-chip debug function pin is used as an on-chip debug mode pin) selects normal operation mode (in which a pin that functions alternately as on-chip debug function pin is used as a port/peripheral function pin) and disconnects the on-chip pull-down resistor of the p05 pin. < > note reset input sets this register to 01h. after reset by the wdtres1 or wdtres2 signal, however, the value of the ocdm register is retained. cautions 1. when using the ddi, ddo, dck, and dms pins not as on-chip debug pins but as port pins after external reset, the follo wing actions must be taken (be sure to perform the following for the pd70f3733). ? input a low level to the p05 pin. ? set the odcm0 bit. in this case, take the following actions. <1> clear the ocdm0 bit to 0. <2> fix the p05 pin to the lo w level until <1> is completed. 2. the p05 pin has an on-chip pull-down resistor. this resi stor is disconnected when the ocdm0 flag is cleared to 0. ocdm0 flag (1: pull-down on, 0: pull-down off) 10 to 100 k ? (30 k ? (typ.)) p05 chapter 27 on-chip debug function preliminary user?s manual u17702ej1v0ud 779 27.5 operation the on-chip debug function is made invalid under the conditions shown in the table below. when this function is not used, keep the drst pin low until the ocdm.ocdm0 flag is cleared to 0. ocdm0 flag drst pin 0 1 l invalid invalid h invalid valid remark l: low-level input h: high-level input figure 27-1. timing when on-chip debug function is not used low-level input after ocdm0 bit is cleared, high level can be input/output. clearing ocdm0 bit releasing reset reset ocdm0 p05/intp2/drst chapter 27 on-chip debug function preliminary user?s manual u17702ej1v0ud 780 27.6 rom security function 27.6.1 security id the flash memory versions of the v850es/kj2 perform authentication using a 10-byte id code to prevent the contents of the flash memory from being read by an unaut horized person during on-chip debugging by the on-chip debug emulator. set the id code in the 10-byte on-chip flash memory area from 0000070h to 0000079h to allow the debugger perform id authentication. if the ids match, the security is released and reading fl ash memory and using the on-chip debug emulator are enabled. ? set the 10-byte id code to 0000070h to 0000079h. ? bit 7 of 0000079h is the on-chip debug emulator enable flag. (0: disable, 1: enable) ? when the on-chip debug emulator is started, the debugger requests id input. when the id code input on the debugger and the id code set in 0000070h to 0000079h match, the debugger starts. ? debugging cannot be performed if the on-chip debug emul ator enable flag is 0, even if the id codes match. 0000079h 0000070h 0000000h security id (10 bytes) caution when the data in the flash memory has been deleted, all the bits are set to 1. chapter 27 on-chip debug function preliminary user?s manual u17702ej1v0ud 781 27.6.2 setting the following shows how to set the id code as shown in table 27-1. when the id code is set as shown in table 27-1, the id code input in the configuration dialog box of the id850qb is ?123456789abcdef123d4?. table 27-1. id code address value 0x70 0x12 0x71 0x34 0x72 0x56 0x73 0x78 0x74 0x9a 0x75 0xbc 0x76 0xde 0x77 0xf1 0x78 0x23 0x79 0xd4 the id code can be specified for the devic e file that supports the ca850 ver. 2.60 or later and the security id by the pm+ linker option setting. chapter 27 on-chip debug function preliminary user?s manual u17702ej1v0ud 782 [program example (when usi ng ca850 ver. 2.60 or later)] #-------------------------------------- # securityid (continue ilgop handler) #-------------------------------------- .section "security_id" --interrupt handler address 0x70 .word 0x78563412 --0-3 byte code .word 0xf1debc9a --4-7 byte code .hword 0xd423 --8-9 byte code remark add the above program exam ple to the startup files. 27.7 cautions (1) if a reset signal is input (from the target system or a reset signal from an internal reset source) during run (program execution), the br eak function may malfunction. (2) even if the reset signal is masked by the mask function, the i/o buffer (port pin) may be reset if a reset signal is input from a pin. (3) because a software breakpoint set in the internal flash me mory is realized by the rom correction function, it is made temporarily invalid by target reset or internal reset generated by watchdog timer 2. the breakpoint becomes valid again when a hardware break or forced br eak occurs, but a software break does not occur until then. (4) pin reset during a break is masked and the cpu and perip heral i/o are not reset. if pi n reset or internal reset is generated as soon as the flash memo ry is rewritten by dma or read by the ram monitor function while the user program is being executed, the cpu and peripheral i/o may not be correctly reset. (5) in the on-chip debug mode, the ddo pin is forcibly set to the high-level output. preliminary user?s manual u17702ej1v0ud 783 chapter 28 electrical specifications (target) absolute maximum ratings (t a = 25 c) (1/2) parameter symbol conditions ratings unit v dd v dd = ev dd = av ref0 ? 0.3 to +6.5 v bv dd bv dd v dd ? 0.3 to v dd + 0.3 note v ev dd v dd = ev dd = av ref0 ? 0.3 to +6.5 v av ref0 v dd = ev dd = av ref0 ? 0.3 to +6.5 v av ref1 av ref1 v dd (d/a output mode) av ref1 = av ref0 = v dd (port mode) ? 0.3 to v dd + 0.3 note v v ss v ss = ev ss = bv ss = av ss ? 0.3 to +0.3 v av ss v ss = ev ss = bv ss = av ss ? 0.3 to +0.3 v bv ss v ss = ev ss = bv ss = av ss ? 0.3 to +0.3 v supply voltage ev ss v ss = ev ss = bv ss = av ss ? 0.3 to +0.3 v v i1 p00 to p06, p30 to p35, p38, p39, p40 to p42, p50 to p55, p60 to p613, p80, p81, p90 to p915, reset, flmd0 ? 0.3 to ev dd + 0.3 note v v i2 pcd0 to pcd3, pcm0 to pcm5, pcs0 to pcs7, pct0 to pct7, pdl0 to pdl15, pdh0 to pdh7 ? 0.3 to bv dd + 0.3 note v v i3 p10, p11 ? 0.3 to av ref1 + 0.3 note v v i4 p36, p37, p614, p615 ? 0.3 to +13 v input voltage v i5 x1, x2, xt1, xt2 ? 0.3 to v dd + 0.3 note v analog input voltage v ian p70 to p715 ? 0.3 to av ref0 + 0.3 note v note be sure not to exceed the absolute maximum ratings (max. value) of each supply voltage. cautions 1. do not directly connect the output (or i/o) pins of ic products to each other, or to v dd , v cc , and gnd. open-drain pins or open-c ollector pins, however, can be dir ectly connected to each other. direct connection of the output pins between an ic product and an external circuit is possible, if the output pins can be set to the high-impedance stat e and the output timing of the external circuit is designed to avoid output conflict. 2. product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. that is, the ab solute maximum ratings are rate d values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that th e absolute maximum ratings are not exceeded. the ratings and conditions indicated for dc characteristics and ac characteristics represent the quality assurance range during normal operation. chapter 28 electrical specifications (target) preliminary user?s manual u17702ej1v0ud 784 absolute maximum ratings (t a = 25 c) (2/2) parameter symbol conditions ratings unit note 20 ma p36 to p39, p614, p615 per pin 30 ma p00 to p06, p30 to p39, p40 to p42 35 ma p50 to p55, p60 to p615, p80, p81, p90 to p915 total of all pins: 70 ma 35 ma pcd0 to pcd3, pcm0 to pcm5, pcs0 to pcs7, pct0 to pct7 35 ma output current, low i ol pdl0 to pdl15, pdh0 to pdh7 total of all pins: 70 ma 35 ma note per pin ? 10 ma p00 to p06, p30 to p35, p40 to p42 ? 30 ma p50 to p55, p60 to p613, p80, p81, p90 to p915 total of all pins: ? 60 ma ? 30 ma pcd0 to pcd3, pcm0 to pcm5, pcs0 to pcs7, pct0 to pct7 ? 30 ma output current, high i oh pdl0 to pdl15, pdh0 to pdh7 total of all pins: ? 60 ma ? 30 ma normal operation mode ? 40 to +85 c operating ambient temperature t a flash programming mode ? 40 to +85 c storage temperature t stg ? 40 to +125 c note p00 to p06, p10, p11, p30 to p35, p40 to p42, p50 to p55, p60 to p613, p80, p81, p90 to p915, pcd0 to pcd3, pcm0 to pcm5, pcs0 to pcs7, pct0 to pct7, pdl0 to pdl15, pdh0 to pdh7 cautions 1. do not directly connect the output (or i/o) pins of ic products to each other, or to v dd , v cc , and gnd. open-drain pins or open-c ollector pins, however, can be dir ectly connected to each other. direct connection of the output pins between an ic product and an external circuit is possible, if the output pins can be set to the high-impedance stat e and the output timing of the external circuit is designed to avoid output conflict. 2. product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. that is, the ab solute maximum ratings are rate d values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that th e absolute maximum ratings are not exceeded. the ratings and conditions indicated for dc characteristics and ac characteristics represent the quality assurance range during normal operation. capacitance (t a = 25 c, v dd = ev dd = av ref0 = bv dd = av ref1 = v ss = ev ss = bv ss = av ss = 0 v) parameter symbol conditions min. typ. max. unit input capacitance c i p70 to p715 15 pf note 15 pf i/o capacitance c io f x = 1 mhz unmeasured pins returned to 0 v p36 to p39, p614, p615 20 pf note p00 to p06, p10, p11, p30 to p35, p40 to p42, p50 to p55, p60 to p 613, p80, p81, p90 to p915, pcd0 to pcd3, pcm0 to pcm5, pcs0 to pcs7, pct0 to pct7, pdl0 to pdl15, pdh0 to pdh7 remark f x : main clock oscillation frequency chapter 28 electrical specifications (target) preliminary user?s manual u17702ej1v0ud 785 operating conditions (t a = ? 40 to +85 c, v dd = ev dd = av ref0 = 2.7 to 5.5 v, 2.7 v bv dd v dd , 2.7 v av ref1 v dd , v ss = ev ss = bv ss = av ss = 0 v, c l = 50 pf) parameter symbol conditions min. typ. max. unit regc = v dd = 4.5 to 5.5 v 0.25 20 mhz regc = v dd = 4.0 to 5.5 v 0.25 16 mhz regc = 10 f, v dd = 4.0 to 5.5 v 0.25 16 mhz in pll mode regc = v dd = 2.7 to 5.5 v 0.25 10 mhz regc = 10 f, v dd = 4.0 to 5.5 v 0.0625 10 mhz in clock-through mode regc = v dd = 2.7 to 5.5 v 0.0625 10 mhz internal system clock frequency f clk operating with subclock note 32.768 khz note regc = v dd = 2.7 to 5.5 v or regc = 10 f, v dd = 4.0 to 5.5 v internal system clock fr equency vs. supply voltage 1.0 0.1 0.032 0.01 supply voltage v dd [v] when regc = 10 f internal system clock frequency f clk [mhz] 2.0 2.5 2.7 10.0 16.0 20.0 100 3.0 3.5 4.0 4.5 5.0 5.5 6.0 pll characteristics (t a = ? 40 to + 85 c, v dd = 2.7 to 5.5 v, v ss = 0 v) parameter symbol conditions min. typ. max. unit input frequency f x 2 5 mhz output frequency f xx 8 20 mhz lock time t pll after v dd reaches 2.7 v (min.) 200 s chapter 28 electrical specifications (target) preliminary user?s manual u17702ej1v0ud 786 operating conditions for eeprom emulation (t a = ? 40 to +85 c, v dd = ev dd = av ref0 = 2.7 to 5.5 v, 2.7 v bv dd v dd , 2.7 v av ref1 v dd , v ss = ev ss = bv ss = av ss = 0 v, c l = 50 pf) parameter symbol conditions min. typ. max. unit regc = v dd = 4.5 to 5.5 v 0.25 16 mhz regc = v dd = 4.0 to 5.5 v 0.25 12 mhz regc = 10 f, v dd = 4.0 to 5.5 v 0.25 6 mhz in pll mode regc = v dd = 2.7 to 5.5 v 0.25 6 mhz regc = v dd = 4.0 to 5.5 v 0.0625 10 mhz regc = 10 f, v dd = 4.0 to 5.5 v 0.0625 6 mhz in clock-through mode regc = v dd = 2.7 to 5.5 v 0.0625 6 mhz internal system clock frequency f clk operating with subclock notes 1, 2 32.768 khz notes 1. regc = v dd = 2.7 to 5.5 v or regc = 10 f, v dd = 4.0 to 5.5 v 2. do not stop the main clock. internal system clock fr equency vs. supply voltage 1.0 0.1 0.032 0.01 supply voltage v dd [v] when regc = 10 f internal system clock frequency f clk [mhz] 2.0 2.5 2.7 3.5 10.0 6.0 20.0 16.0 100 3.0 4.0 5.0 5.5 4.5 6.0 chapter 28 electrical specifications (target) preliminary user?s manual u17702ej1v0ud 787 main clock oscilla tor characteristics (1) crystal resonator, ceramic resonator (t a = ? 40 to +85 c, v dd = 2.7 to 5.5 v, v ss = 0 v) recommended circuit parameter conditions min. typ. max. unit regc = v dd = 4.5 to 5.5 v 2 5 mhz regc = v dd = 4.0 to 5.5 v 2 4 mhz regc = 10 f, v dd = 4.0 to 5.5 v 2 4 mhz in pll mode regc = v dd = 2.7 to 5.5 v 2 2.5 mhz regc = v dd = 2.7 to 5.5 v 2 10 mhz oscillation frequency (f x ) note 1 in clock through mode regc = 10 f, v dd = 4.0 to 5.5 v 2 10 mhz after reset is released osts0 = 1 2 15 /f x s x2 x1 oscillation stabilization time note 2 after stop mode is released note 3 s notes 1. indicates only oscillator characteristics. 2. time required to stabilize the resonator after reset or stop mode is released. 3. the value differs depending on the osts register settings. (2) external clock (t a = ? 40 to +85 c, regc = v dd = 2.7 to 5.5 v, v ss = 0 v) recommended circuit parameter conditions min. typ. max. unit regc = v dd = 4.5 to 5.5 v 2 5 mhz regc = v dd = 4.0 to 5.5 v 2 4 mhz in pll mode regc = v dd = 2.7 to 5.5 v 2 2.5 mhz x2 x1 external clock x1, x2 input frequency (f x ) note in clock through mode regc = v dd = 2.7 to 5.5 v 2 10 mhz note the duty ratio of the input waveform must be within 50% 5%. cautions 1. when using the main cl ock oscillator, wire as follows in the area enclosed by th e broken lines in the above figures to avo id an adverse effect fr om wiring capacitance. ? keep the wiring length as short as possible. do not cross the wiring with the other signal lines. do not route the wiring near a signal line th rough which a high fluctuating current flows. always make the ground point of the osci llator capacitor the same potential as v ss . do not ground the capacitor to a ground pa ttern through which a high current flows. do not fetch signals from the oscillator. 2. when the main clock is stopped and the devi ce is operating on the subclock, wait until the oscillation stabilization time has been secured by the program before switching back to the main clock. 3. when regc = 10 f, the supply voltage to the oscillator is the on-chip regulator output (3.6 v (typ.)). however, the supply vo ltage to the oscillator is v dd in the following modes. after reset (except during wdtres1 and oscillation stabilization time) in stop mode in sub-idle mode chapter 28 electrical specifications (target) preliminary user?s manual u17702ej1v0ud 788 subclock oscillato r characteristics (1) crystal resonator (t a = ? 40 to +85 c, v dd = 2.7 to 5.5 v, v ss = 0 v) recommended circuit parameter conditions min. typ. max. unit oscillation frequency (f xt ) note 1 32 32.768 35 khz xt2 xt1 oscillation stabilization time note 2 10 s notes 1. indicates only oscillator characteristics. 2. time required from when v dd reaches oscillation voltage range (2 .7 v (min.)) to when the crystal resonator stabilizes. (2) external clock (t a = ? 40 to +85 c, regc = v dd = 2.7 to 5.5 v, v ss = 0 v) recommended circuit parameter conditions min. typ. max. unit xt2 xt1 external clock xt1 input frequency (f xt ) note regc = v dd = 2.7 to 5.5 v 32 35 khz note the duty ratio of the input waveform must be within 50% 5%. cautions 1. when using the subclock oscillator, wire as follows in the area enclosed by the broken lines in the above figures to avo id an adverse effect fr om wiring capacitance. keep the wiring length as short as possible. do not cross the wiring with the other signal lines. do not route the wiring near a signal line th rough which a high fluctuating current flows. always make the ground point of the osci llator capacitor the same potential as v ss . do not ground the capacitor to a ground pa ttern through which a high current flows. do not fetch signals from the oscillator. 2. the subclock oscillator is designed as a low-am plitude circuit for reducing power consumption, and is more prone to malfunction due to noise than the main clock oscillato r. particular care is therefore required with the wiring me thod when the subclock is used. 3. when regc = 10 f, the supply voltage to the oscillator is the on-chip regulator output (3.6 v (typ.)). however, the supply vo ltage to the oscillator is v dd in the following modes. after reset (except during wdtres1 and oscillation stabilization time) in stop mode in sub-idle mode chapter 28 electrical specifications (target) preliminary user?s manual u17702ej1v0ud 789 dc characteristics (t a = ? 40 to +85 c, v dd = ev dd = av ref0 = 2.7 to 5.5 v, 2.7 v bv dd v dd , 2.7 v av ref1 v dd , v ss = ev ss = bv ss = av ss = 0 v) (1/4) parameter symbol conditions max. unit per pin for p00 to p06, p10, p11, p30 to p35, p40 to p42, p50 to p55, p60 to p613, p80, p81, p90 to p915 ? 5.0 ma ev dd = 4.0 to 5.5 v ? 30 ma total of p00 to p06, p30 to p35, p40 to p42 ev dd = 2.7 to 5.5 v ? 15 ma ev dd = 4.0 to 5.5 v ? 30 ma i oh1 total of p50 to p55, p60 to p613, p80, p81, p90 to p915 ev dd = 2.7 to 5.5 v ? 15 ma per pin for pcd0 to pcd3, pcm0 to pcm5, pcs0 to pcs7, pct0 to pct7, pdh0 to pdh7, pdl0 to pdl15 ? 5.0 ma bv dd = 4.0 to 5.5 v ? 30 ma total of pcd0 to pcd3, pcm0 to pcm5, pcs0 to pcs7, pct0 to pct7 bv dd = 2.7 to 5.5 v ? 15 ma bv dd = 4.0 to 5.5 v ? 30 ma output current, high i oh2 total of pdl0 to pdl15, pdh0 to pdh7 bv dd = 2.7 to 5.5 v ? 15 ma per pin for p00 to p06, p10, p11, p30 to p35, p40 to p42, p50 to p55, p60 to p613, p80, p81, p90 to p915 10 ma ev dd = 4.0 to 5.5 v 15 ma per pin for p36 to p39 ev dd = 2.7 to 5.5 v 8 ma ev dd = 4.0 to 5.5 v 10 ma per pin for p614, p615 ev dd = 2.7 to 5.5 v 5 ma total of p00 to p06, p30 to p37, p40 to p42 30 ma i ol1 total of p38, p39, p50 to p55, p60 to p615, p80, p81, p90 to p915 30 ma per pin for pcd0 to pcd3, pcm0 to pcm5, pcs0 to pcs7, pct0 to pct7, pdh0 to pdh7, pdl0 to pdl15 10 ma total of pcd0 to pcd3, pcm0 to pcm5, pcs0 to pcs7, pct0 to pct7 30 ma output current, low i ol2 total of pdl0 to pdl15, pdh0 to pdh7 30 ma chapter 28 electrical specifications (target) preliminary user?s manual u17702ej1v0ud 790 dc characteristics (t a = ? 40 to +85 c, v dd = ev dd = av ref0 = 2.7 to 5.5 v, 2.7 v bv dd v dd , 2.7 v av ref1 v dd , v ss = ev ss = bv ss = av ss = 0 v) (2/4) parameter symbol conditions min. typ. max. unit v ih1 note 1 0.7ev dd ev dd v v ih2 note 2 0.8ev dd ev dd v v ih3 note 3 0.7bv dd bv dd v v ih4 p70 to p715 0.7av ref0 av ref0 v v ih5 p10, p11 note 4 0.7av ref1 av ref1 v v ih6 p36, p37, p614, p615 0.7ev dd 12 v input voltage, high v ih7 note 5 x1, x2, xt1, xt2 v dd ? 0.5 v dd v v il1 note 1 ev ss 0.3ev dd v v il2 note 2 ev ss 0.2ev dd v v il3 note 3 bv ss 0.3bv dd v v il4 p70 to p715 av ss 0.3av ref0 v v il5 p10, p11 note 4 av ss 0.3av ref1 v v il6 p36, p37, p614, p615 ev ss 0.3ev dd v input voltage, low v il7 note 5 x1, x2, xt1, xt2 v ss 0.4 v notes 1. p00, p01, p30, p41, p60 to p65, p67, p611 , p98, p911 and their alternate-function pins. 2. reset, flmd0, p02 to p06, p31 to p35, p38, p39, p40, p42, p50 to p55, p66, p68 to p610, p612, p613, p80, p81, p90 to p97, p99, p910, p9 12 to p915 and their alternate-function pins. 3. pcd0 to pcd3, pcm0 to pcm5, pcs0 to pcs7, pct0 to pct7, pdl0 to pdl15, pdh0 to pdh7 and their alternate-function pins. 4. when used as port pins, set av ref1 = av ref0 = v dd. 5. when the external clock is used. chapter 28 electrical specifications (target) preliminary user?s manual u17702ej1v0ud 791 dc characteristics (t a = ? 40 to +85 c, v dd = ev dd = av ref0 = 2.7 to 5.5 v, 2.7 v bv dd v dd , 2.7 v av ref1 v dd , v ss = ev ss = bv ss = av ss = 0 v) (3/4) parameter symbol conditions min. typ. max. unit note 1 i oh = ? 2.0 ma, ev dd = 4.0 to 5.5 v ev dd ? 1.0 ev dd v v oh1 note 2 i oh = ? 0.1 ma, ev dd = 2.7 to 5.5 v ev dd ? 0.5 ev dd v note 3 i oh = ? 2.0 ma, bv dd = 4.0 to 5.5 v bv dd ? 1.0 bv dd v v oh2 note 4 i oh = ? 0.1 ma, bv dd = 2.7 to 5.5 v bv dd ? 0.5 bv dd v i oh = ? 2.0 ma av ref1 ? 1.0 av ref1 v output voltage, high v oh3 p10, p11 note 5 i oh = ? 0.1 ma av ref1 ? 0.5 av ref1 v v ol1 note 6 i ol = 2.0 ma note 7 0 0.8 v v ol2 note 8 i ol = 2.0 ma 0 0.8 v v ol3 p10, p11 note 5 i ol = 2.0 ma 0 0.8 v i ol = 15 ma, ev dd = 4.0 to 5.5 v 0 2.0 v i ol = 8 ma, ev dd = 3.0 to 5.5 v 0 1.0 v v ol4 p36 to p39 i ol = 5 ma, ev dd = 2.7 to 5.5 v 0 1.0 v i ol = 10 ma, ev dd = 4.0 to 5.5 v 0 2.0 v output voltage, low v ol5 p614, p615 i ol = 5 ma, ev dd = 2.7 to 5.5 v 0 1.0 v input leakage current, high i lih v in = v dd 3.0 a input leakage current, low i lil v in = 0 v ? 3.0 a output leakage current, high i loh v o = v dd 3.0 a output leakage current, low i lol v o = 0 v ? 3.0 a pull-up resistor r l v in = 0 v 10 30 100 k ? notes 1. total of p00 to p06, p30 to p35, p40 to p42 and their alternate-function pins: i oh = ? 30 ma, total of p50 to p55, p60 to p613, p80, p81, p90 to p915 and their alternate-function pins: i oh = ? 30 ma. 2. total of p00 to p06, p30 to p35, p40 to p42 and their alternate-function pins: i oh = ? 15 ma, total of p50 to p55, p60 to p613, p80, p81, p90 to p915 and their alternate-function pins: i oh = ? 15 ma. 3. total of pcd0 to pcd3 , pcm0 to pcm5, pcs0 to pcs7, pct0 to pct7: i oh = ? 30 ma, total of pdh0 to pdh7, pdl0 to pdl15 and their alternate-function pins: i oh = ? 30 ma. 4. total of pcd0 to pcd3 , pcm0 to pcm5, pcs0 to pcs7, pct0 to pct7: i oh = ? 15 ma, total of pdh0 to pdh7, pdl0 to pdl15 and their alternate-function pins: i oh = ? 15 ma. 5. when used as port pins, set av ref1 = av ref0 = v dd . 6. total of p00 to p06, p30 to p37, p40 to p42 and their alternate-function pins: i ol = 30 ma, total of p38, p39, p50 to p55, p60 to p615, p80, p81, p90 to p915 and their alternate-function pins: i ol = 30 ma. 7. refer to i ol1 for i ol of p36 to p39, p614, and p615. 8. total of pcd0 to pcd3, pcm0 to pcm5, pcs0 to pcs7, pct0 to pc t7 and their alternate-function pins: i ol = 30 ma, total of pdh0 to pdh7, pdl0 to pdl15 and their alternate-function pins: i ol = 30 ma. chapter 28 electrical specifications (target) preliminary user?s manual u17702ej1v0ud 792 dc characteristics (t a = ? 40 to +85 c, v dd = ev dd = av ref0 = 2.7 to 5.5 v, 2.7 v bv dd v dd , 2.7 v av ref1 v dd , v ss = ev ss = bv ss = av ss = 0 v) (4/4) parameter symbol conditions min. typ. note 2 max. unit normal operation mode (all peripheral functions operating) f xx = 20 mhz (f x = 5 mhz) (in pll mode) regc = v dd = 5 v 10% 55 75 ma f xx = 16 mhz (f x = 4 mhz) (in pll mode) v dd = 5 v 10%, regc = 10 f 34 50 ma i dd1 f xx = 10 mhz (in clock-through mode) regc = v dd = 3 v 10% 18 37 ma halt mode (all peripheral functions operating) f xx = 20 mhz (f x = 5 mhz) (in pll mode) regc = v dd = 5 v 10% 29 43 ma f xx = 16 mhz (f x = 4 mhz) (in pll mode) v dd = 5 v 10%, regc = 10 f 17 31 ma i dd2 f xx = 10 mhz (in clock-through mode) regc = v dd = 3 v 10% 10 17 ma idle mode (watch timer operating) f x = 5 mhz (when pll mode off) regc = v dd = 5 v 10% 2.1 3.3 ma f x = 4 mhz (when pll mode off) v dd = 5 v 10%, regc = 10 f 1.5 2.7 ma i dd3 f x = 10 mhz (in clock-through mode) regc = v dd = 3 v 10% 1.5 2.7 ma i dd4 subclock operation mode (f xt = 32.768 khz) main oscillation stopped 250 420 a i dd5 sub-idle mode (f xt = 32.768 khz) watch timer operating, main oscillation stopped 20 75 a stop mode subclock oscillating 15 60 a i dd6 subclock stopped (xt1 = v ss , psmr.xtstp bit = 1) 0.1 30 a flash memory erase/write (t a = ? 40 to +85 c) f xx = 20 mhz (f x = 5 mhz) (in pll mode) regc = v dd = 5 v 10% 55 75 ma f xx = 16 mhz (f x = 4 mhz) (in pll mode) v dd = 5 v 10%, regc = 10 f 34 50 ma supply current note 1 i dd7 f xx = 10 mhz (in clock-through mode) regc = v dd = 3 v 10% 18 37 ma notes 1. total current of v dd , ev dd , and bv dd (all ports stopped). av ref0 and av ref1 are not included. 2. typ. value of v dd is as follows. v dd = 5.0 v when v dd = 5 v 10% v dd = 3.0 v when v dd = 3 v 10% remark f xx : main clock frequency f x : main clock oscillation frequency f xt : subclock frequency chapter 28 electrical specifications (target) preliminary user?s manual u17702ej1v0ud 793 data retention characteristics stop mode (t a = ? 40 to +85 c) parameter symbol conditions min. typ. max. unit data retention voltage v dddr stop mode 2.0 5.5 v stop release signal input time t drel 0 s caution shifting to stop mode and restoring from stop mode mu st be performed within the rated operating range. t drel stop release signal input stop mode setting v dddr v dd reset (input) stop mode release interrupt (nmi, etc.) (released by falling edge) stop mode release interrupt (nmi, etc.) (released by rising edge) operating voltage lower limit chapter 28 electrical specifications (target) preliminary user?s manual u17702ej1v0ud 794 ac characteristics ac test input measurement points (v dd , av ref0 , ev dd, bv dd ) ac test output measurement points load conditions v oh v ol v oh v ol measurement points dut (device under measurement) c l = 50 pf caution if the load capaci tance exceeds 50 pf due to the circ uit configuration, bring the load capacitance of the device to 50 pf or less by inserting a buffer or by some other means. v dd 0 v v ih v il v ih v il measurement points chapter 28 electrical specifications (target) preliminary user?s manual u17702ej1v0ud 795 clkout output timing (t a = ? 40 to +85 c, v dd = ev dd = av ref0 = 2.7 to 5.5 v, 2.7 v bv dd v dd , 2.7 v av ref1 v dd , v ss = ev ss = bv ss = av ss = 0 v, c l = 50 pf) parameter symbol conditions min. max. unit output cycle t cyk <1> 50 ns 30.6 s v dd = 4.0 to 5.5 v t cyk /2 ? 17 ns high-level width t wkh <2> v dd = 2.7 to 5.5 v t cyk /2 ? 26 ns v dd = 4.0 to 5.5 v t cyk /2 ? 17 ns low-level width t wkl <3> v dd = 2.7 to 5.5 v t cyk /2 ? 26 ns v dd = 4.0 to 5.5 v 17 ns rise time t kr <4> v dd = 2.7 to 5.5 v 26 ns v dd = 4.0 to 5.5 v 17 ns fall time t kf <5> v dd = 2.7 to 5.5 v 26 ns clock timing clkout (output) <1> <2> <3> <4> <5> chapter 28 electrical specifications (target) preliminary user?s manual u17702ej1v0ud 796 bus timing (1) in multiplex bus mode (a) read/write cycle (clkout asynchronous) (t a = ? 40 to +85 c, v dd = ev dd = av ref0 = 4.0 to 5.5 v, 4.0 v bv dd v dd , 4.0 v av ref1 v dd , v ss = ev ss = bv ss = av ss = 0 v, c l = 50 pf) (1/2) parameter symbol conditions min. max. unit address setup time (to astb ) t sast <6> (0.5 + t asw )t ? 23 ns address hold time (from astb ) t hsta <7> (0.5 + t ahw )t ? 15 ns delay time from rd to address float t frda <8> 16 ns data input setup time from address t said <9> (2 + n + t asw + t ahw )t ? 40 ns data input setup time from rd t srid <10> (1 + n)t ? 25 ns delay time from astb to rd, wrm t dstrdwr <11> (0.5 + t ahw )t ? 20 ns data input hold time (from rd ) t hrdid <12> 0 ns address output time from rd t drda <13> (1 + i)t ? 16 ns delay time from rd, wrm to astb t drdwrst <14> 0.5t ? 10 ns delay time from rd to astb t drdst <15> (1.5 + i + t asw )t ? 10 ns rd, wrm low-level width t wrdwrl <16> (1 + n)t ? 10 ns astb high-level width t wsth <17> (1 + i + t asw )t ? 25 ns data output time from wrm t dwrod <18> 20 ns data output setup time (to wrm ) t sodwr <19> (1 + n)t ? 25 ns data output hold time (from wrm ) t hwrod <20> t ? 15 ns t sawt1 <21> (1.5 + t asw + t ahw )t ? 45 ns wait setup time (to address) t sawt2 <22> n 1 (1.5 + n + t asw + t ahw )t ? 45 ns t hawt1 <23> (0.5 + n + t asw + t ahw )t ns wait hold time (from address) t hawt2 <24> n 1 (1.5 + n + t asw + t ahw )t ns t sstwt1 <25> (1 + t ahw )t ? 32 ns wait setup time (to astb ) t sstwt2 <26> n 1 (1 + n + t ahw )t ? 32 ns t hstwt1 <27> (n + t ahw )t ns wait hold time (from astb ) t hstwt2 <28> n 1 (1 + n + t ahw )t ns remarks 1. t asw : number of address setup wait clocks (0 or 1) t ahw : number of address hold wait clocks (0 or 1) 2. t = 1/f cpu (f cpu : cpu operating clock frequency) 3. n: number of wait clocks inserted in the bus cycle the sampling timing changes when a programmable wait is inserted. 4. m = 0, 1 5. i: number of idle states inserted after a read cycle (0 or 1) 6. the values in the above specifications are values for when clocks with a 1:1 duty ratio are input from x1. chapter 28 electrical specifications (target) preliminary user?s manual u17702ej1v0ud 797 (t a = ? 40 to +85 c, v dd = ev dd = av ref0 = 2.7 to 5.5 v, 2.7 v bv dd v dd , 2.7 v av ref1 v dd , v ss = ev ss = bv ss = av ss = 0 v, c l = 50 pf) (2/2) parameter symbol conditions min. max. unit address setup time (to astb ) t sast <6> (0.5 + t asw )t ? 42 ns address hold time (from astb ) t hsta <7> (0.5 + t ahw )t ? 30 ns delay time from rd to address float t frda <8> 32 ns data input setup time from address t said <9> (2 + n + t asw + t ahw )t ? 72 ns data input setup time from rd t srid <10> (1 + n)t ? 40 ns delay time from astb to rd, wrm t dstrdwr <11> (0.5 + t ahw )t ? 35 ns data input hold time (from rd ) t hrdid <12> 0 ns address output time from rd t drda <13> (1 + i)t ? 32 ns delay time from rd, wrm to astb t drdwrst <14> 0.5t ? 20 ns delay time from rd to astb t drdst <15> (1.5 + i + t asw )t ? 20 ns rd, wrm low-level width t wrdwrl <16> (1 + n)t ? 20 ns astb high-level width t wsth <17> (1 + i + t asw )t ? 50 ns data output time from wrm t dwrod <18> 35 ns data output setup time (to wrm ) t sodwr <19> (1 + n)t ? 40 ns data output hold time (from wrm ) t hwrod <20> t ? 30 ns t sawt1 <21> (1.5 + t asw + t ahw )t ? 80 ns wait setup time (to address) t sawt2 <22> n 1 (1.5 + n + t asw + t ahw )t ? 80 ns t hawt1 <23> (0.5 + n + t asw + t ahw )t ns wait hold time (from address) t hawt2 <24> n 1 (1.5 + n + t asw + t ahw )t ns t sstwt1 <25> (1 + t ahw )t ? 60 ns wait setup time (to astb ) t sstwt2 <26> n 1 (1 + n + t ahw )t ? 60 ns t hstwt1 <27> (n + t ahw )t ns wait hold time (from astb ) t hstwt2 <28> n 1 (1 + n + t ahw )t ns caution set the following in accordan ce with the usage conditions of the cpu operating clock frequency (k = 0 to 3). ? 70 ns < 1/ f cpu < 84 ns set an address setup wait (awc.aswk bit = 1). ? 62.5 ns < 1/ f cpu < 70 ns set an address setup wait (aswk bit = 1) and address hold wait (awc.ahwk bit = 1). remarks 1. t asw : number of address setup wait clocks (0 or 1) t ahw : number of address hold wait clocks (0 or 1) 2. t = 1/f cpu (f cpu : cpu operating clock frequency) 3. n: number of wait clocks inserted in the bus cycle the sampling timing changes when a programmable wait is inserted. 4. m = 0, 1 5. i: number of idle states inserted after a read cycle (0 or 1) 6. the values in the above specifications are values for when clocks with a 1:1 duty ratio are input from x1. chapter 28 electrical specifications (target) preliminary user?s manual u17702ej1v0ud 798 read cycle (clkout asynchr onous): in multiplex bus mode clkout (output) a16 to a23 (output) cs0 to cs3 (output) ad0 to ad15 (i/o) astb (output) rd (output) wait (input) t1 t2 tw t3 data address hi-z <6> <7> <17> <9> <12> <14> <10> <11> <25> <27> <26> <28> <21> <23> <22> <24> <16> <8> <13> <15> remark wr0 and wr1 are high level. chapter 28 electrical specifications (target) preliminary user?s manual u17702ej1v0ud 799 write cycle (clkout asynchr onous): in multiplex bus mode clkout (output) ad0 to ad15 (i/o) astb (output) wr0 (output), wr1 (output) wait (input) t1 t2 tw t3 data address <25> <27> <26> <28> <21> <23> <22> <24> <6> <17> <7> <14> <20> <19> <16> <11> <18> a16 to a23 (output) cs0 to cs3 (output) remark rd is high level. chapter 28 electrical specifications (target) preliminary user?s manual u17702ej1v0ud 800 (b) read/write cycle (clkout synch ronous): in multiplex bus mode (t a = ? 40 to +85 c, v dd = ev dd = av ref0 = 4.0 to 5.5 v, 4.0 v bv dd v dd , 4.0 v av ref1 v dd , v ss = ev ss = bv ss = av ss = 0 v, c l = 50 pf) (1/2) parameter symbol conditions min. max. unit delay time from clkout to address t dka <29> 0 19 ns delay time from clkout to address float t fka <30> 0 14 ns delay time from clkout to astb t dkst <31> 0 23 ns delay time from clkout to rd, wrm t dkrdwr <32> ? 22 0 ns data input setup time (to clkout ) t sidk <33> 15 ns data input hold time (from clkout ) t hkid <34> 0 ns data output delay time from clkout t dkod <35> 19 ns wait setup time (to clkout ) t swtk <36> 15 ns wait hold time (from clkout ) t hkwt <37> 0 ns remarks 1. m = 0, 1 2. the values in the above specifications are values for when clocks with a 1:1 duty ratio are input from x1. (t a = ? 40 to +85 c, v dd = ev dd = av ref0 = 2.7 to 5.5 v, 2.7 v bv dd v dd , 2.7 v av ref1 v dd , v ss = ev ss = bv ss = av ss = 0 v, c l = 50 pf) (2/2) parameter symbol conditions min. max. unit delay time from clkout to address t dka <29> 0 19 ns delay time from clkout to address float t fka <30> 0 18 ns delay time from clkout to astb t dkst <31> 0 55 ns delay time from clkout to rd, wrm t dkrdwr <32> ? 22 0 ns data input setup time (to clkout ) t sidk <33> 30 ns data input hold time (from clkout ) t hkid <34> 0 ns data output delay time from clkout t dkod <35> 19 ns wait setup time (to clkout ) t swtk <36> 25 ns wait hold time (from clkout ) t hkwt <37> 0 ns remarks 1. m = 0, 1 2. the values in the above specifications are values for when clocks with a 1:1 duty ratio are input from x1. chapter 28 electrical specifications (target) preliminary user?s manual u17702ej1v0ud 801 read cycle (clkout synchronous): in multiplex bus mode clkout (output) a16 to a23 (output) cs0 to cs3 (output) ad0 to ad15 (i/o) astb (output) rd (output) wait (input) t1 t2 tw t3 data address hi-z <29> <31> <32> <30> <31> <32> <36> <36> <37> <37> <33> <34> remark wr0 and wr1 are high level. chapter 28 electrical specifications (target) preliminary user?s manual u17702ej1v0ud 802 write cycle (clkout synchronous): in multiplex bus mode clkout (output) ad0 to ad15 (i/o) astb (output) wr0 (output), wr1 (output) wait (input) t1 t2 tw t3 data address <29> <31> <32> <32> <37> <37> <36> <36> <31> <35> a16 to a23 (output) cs0 to cs3 (output) remark rd is high level. chapter 28 electrical specifications (target) preliminary user?s manual u17702ej1v0ud 803 (2) in separate bus mode (a) read cycle (clkout asynchr onous): in separate bus mode (t a = ? 40 to +85 c, v dd = ev dd = av ref0 = 4.0 to 5.5 v, 4.0 v bv dd v dd , 4.0 v av ref1 v dd , v ss = ev ss = bv ss = av ss = 0 v, c l = 50 pf) (1/2) parameter symbol conditions min. max. unit address setup time (to rd ) t sard <38> (0.5 + t asw )t ? 50 ns address hold time (from rd ) t hard <39> it ? 13 ns rd low-level width t wrdl <40> (1.5 + n + t ahw )t ? 15 ns data setup time (to rd ) t sisd <41> 30 ns data hold time (from rd ) t hisd <42> 0 ns data setup time (to address) t said <43> (2 + n + t asw + t ahw )t ? 65 ns t srdwt1 <44> (0.5 + t ahw )t ? 32 ns wait setup time (to rd ) t srdwt2 <45> n 1 (0.5 + n + t ahw )t ? 32 ns t hrdwt1 <46> (n ? 0.5 + t ahw )t ns wait hold time (from rd ) t hrdwt2 <47> n 1 (n + 0.5 + t ahw )t ns t sawt1 <48> (1 + t asw + t ahw )t ? 65 ns wait setup time (to address) t sawt2 <49> n 1 (1 + n + t asw + t ahw )t ? 65 ns t hawt1 <50> (n + t asw + t ahw )t ns wait hold time (from address) t hawt2 <51> n 1 (1 + n + t asw + t ahw )t ns caution set the following in accordan ce with the usage conditions of the cpu operating clock frequency (k = 0 to 3). ? 1/ f cpu < 100 ns set an address setup wait (aswk bit = 1). remarks 1. t asw : number of address setup wait clocks (0 or 1) t ahw : number of address hold wait clocks (0 or 1) 2. t = 1/f cpu (f cpu : cpu operating clock frequency) 3. n: number of wait clocks inserted in the bus cycle the sampling timing changes when a programmable wait is inserted 4. i: number of idle states inserted after a read cycle (0 or 1) 5. the values in the above specifications are values for when clocks with a 1:1 duty ratio are input from x1. chapter 28 electrical specifications (target) preliminary user?s manual u17702ej1v0ud 804 (t a = ? 40 to +85 c, v dd = ev dd = av ref0 = 2.7 to 5.5 v, 2.7 v bv dd v dd , 2.7 v av ref1 v dd , v ss = ev ss = bv ss = av ss = 0 v, c l = 50 pf) (2/2) parameter symbol conditions min. max. unit address setup time (to rd ) t sard <38> (0.5 + t asw )t ? 100 ns address hold time (from rd ) t hard <39> it ? 26 ns rd low-level width t wrdl <40> (1.5 + n + t ahw )t ? 30 ns data setup time (to rd ) t sisd <41> 60 ns data hold time (from rd ) t hisd <42> 0 ns data setup time (to address) t said <43> (2 + n + t asw + t ahw )t ? 120 ns t srdwt1 <44> (0.5 + t ahw )t ? 50 ns wait setup time (to rd ) t srdwt2 <45> n 1 (0.5 + n + t ahw )t ? 50 ns t hrdwt1 <46> (n ? 0.5 + t ahw )t ns wait hold time (from rd ) t hrdwt2 <47> n 1 (n + 0.5 + t ahw )t ns t sawt1 <48> (1 + t asw + t ahw )t ? 130 ns wait setup time (to address) t sawt2 <49> n 1 (1 + n + t asw + t ahw )t ? 130 ns t hawt1 <50> (n + t asw + t ahw )t ns wait hold time (from address) t hawt2 <51> n 1 (1 + n + t asw + t ahw )t ns caution set the following in accordan ce with the usage conditions of the cpu operating clock frequency (k = 0 to 3). ? 1/ f cpu < 200 ns set an address setup wait (aswk bit = 1). remarks 1. t asw : number of address setup wait clocks (0 or 1) t ahw : number of address hold wait clocks (0 or 1) 2. t = 1/f cpu (f cpu : cpu operating clock frequency) 3. n: number of wait clocks inserted in the bus cycle the sampling timing changes when a programmable wait is inserted. 4. i: number of idle states inserted after a read cycle (0 or 1) 5. the values in the above specifications are values for when clocks with a 1:1 duty ratio are input from x1. chapter 28 electrical specifications (target) preliminary user?s manual u17702ej1v0ud 805 read cycle (clkout asynchr onous): in separate bus mode clkout (output) t1 <43> hi-z hi-z <38> <40> <47> <45> <46> <44> <48> <50> <49> <51> <42> <41> <39> tw t2 rd (output) cs0 to cs3 (output) a0 to a23 (output) ad0 to ad15 (i/o) wait (input) remark wr0 and wr1 are high level. chapter 28 electrical specifications (target) preliminary user?s manual u17702ej1v0ud 806 (b) write cycle (clkout asynchr onous): in separate bus mode (t a = ? 40 to +85 c, v dd = ev dd = av ref0 = 4.0 to 5.5 v, 4.0 v bv dd v dd , 4.0 v av ref1 v dd , v ss = ev ss = bv ss = av ss = 0 v, c l = 50 pf) (1/2) parameter symbol conditions min. max. unit address setup time (to wrm ) t sawr <52> (1 + t asw + t ahw )t ? 60 ns address hold time (from wrm ) t hawr <53> 0.5t ? 10 ns wrm low-level width t wwrl <54> (0.5 + n)t ? 10 ns delay time from wrm to data output t dosdw <55> ? 5 ns data setup time (to wrm ) t sosdw <56> (0.5 + n)t ? 20 ns data hold time (from wrm ) t hosdw <57> 0.5t ? 20 ns data setup time (to address) t saod <58> (1 + t asw + t ahw )t ? 30 ns t swrwt1 <59> 30 ns wait setup time (to wrm ) t swrwt2 <60> n 1 nt ? 30 ns t hwrwt1 <61> 0 ns wait hold time (from wrm ) t hwrwt2 <62> n 1 nt ns t sawt1 <63> (1 + t asw + t ahw )t ? 45 ns wait setup time (to address) t sawt2 <64> n 1 (1 + n + t asw + t ahw )t ? 45 ns t hawt1 <65> (n + t asw + t ahw )t ns wait hold time (from address) t hawt2 <66> n 1 (1 + n + t asw + t ahw )t ns caution set the following in accordan ce with the usage conditions of the cpu operating clock frequency (k = 0 to 3). ? 1/ f cpu < 60 ns set an address setup wait (aswk bit = 1). remarks 1. m = 0, 1 2. t asw : number of address setup wait clocks (0 or 1) t ahw : number of address hold wait clocks (0 or 1) 3. t = 1/f cpu (f cpu : cpu operating clock frequency) 4. n: number of wait clocks inserted in the bus cycle the sampling timing changes when a programmable wait is inserted. 5. the values in the above specifications are values for when clocks with a 1:1 duty ratio are input from x1. chapter 28 electrical specifications (target) preliminary user?s manual u17702ej1v0ud 807 (t a = ? 40 to +85 c, v dd = ev dd = av ref0 = 2.7 to 5.5 v, 2.7 v bv dd v dd , 2.7 v av ref1 v dd , v ss = ev ss = bv ss = av ss = 0 v, c l = 50 pf) (2/2) parameter symbol conditions min. max. unit address setup time (to wrm ) t sawr <52> (1 + t asw + t ahw )t ? 100 ns address hold time (from wrm ) t hawr <53> 0.5t ? 10 ns wrm low-level width t wwrl <54> (0.5 + n)t ? 10 ns delay time from wrm to data output t dosdw <55> ? 5 ns data setup time (to wrm ) t sosdw <56> (0.5 + n)t ? 35 ns data hold time (from wrm ) t hosdw <57> 0.5t ? 35 ns data setup time (to address) t saod <58> (1 + t asw + t ahw )t ? 55 ns t swrwt1 <59> 50 ns wait setup time (to wrm ) t swrwt2 <60> n 1 nt ? 50 ns t hwrwt1 <61> 0 ns wait hold time (from wrm ) t hwrwt2 <62> n 1 nt ns t sawt1 <63> (1 + t asw + t ahw )t ? 100 ns wait setup time (to address) t sawt2 <64> n 1 (1 + n + t asw + t ahw )t ? 100 ns t hawt1 <65> (n + t asw + t ahw )t ns wait hold time (from address) t hawt2 <66> n 1 (1 + n + t asw + t ahw )t ns caution set the following in accordan ce with the usage conditions of the cpu operating clock frequency (k = 0 to 3). ? 1/ f cpu < 100 ns set an address setup wait (aswk bit = 1). remarks 1. m = 0, 1 2. t asw : number of address setup wait clocks (0 or 1) t ahw : number of address hold wait clocks (0 or 1) 3. t = 1/f cpu (f cpu : cpu operating clock frequency) 4. n: number of wait clocks inserted in the bus cycle the sampling timing changes when a programmable wait is inserted. 5. the values in the above specifications are values for when clocks with a 1:1 duty ratio are input from x1. chapter 28 electrical specifications (target) preliminary user?s manual u17702ej1v0ud 808 write cycle (clkout asynchr onous): in separate bus mode clkout (output) t1 <58> <52> <55> <54> <62> <60> <61> <59> <63> <65> <64> <66> <57> <56> <53> tw t2 wr0, wr1 (output) cs0 to cs3 (output) a0 to a23 (output) ad0 to ad15 (i/o) wait (input) hi-z hi-z remark rd is high level. chapter 28 electrical specifications (target) preliminary user?s manual u17702ej1v0ud 809 (c) read cycle (clkout synch ronous): in separate bus mode (t a = ? 40 to +85 c, v dd = ev dd = av ref0 = 4.0 to 5.5 v, 4.0 v bv dd v dd , 4.0 v av ref1 v dd , v ss = ev ss = bv ss = av ss = 0 v, c l = 50 pf) (1/2) parameter symbol conditions min. max. unit delay time from clkout to address, cs t dksa <67> 0 35 ns data input setup time (to clkout ) t sisdk <68> 15 ns data input hold time (from clkout ) t hkisd <69> 0 ns delay time from clkout to rd t dksr <70> 0 6 ns wait setup time (to clkout ) t swtk <71> 20 ns wait hold time (from clkout ) t hkwt <72> 0 ns remark the values in the above specifications are values for when clocks with a 1:1 duty ratio are input from x1. (t a = ? 40 to +85 c, v dd = ev dd = av ref0 = 2.7 to 5.5 v, 2.7 v bv dd v dd , 2.7 v av ref1 v dd , v ss = ev ss = bv ss = av ss = 0 v, c l = 50 pf) (2/2) parameter symbol conditions min. max. unit delay time from clkout to address, cs t dksa <67> 0 65 ns data input setup time (to clkout ) t sisdk <68> 30 ns data input hold time (from clkout ) t hkisd <69> 0 ns delay time from clkout to rd t dksr <70> 0 10 ns wait setup time (to clkout ) t swtk <71> 40 ns wait hold time (from clkout ) t hkwt <72> 0 ns remark the values in the above specifications are values for when clocks with a 1:1 duty ratio are input from x1. chapter 28 electrical specifications (target) preliminary user?s manual u17702ej1v0ud 810 read cycle (clkout synchronous, 1 wait): in separate bus mode clkout (output) t1 <70> <71> <72> <71> <72> <67> <70> <68> <69> hi-z hi-z tw t2 rd (output) cs0 to cs3 (output) a0 to a23 (output) ad0 to ad15 (i/o) wait (input) <67> remark wr0 and wr1 are high level. chapter 28 electrical specifications (target) preliminary user?s manual u17702ej1v0ud 811 (d) write cycle (clkout synchr onous): in separate bus mode (t a = ? 40 to +85 c, v dd = ev dd = av ref0 = 4.0 to 5.5 v, 4.0 v bv dd v dd , 4.0 v av ref1 v dd , v ss = ev ss = bv ss = av ss = 0 v, c l = 50 pf) (1/2) parameter symbol conditions min. max. unit delay time from clkout to address, cs t dksa <73> 0 35 ns data output delay time from clkout t dksd <74> 0 10 ns delay time from clkout to wrm t dksw <75> 0 10 ns wait setup time (to clkout ) t swtk <76> 20 ns wait hold time (from clkout ) t hkwt <77> 0 ns remarks 1. m = 0, 1 2. the values in the above specifications are values for when clocks with a 1:1 duty ratio are input from x1. (t a = ? 40 to +85 c, v dd = ev dd = av ref0 = 2.7 to 5.5 v, 2.7 v bv dd v dd , 2.7 v av ref1 v dd , v ss = ev ss = bv ss = av ss = 0 v, c l = 50 pf) (2/2) parameter symbol conditions min. max. unit delay time from clkout to address, cs t dksa <73> 0 65 ns data output delay time from clkout t dksd <74> 0 15 ns delay time from clkout to wrm t dksw <75> 0 15 ns wait setup time (to clkout ) t swtk <76> 40 ns wait hold time (from clkout ) t hkwt <77> 0 ns remarks 1. m = 0, 1 2. the values in the above specifications are values for when clocks with a 1:1 duty ratio are input from x1. chapter 28 electrical specifications (target) preliminary user?s manual u17702ej1v0ud 812 write cycle (clkout synchronous ): in separate bus mode clkout (output) t1 <74> <75> <77> <76> <75> tw t2 wr0, wr1 (output) cs0 to cs3 (output) a0 to a23 (output) ad0 to ad15 (i/o) wait (input) <73> <73> <77> <76> <74> hi-z hi-z remark rd is high level. chapter 28 electrical specifications (target) preliminary user?s manual u17702ej1v0ud 813 (3) bus hold (a) clkout asynchronous (t a = ? 40 to +85 c, v dd = ev dd = av ref0 = 4.0 to 5.5 v, 4.0 v bv dd v dd , 4.0 v av ref1 v dd , v ss = ev ss = bv ss = av ss = 0 v, c l = 50 pf) (1/2) parameter symbol conditions min. max. unit hldrq high-level width t whqh <78> t + 10 ns hldak low-level width t whal <79> t ? 15 ns delay time from hldak to bus output t dhac <80> ? 40 ns delay time from hldrq to hldak t dhqha1 <81> (2n + 7.5)t + 40 ns delay time from hldrq to hldak t dhqha2 <82> 0.5t 1.5t + 40 ns remarks 1. t = 1/f cpu (f cpu : cpu operating clock frequency) 2. n: number of wait clocks inserted in the bus cycle the sampling timing changes when a programmable wait is inserted. 3. the values in the above specifications are values for when clocks with a 1:1 duty ratio are input from x1. (t a = ? 40 to +85 c, v dd = ev dd = av ref0 = 2.7 to 5.5 v, 2.7 v bv dd v dd , 2.7 v av ref1 v dd , v ss = ev ss = bv ss = av ss = 0 v, c l = 50 pf) (2/2) parameter symbol conditions min. max. unit hldrq high-level width t whqh <78> t + 10 ns hldak low-level width t whal <79> t ? 15 ns delay time from hldak to bus output t dhac <80> ? 80 ns delay time from hldrq to hldak t dhqha1 <81> (2n + 7.5)t + 70 ns delay time from hldrq to hldak t dhqha2 <82> 0.5t 1.5t + 70 ns remarks 1. t = 1/f cpu (f cpu : cpu operating clock frequency) 2. n: number of wait clocks inserted in the bus cycle the sampling timing changes when a programmable wait is inserted. 3. the values in the above specifications are values for when clocks with a 1:1 duty ratio are input from x1. chapter 28 electrical specifications (target) preliminary user?s manual u17702ej1v0ud 814 bus hold (clkout asynchronous) clkout (output) hldrq (input) hldak (output) address bus (output) data bus (i/o) th th th ti ti hi-z cs0 to cs3 (output) hi-z astb (output) rd (output), wr0 (output), wr1 (output) hi-z hi-z <78> <82> <79> <80> <81> chapter 28 electrical specifications (target) preliminary user?s manual u17702ej1v0ud 815 (b) clkout synchronous (t a = ? 40 to +85 c, v dd = ev dd = av ref0 = 4.0 to 5.5 v, 4.0 v bv dd v dd , 4.0 v av ref1 v dd , v ss = ev ss = bv ss = av ss = 0 v, c l = 50 pf) (1/2) parameter symbol conditions min. max. unit hldrq setup time (to clkout ) t shqk <83> 15 ns hldrq hold time (from clkout ) t hkhq <84> 0 ns delay time from clkout to bus float t dkf <85> 20 ns delay time from clkout to hldak t dkha <86> 20 ns remark the values in the above specifications are values for when clocks with a 1:1 duty ratio are input from x1. (t a = ? 40 to +85 c, v dd = ev dd = av ref0 = 2.7 to 5.5 v, 2.7 v bv dd v dd , 2.7 v av ref1 v dd , v ss = ev ss = bv ss = av ss = 0 v, c l = 50 pf) (2/2) parameter symbol conditions min. max. unit hldrq setup time (to clkout ) t shqk <83> 25 ns hldrq hold time (from clkout ) t hkhq <84> 0 ns delay time from clkout to bus float t dkf <85> 40 ns delay time from clkout to hldak t dkha <86> 40 ns remark the values in the above specifications are values for when clocks with a 1:1 duty ratio are input from x1. chapter 28 electrical specifications (target) preliminary user?s manual u17702ej1v0ud 816 bus hold (clkout synchronous) clkout (output) hldrq (input) hldak (output) address bus (output) data bus (i/o) th th th t2 t3 ti ti hi-z cs0 to cs3 (output) hi-z astb (output) rd (output), wr0 (output), wr1 (output) hi-z hi-z <83> <83> <86> <86> <84> <85> chapter 28 electrical specifications (target) preliminary user?s manual u17702ej1v0ud 817 basic operation (1) reset/external interrupt timing ( t a = ? 40 to +85 c, v dd = ev dd = av ref0 = 2.7 to 5.5 v, 2.7 v bv dd v dd , 2.7 v av ref1 v dd , v ss = ev ss = bv ss = av ss = 0 v, c l = 50 pf ) parameter symbol conditions min. max. unit t wrsl1 <87> reset in power-on status 2 s power-on reset when regc = v dd 2 s t vr > 150 s 10 s reset low-level width t wrsl2 <88> note t vr 150 s 40 s nmi high-level width t wnih <89> analog noise elimination 1 s nmi low-level width t wnil <90> analog noise elimination 1 s n = 0 to 7 (analog noise elimination) 600 ns intpn high-level width t with <91> n = 3 (when digital noise elimination selected) ni t ismp + 200 ns n = 0 to 7 (analog noise elimination) 600 ns intpn low-level width t witl <92> n = 3 (when digital noise elimination selected) ni t ismp + 200 ns regc = v dd = 4.0 to 5.5 v t + 50 ns v dd = 4.0 to 5.5 v, regc = 10 f t + 100 ns adtrg high-lvel width t wadh <93> regc = v dd = 2.7 to 5.5 v t + 100 ns regc = v dd = 4.0 to 5.5 v t + 50 ns v dd = 4.0 to 5.5 v, regc = 10 f t + 100 ns adtrg low-level width t wadl <94> regc = v dd = 2.7 to 5.5 v t + 100 ns note power-on reset when regc = 10 f remarks 1. t vr : time required for v dd to rise from 0 v to 4.0 v (= operation lower-limit voltage) ni: number of samplings set with the nfc.nfsts bit t ismp : digital noise elimination sa mpling clock cycle of intp3 pin t: a/d base clock cycle (f ad ) 2. the above specification shows the pulse width that is accurately detected as a valid edge. if a pulse narrower than the above specification is input, theref ore, it may also be detected as a valid edge. chapter 28 electrical specifications (target) preliminary user?s manual u17702ej1v0ud 818 reset/interrupt <88> <87> t vr v dd reset (input) nmi (input) intpn (input) adtrg (input) <89>/<91>/<93> <90>/<92>/<94> remark n = 0 to 7 chapter 28 electrical specifications (target) preliminary user?s manual u17702ej1v0ud 819 timer timing ( t a = ? 40 to +85 c, v dd = ev dd = av ref0 = 2.7 to 5.5 v, 2.7 v bv dd v dd , 2.7 v av ref1 v dd , v ss = ev ss = bv ss = av ss = 0 v, c l = 50 pf ) parameter symbol conditions min. max. unit regc = v dd = 4.5 to 5.5 v 2t smp0 + 100 note 1 ns ti0n high-level width t ti0h <95> regc = 10 f, v dd = 4.0 to 5.5 v, regc = v dd = 2.7 to 5.5 v 2t smp0 + 200 note 1 ns regc = v dd = 4.5 to 5.5 v 2t smp0 + 100 note 1 ns ti0n low-level width t ti0l <96> regc = 10 f, v dd = 4.0 to 5.5 v, regc = v dd = 2.7 to 5.5 v 2t smp0 + 200 note 1 ns regc = v dd = 4.5 to 5.5 v 50 ns ti5m high-level width t ti5h <97> regc = 10 f, v dd = 4.0 to 5.5 v, regc = v dd = 2.7 to 5.5 v 100 ns regc = v dd = 4.5 to 5.5 v 50 ns ti5m low-level width t ti5l <98> regc = 10 f, v dd = 4.0 to 5.5 v, regc = v dd = 2.7 to 5.5 v 100 ns regc = v dd = 4.5 to 5.5 v np t smpp + 100 note 2 ns tip0m high-level width t tiph <99> regc = 10 f, v dd = 4.0 to 5.5 v, regc = v dd = 2.7 to 5.5 v np t smpp + 200 note 2 ns regc = v dd = 4.5 to 5.5 v np t smpp + 100 note 2 ns tip0m low-level width t tipl <100> regc = 10 f, v dd = 4.0 to 5.5 v, regc = v dd = 2.7 to 5.5 v np t smpp + 200 note 2 ns notes 1. t smp0 : timer 0 count clock cycle however, t smp0 = 4/f xx when ti0n is used as an external clock. 2. np: number of sampling clocks set by the pmnfc.pmnfsts bit t smpp : digital noise elimination sa mpling clock cycle of tip0m pin if tip00 is used as an external clock or an external clear, however, t smpp = 0 (digital noise is not eliminated). remarks 1. n = 00, 01, 10, 11, 20, 21, 30, 31, 40, 41, 50, 51 m = 0, 1 2. the above specification shows the pul se width that is accurately detected as a valid edge. if a pulse narrower than the above specification is input, theref ore, it may also be detected as a valid edge. timer input timing ti0n (input) ti5m (input) tip0m (input) <95>/<97>/<99> <96>/<98>/<100> remark n = 00, 01, 10, 11, 20, 21, 30, 31, 40, 41, 50, 51 m = 0, 1 chapter 28 electrical specifications (target) preliminary user?s manual u17702ej1v0ud 820 uart timing (t a = ? 40 to +85 c, v dd = ev dd = av ref0 = 2.7 to 5.5 v, 2.7 v bv dd v dd , 2.7 v av ref1 v dd , v ss = ev ss = bv ss = av ss = 0 v, c l = 50 pf) parameter symbol conditions min. max. unit transmit rate 312.5 kbps regc = v dd = 4.5 to 5.5 v 12 mhz asck0 frequency regc = 10 f, v dd = 4.0 to 5.5 v, regc = v dd = 2.7 to 5.5 v 6 mhz chapter 28 electrical specifications (target) preliminary user?s manual u17702ej1v0ud 821 csi0 timing (1) master mode (t a = ? 40 to +85 c, v dd = ev dd = av ref0 = 2.7 to 5.5 v, 2.7 v bv dd v dd , 2.7 v av ref1 v dd , v ss = ev ss = bv ss = av ss = 0 v, c l = 50 pf) parameter symbol conditions min. max. unit regc = v dd = 4.0 to 5.5 v 200 ns sck0n cycle time t kcy1 <101> regc = 10 f, v dd = 4.0 to 5.5 v, regc = v dd = 2.7 to 5.5 v 400 ns sck0n high-/low-level width t kh1 , t kl1 <102> t kcy1 /2 ? 30 ns regc = v dd = 4.0 to 5.5 v 30 ns si0n setup time (to sck0n) t sik1 <103> regc = 10 f, v dd = 4.0 to 5.5 v, regc = v dd = 2.7 to 5.5 v 50 ns regc = v dd = 4.0 to 5.5 v 30 ns si0n hold time (from sck0n) t ksi1 <104> regc = 10 f, v dd = 4.0 to 5.5 v, regc = v dd = 2.7 to 5.5 v 50 ns regc = v dd = 4.0 to 5.5 v 30 ns delay time from sck0n to so0n output t kso1 <105> regc = 10 f, v dd = 4.0 to 5.5 v, regc = v dd = 2.7 to 5.5 v 60 ns remark n = 0 to 2 (2) slave mode (t a = ? 40 to +85 c, v dd = ev dd = av ref0 = 2.7 to 5.5 v, 2.7 v bv dd v dd , 2.7 v av ref1 v dd , v ss = ev ss = bv ss = av ss = 0 v, c l = 50 pf) parameter symbol conditions min. max. unit regc = v dd = 4.0 to 5.5 v 200 ns sck0n cycle time t kcy2 <101> regc = 10 f, v dd = 4.0 to 5.5 v, regc = v dd = 2.7 to 5.5 v 400 ns regc = v dd = 4.0 to 5.5 v 45 ns sck0n high-/low-level width t kh2 , t kl2 <102> regc = 10 f, v dd = 4.0 to 5.5 v, regc = v dd = 2.7 to 5.5 v 90 ns regc = v dd = 4.0 to 5.5 v 30 ns si0n setup time (to sck0n) t sik2 <103> regc = 10 f, v dd = 4.0 to 5.5 v, regc = v dd = 2.7 to 5.5 v 60 ns regc = v dd = 4.0 to 5.5 v 30 ns si0n hold time (from sck0n) t ksi2 <104> regc = 10 f, v dd = 4.0 to 5.5 v, regc = v dd = 2.7 to 5.5 v 60 ns regc = v dd = 4.0 to 5.5 v 50 ns delay time from sck0n to so0n output t kso2 <105> regc = 10 f, v dd = 4.0 to 5.5 v, regc = v dd = 2.7 to 5.5 v 100 ns remark n = 0 to 2 chapter 28 electrical specifications (target) preliminary user?s manual u17702ej1v0ud 822 (a) csicn.ckpn, dapn bits = 00 or 11 so0n (output) input data output data si0n (input) sck0n (i/o) <101> <102> <102> <103> <104> <105> hi-z hi-z (b) csicn.ckpn, dapn bits = 01 or 10 so0n (output) input data output data si0n (input) sck0n (i/o) <101> <102> <102> <103> <104> <105> hi-z hi-z remark n = 0 to 2 chapter 28 electrical specifications (target) preliminary user?s manual u17702ej1v0ud 823 csia timing (1) master mode (t a = ? 40 to +85 c, v dd = ev dd = av ref0 = 2.7 to 5.5 v, 2.7 v bv dd v dd , 2.7 v av ref1 v dd , v ss = ev ss = bv ss = av ss = 0 v, c l = 50 pf) parameter symbol conditions min. max. unit regc = v dd = 4.0 to 5.5 v 500 ns sckan cycle time t kcy3 <106> regc = 10 f, v dd = 4.0 to 5.5 v, regc = v dd = 2.7 to 5.5 v 1000 ns sckan high-/low-level width t kh3 , t kl3 <107> t kcy3 /2 ? 30 ns regc = v dd = 4.0 to 5.5 v 30 ns sian setup time (to sckan ) t sik3 <108> regc = 10 f, v dd = 4.0 to 5.5 v, regc = v dd = 2.7 to 5.5 v 60 ns regc = v dd = 4.0 to 5.5 v 30 ns sian hold time (from sckan ) t ksi3 <109> regc = 10 f, v dd = 4.0 to 5.5 v, regc = v dd = 2.7 to 5.5 v 60 ns regc = v dd = 4.0 to 5.5 v 30 ns delay time from sckan to soan output t kso3 <110> regc = 10 f, v dd = 4.0 to 5.5 v, regc = v dd = 2.7 to 5.5 v 60 ns remark n = 0, 1 (2) slave mode (t a = ? 40 to +85 c, v dd = ev dd = av ref0 = 2.7 to 5.5 v, 2.7 v bv dd v dd , 2.7 v av ref1 v dd , v ss = ev ss = bv ss = av ss = 0 v, c l = 50 pf) parameter symbol conditions min. max. unit regc = v dd = 4.0 to 5.5 v 840 ns sckan cycle time t kcy4 <106> regc = 10 f, v dd = 4.0 to 5.5 v, regc = v dd = 2.7 to 5.5 v 1700 ns sckan high-/low-level width t kh4 , t kl4 <107> t kcy4 /2 ? 30 ns regc = v dd = 4.0 to 5.5 v 50 ns sian setup time (to sckan ) t sik4 <108> regc = 10 f, v dd = 4.0 to 5.5 v, regc = v dd = 2.7 to 5.5 v 100 ns regc = v dd = 4.0 to 5.5 v t cy 2 + 15 note ns sian hold time (from sckan ) t ksi4 <109> regc = 10 f, v dd = 4.0 to 5.5 v, regc = v dd = 2.7 to 5.5 v t cy 2 + 30 note ns regc = v dd = 4.0 to 5.5 v t cy 2 + 30 note ns delay time from sckan to soan output t kso4 <110> regc = 10 f, v dd = 4.0 to 5.5 v, regc = v dd = 2.7 to 5.5 v t cy 2 + 60 note ns note t cy : f scka cycle remark n = 0, 1 chapter 28 electrical specifications (target) preliminary user?s manual u17702ej1v0ud 824 soan (output) input data output data sian (input) sckan (i/o) <106> <107> <107> <108> <109> <110> hi-z hi-z remark n = 0, 1 chapter 28 electrical specifications (target) preliminary user?s manual u17702ej1v0ud 825 i 2 c bus mode (t a = ? 40 to +85 c, v dd = ev dd = av ref0 = 2.7 to 5.5 v, 2.7 v bv dd v dd , 2.7 v av ref1 v dd , v ss = ev ss = bv ss = av ss = 0 v, c l = 50 pf) normal mode high-speed mode parameter symbol min. max. min. max. unit scln clock frequency f clk 0 100 0 400 khz bus free time (between start and stop conditions) t buf <111> 4.7 ? 1.3 ? s hold time note 1 t hd:sta <112> 4.0 ? 0.6 ? s scln clock low-level width t low <113> 4.7 ? 1.3 ? s scln clock high-level width t high <114> 4.0 ? 0.6 ? s setup time for start/restart conditions t su:sta <115> 4.7 ? 0.6 ? s cbus compatible master 5.0 ? ? ? s data hold time i 2 c mode t hd:dat <116> 0 note 2 ? 0 note 2 0.9 note 3 s data setup time t su:dat <117> 250 ? 100 note 4 ? ns sdan and scln signal rise time t r <118> ? 1000 20 + 0.1cb note 5 300 ns sdan and scln signal fall time t f <119> ? 300 20 + 0.1cb note 5 300 ns stop condition setup time t su:sto <120> 4.0 ? 0.6 ? s pulse width of spike suppressed by input filter t sp <121> ? ? 0 50 ns capacitance load of each bus line cb ? 400 ? 400 pf notes 1. at the start condition, the first clock pulse is generated after the hold time. 2. the system requires a minimum of 300 ns hold time internally for the sdan signal (at v ihmin. of scln signal) in order to occupy the undef ined area at the falling edge of scln. 3. if the system does not extend the scln signal low hold time (t low ), only the maximum data hold time (t hd : dat ) needs to be satisfied. 4. the high-speed mode i 2 c bus can be used in the normal-mode i 2 c bus system. in this case, set the high- speed mode i 2 c bus so that it meets the following conditions. ? if the system does not extend the scln signal?s low state hold time: t su : dat 250 ns ? if the system extends the scln signal?s low state hold time: transmit the following data bit to the sdan line prior to the scln line release (t rmax. + t su:dat = 1000 + 250 = 1250 ns: normal mode i 2 c bus specification). 5. cb: total capacitance of one bus line (unit: pf) remark n = 0, 1 chapter 28 electrical specifications (target) preliminary user?s manual u17702ej1v0ud 826 i 2 c bus mode stop condition start condition restart condition stop condition scln (i/o) sdan (i/o) <113> <119> <119> <118> <118> <116> <117> <115> <112> <111> <112> <121> <120> <114> remark n = 0, 1 chapter 28 electrical specifications (target) preliminary user?s manual u17702ej1v0ud 827 a/d converter (t a = ? 40 to +85 c, v dd = ev dd = av ref0 = 2.7 to 5.5 v, 2.7 v bv dd v dd , 2.7 v av ref1 v dd , v ss = ev ss = bv ss = av ss = 0 v) parameter symbol conditions min. typ. max. unit resolution 10 10 10 bit 4.0 av ref0 5.5 v 0.2 0.4 %fsr overall error note 1 ainl 2.7 av ref0 4.0 v 0.3 0.6 %fsr high-speed mode 3.0 100 s 4.5 av ref0 5.5 v normal mode 14.0 100 s high-speed mode 4.8 100 s 4.0 av ref0 4.5 v normal mode 14.0 100 s high-speed mode 6.0 100 s 2.85 av ref0 4.0 v normal mode 17.0 100 s high-speed mode 14.0 100 s conversion time t conv 2.7 av ref0 2.85 v normal mode 17.0 100 s 4.0 av ref0 5.5 v 0.4 %fsr zero-scale error note 1 ezs 2.7 av ref0 4.0 v 0.6 %fsr 4.0 av ref0 5.5 v 0.4 %fsr full-scale error note 1 efs 2.7 av ref0 4.0 v 0.6 %fsr 4.0 av ref0 5.5 v 2.5 lsb non-linearity error note 2 ile 2.7 av ref0 4.0 v 4.5 lsb 4.0 av ref0 5.5 v 1.5 lsb differential linearity error note 2 dle 2.7 av ref0 4.0 v 2.0 lsb analog input voltage v ian 0 av ref0 v when using a/d converter 1.3 2.5 ma av ref0 current ia ref0 when not using a/d converter note 3 1.0 10 a notes 1. excluding quantization error ( 0.05 %fsr). 2. excluding quantization error ( 0.5 lsb). 3. adm.adcs bit = 0, adm.adcs2 bit = 0 remark lsb: least significant bit fsr: full scale range chapter 28 electrical specifications (target) preliminary user?s manual u17702ej1v0ud 828 d/a converter (t a = ? 40 to +85 c, v dd = ev dd = av ref0 = 2.7 to 5.5 v, 2.7 v bv dd v dd , 2.7 v av ref1 v dd , v ss = ev ss = bv ss = av ss = 0 v) parameter symbol conditions min. typ. max. unit resolution 8 bit load condition = 2 m ? 1.2 %fsr load condition = 4 m ? 0.8 %fsr overall error notes 1, 2 load condition = 10 m ? 0.6 %fsr v dd = 4.5 to 5.5 v 10 s settling time note 2 c = 30 pf v dd = 2.7 to 4.5 v 15 s output resistance note 3 r o output data: dacsn register = 55h 8 k ? during d/a conversion 1.5 3.0 ma av ref1 current note 4 iav ref1 when d/a conversion stopped 1.0 10 a notes 1. excluding quantization error ( 0.2 %fsr). 2. r is the d/a converter output pin load resistance, and c is the d/a converter output pin load capacitance. 3. value of 1 channel of d/a converter 4. value of 2 channels of d/a converter remark n = 0, 1 chapter 28 electrical specifications (target) preliminary user?s manual u17702ej1v0ud 829 flash memory programming characteristics (t a = ? 40 to +85 c, v dd = ev dd = av ref0 = 2.7 to 5.5 v, 2.7 v bv dd v dd , 2.7 v av ref1 v dd , v ss = ev ss = bv ss = av ss = 0 v, c l = 50 pf) (1) basic characteristics parameter symbol conditions min. typ. max. unit regc = v dd = 4.5 to 5.5 v 2 20 mhz regc = v dd = 4.0 to 5.5 v 2 16 mhz regc = 10 f, v dd = 4.0 to 5.5 v 2 16 mhz programming operation frequency regc = v dd = 2.7 to 5.5 v 2 10 mhz supply voltage v dd 2.7 5.5 v number of rewrites c erwr note 1 100 times programming temperature t prg note 2 ? 40 +85 c notes 1. when writing initially to shipped products, it is c ounted as one rewrite for both ?e rase to write? and ?write only?. example (p: write, e: erase) shipped product p e p e p: 3 rewrites shipped product e p e p e p: 3 rewrites 2. these values may change after evaluation. (2) serial write operation characteristics parameter symbol conditions min. typ. max. unit setup time from v dd to flmd0 t dp <122> 10 ms 3 s time from reset to flmd0 pulse input start t rp <123> 66611.2/f x s flmd0 pulse high-/low-level width t pw <124> 10 100 s flmd0 pulse rise time t r <125> 50 ns flmd0 pulse fall time t f <126> 50 ns serial write operation timing v dd flmd0 flmd1 0 v <122> <124> <124> <123> reset <126> <125> preliminary user?s manual u17702ej1v0ud 830 chapter 29 package drawing 108 73 136 109 144 72 37 144-pin plastic lqfp (fine pitch) (20x20) item millimeters note a 22.0 0.2 b 20.0 0.2 c 20.0 0.2 d f 1.25 22.0 0.2 s144gj-50-uen s 1.5 0.1 k 1.0 0.2 l 0.5 0.2 r3 + 4 ? 3 g 1.25 h 0.22 0.05 i 0.08 j 0.5 (t.p.) m 0.17 n 0.08 p 1.4 q 0.10 0.05 + 0.03 ? 0.07 each lead centerline is located within 0.08 mm of its true position (t.p.) at maximum material condition. s s m detail of lead end i j f g h q r p k m l n cd s a b preliminary user?s manual u17702ej1v0ud 831 appendix a instruction set list a.1 conventions (1) register symbols u sed to describe operands register symbol explanation reg1 general-purpose registers: used as source registers. reg2 general-purpose registers: used mainly as destination registers. also used as source register in some instructions. reg3 general-purpose registers: used mainly to store the re mainders of division result s and the higher 32 bits of multiplication results. bit#3 3-bit data for specifying the bit number immx x bit immediate data dispx x bit displacement data regid system register number vector 5-bit data that specifies the trap vector (00h to 1fh) cccc 4-bit data that shows the condition codes sp stack pointer (r3) ep element pointer (r30) listx x item register list (2) register symbols used to describe opcodes register symbol explanation r 1-bit data of a code that specifies reg1 or regid r 1-bit data of the code that specifies reg2 w 1-bit data of the code that specifies reg3 d 1-bit displacement data i 1-bit immediate data (indicates th e higher bits of immediate data) i 1-bit immediate data cccc 4-bit data that shows the condition codes cccc 4-bit data that shows the condition codes of bcond instruction bbb 3-bit data for specifying the bit number l 1-bit data that specifies a program register in the register list appendix a instruction set list preliminary user?s manual u17702ej1v0ud 832 (3) register symbols used in operations register symbol explanation input for gr [ ] general-purpose register sr [ ] system register zero-extend (n) expand n with zeros until word length. sign-extend (n) expand n with signs until word length. load-memory (a, b) read size b data from address a. store-memory (a, b, c) write data b into address a in size c. load-memory-bit (a, b) read bit b of address a. store-memory-bit (a, b, c) write c to bit b of address a. saturated (n) execute saturated processing of n (n is a 2?s complement). if, as a result of calculations, n 7fffffffh, let it be 7fffffffh. n 80000000h, let it be 80000000h. result reflects the results in a flag. byte byte (8 bits) halfword halfword (16 bits) word word (32 bits) + addition ? subtraction ll bit concatenation multiplication division % remainder from division results and logical product or logical sum xor exclusive or not logical negation logically shift left by logical shift left logically shift right by logical shift right arithmetically shift right by arithmetic shift right (4) register symbols u sed in execution clock register symbol explanation i if executing another instruction immediately a fter executing the first instruction (issue). r if repeating execution of the same instruction immedi ately after executing the first instruction (repeat). l if using the results of instruction execution in the instruction immediately afte r the execution (latency). appendix a instruction set list preliminary user?s manual u17702ej1v0ud 833 (5) register symbols used in flag operations identifier explanation (blank) no change 0 clear to 0 x set or cleared in accordance with the results. r previously saved values are restored. (6) condition codes condition code (cccc) condition formula explanation 0 0 0 0 ov = 1 overflow 1 0 0 0 ov = 0 no overflow 0 0 0 1 cy = 1 carry lower (less than) 1 0 0 1 cy = 0 no carry not lower (greater than or equal) 0 0 1 0 z = 1 zero 1 0 1 0 z = 0 not zero 0 0 1 1 (cy or z) = 1 not higher (less than or equal) 1 0 1 1 (cy or z) = 0 higher (greater than) 0 1 0 0 s = 1 negative 1 1 0 0 s = 0 positive 0 1 0 1 ? always (unconditional) 1 1 0 1 sat = 1 saturated 0 1 1 0 (s xor ov) = 1 less than signed 1 1 1 0 (s xor ov) = 0 greater than or equal signed 0 1 1 1 ((s xor ov) or z) = 1 less than or equal signed 1 1 1 1 ((s xor ov) or z) = 0 greater than signed appendix a instruction set list preliminary user?s manual u17702ej1v0ud 834 a.2 instruction set (in alphabetical order) (1/6) execution clock flags mnemonic operand opcode operation i r l cy ov s z sat reg1,reg2 r r rr r0 01 11 0 rrrrr gr[reg2] gr[reg2]+gr[reg1] 1 1 1 add imm5,reg2 rrrrr010010iiiii gr[reg2] gr[reg2]+sign-extend(imm5) 1 1 1 addi imm16,reg1,reg2 r r rr r1 10 00 0 rrrrr iiiiiiiiiiiiiiii gr[reg2] gr[reg1]+sign-extend(imm16) 1 1 1 and reg1,reg2 r r rr r0 01 01 0 rrrrr gr[reg2] gr[reg2]and gr[reg1] 1 1 1 0 andi imm16,reg1,reg2 r r rr r1 10 11 0 rrrrr iiiiiiiiiiiiiiii gr[reg2] gr[reg1]and zero-extend(imm16) 1 1 1 0 when conditions are satisfied 2 note 2 2 note 2 2 note 2 bcond disp9 ddddd1011dddcccc note 1 if conditions are satisfied then pc pc+sign-extend(disp9) when conditions are not satisfied 1 1 1 bsh reg2,reg3 r r r r r 1 1 1 1 1 1 0 0 0 0 0 wwwww01101000010 gr[reg3] gr[reg2] (23 : 16) ll gr[reg2] (31 : 24) ll gr[reg2] (7 : 0) ll gr[reg2] (15 : 8) 1 1 1 0 bsw reg2,reg3 r r r r r 1 1 1 1 1 1 0 0 0 0 0 wwwww01101000000 gr[reg3] gr[reg2] (7 : 0) ll gr[reg2] (15 : 8) ll gr [reg2] (23 : 16) ll gr[reg2] (31 : 24) 1 1 1 0 callt imm6 0000001000iiiiii ctpc pc+2(return pc) ctpsw psw adr ctbp+zero-extend(imm6 logically shift left by 1) pc ctbp+zero-extend(load-memory(adr,halfword)) 4 4 4 bit#3,disp16[reg1] 10bbb111110rrrrr dddddddddddddddd adr gr[reg1]+sign-extend(disp16) z flag not(load-memory-bit(adr,bit#3)) store-memory-bit(adr,bit#3,0) 3 note 3 3 note 3 3 note 3 clr1 reg2,[reg1] r r rr r1 11 11 1 rrrrr 0000000011100100 adr gr[reg1] z flag not(load-memory-bit(adr,reg2)) store-memory-bit(adr,reg2,0) 3 note 3 3 note 3 3 note 3 cccc,imm5,reg2,reg3 rrrrr111111iiiii wwwww011000cccc0 if conditions are satisfied then gr[reg3] sign-extended(imm5) else gr[reg3] gr[reg2] 1 1 1 cmov cccc,reg1,reg2,reg3 r r r r r 1 1 1 1 1 1 r r r r wwwww011001cccc0 if conditions are satisfied then gr[reg3] gr[reg1] else gr[reg3] gr[reg2] 1 1 1 reg1,reg2 r r rr r0 01 11 1 rrrrr result gr[reg2]?gr[reg1] 1 1 1 cmp imm5,reg2 rrrrr010011iiiii result gr[reg2]?sign-extend(imm5) 1 1 1 ctret 0000011111100000 0000000101000100 pc ctpc psw ctpsw 3 3 3 r r r r r dbret 0000011111100000 0000000101000110 pc dbpc psw dbpsw 3 3 3 r r r r r appendix a instruction set list preliminary user?s manual u17702ej1v0ud 835 (2/6) execution clock flags mnemonic operand opcode operation i r l cy ov s z sat dbtrap 1111100001000000 dbpc pc+2 (restored pc) dbpsw psw psw.np 1 psw.ep 1 psw.id 1 pc 00000060h 3 3 3 di 0000011111100000 0000000101100000 psw.id 1 1 1 1 imm5,list12 0000011001iiiiil lllllllllll00000 sp sp+zero-extend(imm5 logically shift left by 2) gr[reg in list12] load-memory(sp,word) sp sp+4 repeat 2 steps above until all regs in list12 is loaded n+1 note 4 n+1 note 4 n+1 note 4 dispose imm5,list12,[reg1] 0 0 0 0 0 1 1 0 0 1 i i i i i l lllllllllllrrrrr note 5 sp sp+zero-extend(imm5 logically shift left by 2) gr[reg in list12] load-memory(sp,word) sp sp+4 repeat 2 steps above until all regs in list12 is loaded pc gr[reg1] n+3 note 4 n+3 note 4 n+3 note 4 div reg1,reg2,reg3 r r rr r1 11 11 1 rrrrr wwwww01011000000 gr[reg2] gr[reg2]gr[reg1] gr[reg3] gr[reg2]%gr[reg1] 35 35 35 reg1,reg2 r r rr r0 00 01 0 rrrrr gr[reg2] gr[reg2]gr[reg1] note 6 35 35 35 divh reg1,reg2,reg3 r r rr r1 11 11 1 rrrrr wwwww01010000000 gr[reg2] gr[reg2]gr[reg1] note 6 gr[reg3] gr[reg2]%gr[reg1] 35 35 35 divhu reg1,reg2,reg3 r r rr r1 11 11 1 rrrrr wwwww01010000010 gr[reg2] gr[reg2]gr[reg1] note 6 gr[reg3] gr[reg2]%gr[reg1] 34 34 34 divu reg1,reg2,reg3 r r rr r1 11 11 1 rrrrr wwwww01011000010 gr[reg2] gr[reg2]gr[reg1] gr[reg3] gr[reg2]%gr[reg1] 34 34 34 ei 1000011111100000 0000000101100000 psw.id 0 1 1 1 halt 0000011111100000 0000000100100000 stop 1 1 1 hsw reg2,reg3 r r r r r 1 1 1 1 1 1 0 0 0 0 0 wwwww01101000100 gr[reg3] gr[reg2](15 : 0) ll gr[reg2] (31 : 16) 1 1 1 0 jarl disp22,reg2 r r r r r 1 1 1 1 0 d d d d d d ddddddddddddddd0 note 7 gr[reg2] pc+4 pc pc+sign-extend(disp22) 2 2 2 jmp [reg1] 00000000011rrrrr pc gr[reg1] 3 3 3 jr disp22 0000011110dddddd ddddddddddddddd0 note 7 pc pc+sign-extend(disp22) 2 2 2 ld.b disp16[reg1],reg2 r r rr r1 11 00 0 rrrrr dddddddddddddddd adr gr[reg1]+sign-extend(disp16) gr[reg2] sign-extend(load-memory(adr,byte)) 1 1 note 11 ld.bu disp16[reg1],reg2 r r rr r1 11 10 b rrrrr dddddddddddddd1 notes 8, 10 adr gr[reg1]+sign-extend(disp16) gr[reg2] zero-extend(load-memory(adr,byte)) 1 1 note 11 appendix a instruction set list preliminary user?s manual u17702ej1v0ud 836 (3/6) execution clock flags mnemonic operand opcode operation i r l cy ov s z sat ld.h disp16[reg1],reg2 rrrrr111001rrrrr ddddddddddddddd0 note 8 adr gr[reg1]+sign-extend(disp16) gr[reg2] sign-extend(load-memory(adr,halfword)) 1 1 note 11 other than regid = psw 1 1 1 ldsr reg2,regid rrrrr111111rrrrr 0000000000100000 note 12 sr[regid] gr[reg2] regid = psw 1 1 1 ld.hu disp16[reg1],reg2 r r rr r1 11 11 1 rrrrr ddddddddddddddd1 note 8 adr gr[reg1]+sign-extend(disp16) gr[reg2] zero-extend(load-memory(adr,halfword) 1 1 note 11 ld.w disp16[reg1],reg2 r r rr r1 11 00 1 rrrrr ddddddddddddddd1 note 8 adr gr[reg1]+sign-extend(disp16) gr[reg2] load-memory(adr,word) 1 1 note 11 reg1,reg2 r r rr r0 00 00 0 rrrrr gr[reg2] gr[reg1] 1 1 1 imm5,reg2 rrrrr010000iiiii gr[reg2] sign-extend(imm5) 1 1 1 mov imm32,reg1 00000110001rrrrr iiiiiiiiiiiiiiii iiiiiiiiiiiiiiii gr[reg1] imm32 2 2 2 movea imm16,reg1,reg2 r r rr r1 10 00 1 rrrrr iiiiiiiiiiiiiiii gr[reg2] gr[reg1]+sign-extend(imm16) 1 1 1 movhi imm16,reg1,reg2 r r rr r1 10 01 0 rrrrr iiiiiiiiiiiiiiii gr[reg2] gr[reg1]+(imm16 ll 0 16 ) 1 1 1 reg1,reg2,reg3 r r rr r1 11 11 1 rrrrr wwwww01000100000 gr[reg3] ll gr[reg2] gr[reg2]xgr[reg1] note 14 1 4 5 mul imm9,reg2,reg3 rrrrr111111iiiii wwwww01001iiii00 note 13 gr[reg3] ll gr[reg2] gr[reg2]xsign-extend(imm9) 1 4 5 reg1,reg2 r r rr r0 00 11 1 rrrrr gr[reg2] gr[reg2] note 6 xgr[reg1] note 6 1 1 2 mulh imm5,reg2 rrrrr010111iiiii gr[reg2] gr[reg2] note 6 xsign-extend(imm5) 1 1 2 mulhi imm16,reg1,reg2 r r rr r1 10 11 1 rrrrr iiiiiiiiiiiiiiii gr[reg2] gr[reg1] note 6 ximm16 1 1 2 reg1,reg2,reg3 r r rr r1 11 11 1 rrrrr wwwww01000100010 gr[reg3] ll gr[reg2] gr[reg2]xgr[reg1] note 14 1 4 5 mulu imm9,reg2,reg3 rrrrr111111iiiii wwwww01001iiii10 note 13 gr[reg3] ll gr[reg2] gr[reg2]xzero-extend(imm9) 1 4 5 nop 0000000000000000 pass at least one clock cycle doing nothing. 1 1 1 not reg1,reg2 r r rr r0 00 00 1 rrrrr gr[reg2] not(gr[reg1]) 1 1 1 0 bit#3,disp16[reg1] 01bbb111110rrrrr dddddddddddddddd adr gr[reg1]+sign-extend(disp16) z flag not(load-memory-bit(adr,bit#3)) store-memory-bit(adr,bit#3,z flag) 3 note 3 3 note 3 3 note 3 not1 reg2,[reg1] r r rr r1 11 11 1 rrrrr 0000000011100010 adr gr[reg1] z flag not(load-memory-bit(adr,reg2)) store-memory-bit(adr,reg2,z flag) 3 note 3 3 note 3 3 note 3 appendix a instruction set list preliminary user?s manual u17702ej1v0ud 837 (4/6) execution clock flags mnemonic operand opcode operation i r l cy ov s z sat or reg1,reg2 r r rr r0 01 00 0 rrrrr gr[reg2] gr[reg2]or gr[reg1] 1 1 1 0 ori imm16,reg1,reg2 r r rr r1 10 10 0 rrrrr iiiiiiiiiiiiiiii gr[reg2] gr[reg1]or zero-extend(imm16) 1 1 1 0 list12,imm5 0000011110iiiiil lllllllllll00001 store-memory(sp?4,gr[reg in list12],word) sp sp?4 repeat 1 step above until all regs in list12 is stored sp sp-zero-extend(imm5) n+1 note 4 n+1 note 4 n+1 note 4 prepare list12,imm5, sp/imm note 15 0000011110iiiiil lllllllllllff011 imm16/imm32 note 16 store-memory(sp?4,gr[reg in list12],word) sp sp+4 repeat 1 step above until all regs in list12 is stored sp sp-zero-extend (imm5) ep sp/imm n+2 note 4 note 17 n+2 note 4 note 17 n+2 note 4 note 17 reti 0000011111100000 0000000101000000 if psw.ep=1 then pc eipc psw eipsw else if psw.np=1 then pc fepc psw fepsw else pc eipc psw eipsw 3 3 3 r r r r r reg1,reg2 r r rr r1 11 11 1 rrrrr 0000000010100000 gr[reg2] gr[reg2]arithmetically shift right by gr[reg1] 1 1 1 0 sar imm5,reg2 rrrrr010101iiiii gr[reg2] gr[reg2]arithmetically shift right by zero-extend (imm5) 1 1 1 0 sasf cccc,reg2 rrrrr1111110cccc 0000001000000000 if conditions are satisfied then gr[reg2] (gr[reg2]logically shift left by 1) or 00000001h else gr[reg2] (gr[reg2]logically shift left by 1) or 00000000h 1 1 1 reg1,reg2 r r rr r0 00 11 0 rrrrr gr[reg2] saturated(gr[reg2]+gr[reg1]) 1 1 1 satadd imm5,reg2 rrrrr010001iiiii gr[reg2] saturated(gr[reg2]+sign-extend(imm5)) 1 1 1 satsub reg1,reg2 r r rr r0 00 10 1 rrrrr gr[reg2] saturated(gr[reg2]?gr[reg1]) 1 1 1 satsubi imm16,reg1,reg2 r r rr r1 10 01 1 rrrrr iiiiiiiiiiiiiiii gr[reg2] saturated(gr[reg1]?sign-extend(imm16)) 1 1 1 satsubr reg1,reg2 r r rr r0 00 10 0 rrrrr gr[reg2] saturated(gr[reg1]?gr[reg2]) 1 1 1 setf cccc,reg2 rrrrr1111110cccc 0000000000000000 if conditions are satisfied then gr[reg2] 00000001h else gr[reg2] 00000000h 1 1 1 appendix a instruction set list preliminary user?s manual u17702ej1v0ud 838 (5/6) execution clock flags mnemonic operand opcode operation i r l cy ov s z sat bit#3,disp16[reg1] 00bbb111110rrrrr dddddddddddddddd adr gr[reg1]+sign-extend(disp16) z flag not (load-memory-bit(adr,bit#3)) store-memory-bit(adr,bit#3,1) 3 note 3 3 note 3 3 note 3 set1 reg2,[reg1] r r rr r1 11 11 1 rrrrr 0000000011100000 adr gr[reg1] z flag not(load-memory-bit(adr,reg2)) store-memory-bit(adr,reg2,1) 3 note 3 3 note 3 3 note 3 reg1,reg2 r r rr r1 11 11 1 rrrrr 0000000011000000 gr[reg2] gr[reg2] logically shift left by gr[reg1] 1 1 1 0 shl imm5,reg2 rrrrr010110iiiii gr[reg2] gr[reg2] logically shift left by zero-extend(imm5) 1 1 1 0 reg1,reg2 r r rr r1 11 11 1 rrrrr 0000000010000000 gr[reg2] gr[reg2] logically shift right by gr[reg1] 1 1 1 0 shr imm5,reg2 rrrrr010100iiiii gr[reg2] gr[reg2] logically shift right by zero-extend(imm5) 1 1 1 0 sld.b disp7[ep],reg2 r r r r r 0 1 1 0 d d d d d d d adr ep+zero-extend(disp7) gr[reg2] sign-extend(load-memory(adr,byte)) 1 1 note 9 sld.bu disp4[ep],reg2 rrrrr0000110dddd note 18 adr ep+zero-extend(disp4) gr[reg2] zero-extend(load-memory(adr,byte)) 1 1 note 9 sld.h disp8[ep],reg2 r r r r r 1 0 0 0 d d d d d d d note 19 adr ep+zero-extend(disp8) gr[reg2] sign-extend(load-memory(adr,halfword)) 1 1 note 9 sld.hu disp5[ep],reg2 rrrrr0000111dddd notes 18, 20 adr ep+zero-extend(disp5) gr[reg2] zero-extend(load-memory(adr,halfword)) 1 1 note 9 sld.w disp8[ep],reg2 rrrrr1010dddddd0 note 21 adr ep+zero-extend(disp8) gr[reg2] load-memory(adr,word) 1 1 note 9 sst.b reg2,disp7[ep] r r r r r 0 1 1 1 d d d d d d d adr ep+zero-extend(disp7) store-memory(adr,gr[reg2],byte) 1 1 1 sst.h reg2,disp8[ep] r r r r r 1 0 0 1 d d d d d d d note 19 adr ep+zero-extend(disp8) store-memory(adr,gr[reg2],halfword) 1 1 1 sst.w reg2,disp8[ep] rrrrr1010dddddd1 note 21 adr ep+zero-extend(disp8) store-memory(adr,gr[reg2],word) 1 1 1 st.b reg2,disp16[reg1] r r rr r1 11 01 0 rrrrr dddddddddddddddd adr gr[reg1]+sign-extend(disp16) store-memory(adr,gr[reg2],byte) 1 1 1 st.h reg2,disp16[reg1] r r rr r1 11 01 1 rrrrr ddddddddddddddd0 note 8 adr gr[reg1]+sign-extend(disp16) store-memory (adr,gr[reg2], halfword) 1 1 1 st.w reg2,disp16[reg1] rrrrr111011rrrrr ddddddddddddddd1 note 8 adr gr[reg1]+sign-extend(disp16) store-memory (adr,gr[reg2], word) 1 1 1 stsr regid,reg2 r r rr r1 11 11 1 rrrrr 0000000001000000 gr[reg2] sr[regid] 1 1 1 appendix a instruction set list preliminary user?s manual u17702ej1v0ud 839 (6/6) execution clock flags mnemonic operand opcode operation i r l cy ov s z sat sub reg1,reg2 r r rr r0 01 10 1 rrrrr gr[reg2] gr[reg2]?gr[reg1] 1 1 1 subr reg1,reg2 r r rr r0 01 10 0 rrrrr gr[reg2] gr[reg1]?gr[reg2] 1 1 1 switch reg1 00000000010rrrrr adr (pc+2) + (gr [reg1] logically shift left by 1) pc (pc+2) + (sign-extend (load-memory (adr,halfword)) logically shift left by 1 5 5 5 sxb reg1 00000000101rrrrr gr[reg1] sign-extend (gr[reg1] (7 : 0)) 1 1 1 sxh reg1 00000000111rrrrr gr[reg1] sign-extend (gr[reg1] (15 : 0)) 1 1 1 trap vector 00000111111iiiii 0000000100000000 eipc pc+4 (restored pc) eipsw psw ecr.eicc interrupt code psw.ep 1 psw.id 1 pc 00000040h (when vector is 00h to 0fh) 00000050h (when vector is 10h to 1fh) 3 3 3 tst reg1,reg2 r r rr r0 01 01 1 rrrrr result gr[reg2] and gr[reg1] 1 1 1 0 bit#3,disp16[reg1] 11bbb111110rrrrr dddddddddddddddd adr gr[reg1]+sign-extend(disp16) z flag not (load-memory-bit (adr,bit#3)) 3 note 3 3 note 3 3 note 3 tst1 reg2, [reg1] r r rr r1 11 11 1 rrrrr 0000000011100110 adr gr[reg1] z flag not (load-memory-bit (adr,reg2)) 3 note 3 3 note 3 3 note 3 xor reg1,reg2 r r rr r0 01 00 1 rrrrr gr[reg2] gr[reg2] xor gr[reg1] 1 1 1 0 xori imm16,reg1,reg2 r r rr r1 10 10 1 rrrrr iiiiiiiiiiiiiiii gr[reg2] gr[reg1] xor zero-extend (imm16) 1 1 1 0 zxb reg1 00000000100rrrrr gr[reg1] zero-extend (gr[reg1] (7 : 0)) 1 1 1 zxh reg1 00000000110rrrrr gr[reg1] zero-extend (gr[reg1] (15 : 0)) 1 1 1 notes 1. dddddddd: higher 8 bits of disp9. 2. 3 if there is an instruction that rewrites the contents of the psw immediately before. 3. if there is no wait state (3 + the number of read access wait states). 4. n is the total number of list12 load registers. (a ccording to the number of wait states. also, if there are no wait states, n is the total number of list12 registers. if n = 0, same operation as when n = 1) 5. rrrrr: other than 00000. 6. the lower halfword data only are valid. 7. ddddddddddddddddddddd: the higher 21 bits of disp22. 8. ddddddddddddddd: the higher 15 bits of disp16. 9. according to the number of wait stat es (1 if there are no wait states). 10. b: bit 0 of disp16. 11. according to the number of wait stat es (2 if there are no wait states). appendix a instruction set list preliminary user?s manual u17702ej1v0ud 840 notes 12. in this instruction, for convenience of mnemonic descr iption, the source register is made reg2, but the reg1 field is used in the opcode. therefore, the m eaning of register specific ation in the mnemonic description and in the opcode differs from other instructions. rrrrr = regid specification rrrrr = reg2 specification 13. iiiii: lower 5 bits of imm9. iiii: higher 4 bits of imm9. 14. do not specify the same register fo r general-purpose registers reg1 and reg3. 15. sp/imm: specified by bits 19 and 20 of the sub-opcode. 16. ff = 00: load sp in ep. 01: load sign expanded 16-bit immediate data (bits 47 to 32) in ep. 10: load 16-bit logically left shifted 16-bit immediate data (bits 47 to 32) in ep. 11: load 32-bit immediate data (bits 63 to 32) in ep. 17. if imm = imm32, n + 3 clocks. 18. rrrrr: other than 00 000. 19. ddddddd: higher 7 bits of disp8. 20. dddd: higher 4 bits of disp5. 21. dddddd: higher 6 bits of disp8. preliminary user?s manual u17702ej1v0ud 841 appendix b register index (1/10) symbol name unit page adcr a/d conversion result register adc 464 adcrh a/d conversion result register h adc 464 adic interrupt control register intc 697 adm a/d converter mode register adc 460 ads analog input channel specification register adc 463 adtc0 automatic data transfer address count register 0 csia 552 adtc1 automatic data transfer address count register 1 csia 552 adti0 automatic data transfer interval specification register 0 csia 558 adti1 automatic data transfer interval specification register 1 csia 558 adtp0 automatic data transfer address point specification register 0 csia 556 adtp1 automatic data transfer address point specification register 1 csia 556 asif0 asynchronous serial interface tr ansmit status register 0 uart 498 asif1 asynchronous serial interface tr ansmit status register 1 uart 498 asif2 asynchronous serial interface tr ansmit status register 2 uart 498 asim0 asynchronous serial interface mode register 0 uart 495 asim1 asynchronous serial interface mode register 1 uart 495 asim2 asynchronous serial interface mode register 2 uart 495 asis0 asynchronous serial interface status register 0 uart 497 asis1 asynchronous serial interface status register 1 uart 497 asis2 asynchronous serial interface status register 2 uart 497 awc address wait control register bcu 200 bcc bus cycle control register bcu 201 brgc0 baud rate generator control register 0 uart 516 brgc1 baud rate generator control register 1 uart 516 brgc2 baud rate generator control register 2 uart 516 brgca0 divisor selection register 0 csia 556 brgca1 divisor selection register 1 csia 556 brgic interrupt control register intc 697 bsc bus size configuration register bcu 189 cksr0 clock select register 0 uart 515 cksr1 clock select register 1 uart 515 cksr2 clock select register 2 uart 515 cmp00 8-bit timer h compare register 00 tmh 405 cmp01 8-bit timer h compare register 01 tmh 406 cmp10 8-bit timer h compare register 10 tmh 405 cmp11 8-bit timer h compare register 11 tmh 406 cr000 16-bit timer capture/compare register 000 tm0 312 cr001 16-bit timer capture/compare register 001 tm0 312 cr010 16-bit timer capture/compare register 010 tm0 312 cr011 16-bit timer capture/compare register 011 tm0 312 cr020 16-bit timer capture/compare register 020 tm0 312 appendix b register index preliminary user?s manual u17702ej1v0ud 842 (2/10) symbol name unit page cr021 16-bit timer capture/compare register 021 tm0 312 cr030 16-bit timer capture/compare register 030 tm0 312 cr031 16-bit timer capture/compare register 031 tm0 312 cr040 16-bit timer capture/compare register 040 tm0 312 cr041 16-bit timer capture/compare register 041 tm0 312 cr050 16-bit timer capture/compare register 050 tm0 312 cr051 16-bit timer capture/compare register 051 tm0 312 cr5 16-bit timer compare register 5 tm5 385 cr50 8-bit timer compare register 50 tm5 387 cr51 8-bit timer compare register 51 tm5 387 crc00 capture/compare control register 00 tm0 318 crc01 capture/compare control register 01 tm0 318 crc02 capture/compare control register 02 tm0 318 crc03 capture/compare control register 03 tm0 318 crc04 capture/compare control register 04 tm0 318 crc05 capture/compare control register 05 tm0 318 csi0ic0 interrupt control register intc 697 csi0ic1 interrupt control register intc 697 csi0ic2 interrupt control register intc 697 csia0b0 csia0 buffer ramn (n = 0 to f) csia 558 csia0b0h csia0 buffer ramnh (n = 0 to f) csia 558 csia0b0l csia0 buffer ramnl (n = 0 to f) csia 558 csia1b0 csia1 buffer ramn (n = 0 to f) csia 558 csia1b0h csia1 buffer ramnh (n = 0 to f) csia 558 csia1b0l csia1 buffer ramnl (n = 0 to f) csia 558 csiaic0 interrupt control register intc 697 csiaic1 interrupt control register intc 697 csic0 clocked serial interface cl ock selection register 0 csi0 528 csic1 clocked serial interface cl ock selection register 1 csi0 528 csic2 clocked serial interface cl ock selection register 2 csi0 528 csim00 clocked serial interfac e mode register 00 csi0 526 csim01 clocked serial interfac e mode register 01 csi0 526 csim02 clocked serial interfac e mode register 02 csi0 526 csima0 serial operation mode specification register 0 csi0 553 csima1 serial operation mode specification register 1 csi0 553 csis0 serial status register 0 csi0 554 csis1 serial status register 1 csi0 554 csit0 serial trigger register 0 csi0 555 csit1 serial trigger register 1 csi0 555 ctbp callt base pointer cpu 50 ctpc callt execution status saving register cpu 49 ctpsw callt execution status saving register cpu 49 dacs0 d/a conversion value setting register 0 dac 486 dacs1 d/a conversion value setting register 1 dac 486 appendix b register index preliminary user?s manual u17702ej1v0ud 843 (3/10) symbol name unit page dadc0 dma addressing control register 0 dma 662 dadc1 dma addressing control register 1 dma 662 dadc2 dma addressing control register 2 dma 662 dadc3 dma addressing control register 3 dma 662 dam d/a converter mode register dac 486 dbc0 dma byte count register 0 dma 661 dbc1 dma byte count register 1 dma 661 dbc2 dma byte count register 2 dma 661 dbc3 dma byte count register 3 dma 661 dbpc exception/debug trap status saving register cpu 50 dbpsw exception/debug trap status saving register cpu 50 dchc0 dma channel control register 0 dma 663 dchc1 dma channel control register 1 dma 663 dchc2 dma channel control register 2 dma 663 dchc3 dma channel control register 3 dma 663 dda0h dma destination address register 0h dma 660 dda0l dma destination address register 0l dma 660 dda1h dma destination address register 1h dma 660 dda1l dma destination address register 1l dma 660 dda2h dma destination address register 2h dma 660 dda2l dma destination address register 2l dma 660 dda3h dma destination address register 3h dma 660 dda3l dma destination address register 3l dma 660 dmaic0 interrupt control register intc 697 dmaic1 interrupt control register intc 697 dmaic2 interrupt control register intc 697 dmaic3 interrupt control register intc 697 dsa0h dma source address register 0h dma 659 dsa0l dma source address register 0l dma 659 dsa1h dma source address register 1h dma 659 dsa1l dma source address register 1l dma 659 dsa2h dma source address register 2h dma 659 dsa2l dma source address register 2l dma 659 dsa3h dma source address register 3h dma 659 dsa3l dma source address register 3l dma 659 dtfr0 dma trigger factor register 0 dma 664 dtfr1 dma trigger factor register 1 dma 664 dtfr2 dma trigger factor register 2 dma 664 dtfr3 dma trigger factor register 3 dma 664 dwc0 data wait control register 0 bcu 197 ecr interrupt source register cpu 47 eipc interrupt status saving register cpu 46 eipsw interrupt status saving register cpu 46 eximc external bus interface mode control register bcu 188 appendix b register index preliminary user?s manual u17702ej1v0ud 844 (4/10) symbol name unit page fepc nmi status saving register cpu 47 fepsw nmi status saving register cpu 47 iic0 iic shift register 0 i 2 c 600 iic1 iic shift register 1 i 2 c 600 iicc0 iic control register 0 i 2 c 587 iicc1 iic control register 1 i 2 c 587 iiccl0 iic clock selection register 0 i 2 c 597 iiccl1 iic clock selection register 1 i 2 c 597 iicf0 iic flag register 0 i 2 c 595 iicf1 iic flag register 1 i 2 c 595 iicic0 interrupt control register intc 697 iicic1 interrupt control register intc 697 iics0 iic status register 0 i 2 c 592 iics1 iic status register 1 i 2 c 592 iicx0 iic function expansion register 0 i 2 c 598 iicx1 iic function expansion register 1 i 2 c 598 imr0 interrupt mask register 0 intc 700 imr0h interrupt mask register 0h intc 700 imr0l interrupt mask register 0l intc 700 imr1 interrupt mask register 1 intc 700 imr1h interrupt mask register 1h intc 700 imr1l interrupt mask register 1l intc 700 imr2 interrupt mask register 2 intc 700 imr2h interrupt mask register 2h intc 700 imr2l interrupt mask register 2l intc 700 imr3 interrupt mask register 3 intc 700 imr3h interrupt mask register 3h intc 700 imr3l interrupt mask register 3l intc 700 intf0 external interrupt falling edge specification register 0 intc 708 intf3 external interrupt falling edge specification register 3 intc 709 intf9h external interrupt falling edge specification register 9h intc 710 intr0 external interrupt rising edge specification register 0 intc 708 intr3 external interrupt rising edge specification register 3 intc 709 intr9h external interrupt rising edge specification register 9h intc 710 ispr in-service priority register intc 702 kric interrupt control register intc 697 krm key return mode register kr 723 nfc digital noise elimination control register intc 706 ocdm on-chip debug mode register ? 777 osts oscillation stabilization time selection register standby 729 p0 port 0 register port 91 p0nfc tip00 noise elimination control register tmp 307 p1 port 1 register port 93 p1nfc tip01 noise elimination control register tmp 307 appendix b register index preliminary user?s manual u17702ej1v0ud 845 (5/10) symbol name unit page p3 port 3 register port 96 p3h port 3 register h port 96 p3l port 3 register l port 96 p4 port 4 register port 101 p5 port 5 register port 104 p6 port 6 register port 109 p6h port 6 register h port 109 p6l port 6 register l port 109 p7 port 7 register port 113 p7h port 7 register h port 113 p7l port 7 register l port 113 p8 port 8 register port 114 p9 port 9 register port 118 p9h port 9 register h port 118 p9l port 9 register l port 118 pc program counter cpu 44 pcc processor clock control register cg 215 pcd port cd register port 126 pcm port cm register port 127 pcs port cs register port 129 pct port ct register port 131 pdh port dh register port 133 pdl port dl register port 136 pdlh port dl register h port 136 pdll port dl register l port 136 pf3h port 3 function register h port 98 pf4 port 4 function register port 103 pf5 port 5 function register port 106 pf6 port 6 function register port 111 pf6h port 6 function register h port 111 pf6l port 6 function register l port 111 pf8 port 8 function register port 115 pf9h port 9 function register port 121 pfc3 port 3 function control register port 98 pfc4 port 4 function control register port 102 pfc5 port 5 function control register port 107 pfc6h port 6 function control register port 111 pfc8 port 8 function control register port 116 pfc9 port 9 function control register port 121 pfc9h port 9 function control register h port 121 pfc9l port 9 function control register l port 121 pfce3 port 3 function control expansion register port 98 pfm power fail comparison mode register adc 466 pft power fail comparison threshold register adc 466 appendix b register index preliminary user?s manual u17702ej1v0ud 846 (6/10) symbol name unit page pic0 interrupt control register intc 697 pic1 interrupt control register intc 697 pic2 interrupt control register intc 697 pic3 interrupt control register intc 697 pic4 interrupt control register intc 697 pic5 interrupt control register intc 697 pic6 interrupt control register intc 697 pic7 interrupt control register intc 697 pllctl pll control register cg 220, 455 pm0 port 0 mode register port 91 pm1 port 1 mode register port 93 pm3 port 3 mode register port 96 pm3h port 3 mode register h port 96 pm3l port 3 mode register l port 96 pm4 port 4 mode register port 101 pm5 port 5 mode register port 105 pm6 port 6 mode register port 109 pm6h port 6 mode register h port 109 pm6l port 6 mode register l port 109 pm8 port 8 mode register port 114 pm9 port 9 mode register port 118 pm9h port 9 mode register h port 118 pm9l port 9 mode register l port 118 pmc0 port 0 mode control register port 92 pmc3 port 3 mode control register port 97 pmc3h port 3 mode control register h port 97 pmc3l port 3 mode control register l port 97 pmc4 port 4 mode control register port 102 pmc5 port 5 mode control register port 106 pmc6 port 6 mode control register port 110 pmc6h port 6 mode control register h port 110 pmc6l port 6 mode control register l port 110 pmc8 port 8 mode control register port 115 pmc9 port 9 mode control register port 118 pmc9h port 9 mode control register h port 118 pmc9l port 9 mode control register l port 118 pmccm port cm mode control register port 128 pmccs port cs mode control register port 130 pmcct port ct mode control register port 132 pmcd port cd mode register port 126 pmcdh port dh mode control register port 134 pmcdl port dl mode control register port 137 pmcdlh port dl mode control register h port 137 pmcdll port dl mode control register l port 137 appendix b register index preliminary user?s manual u17702ej1v0ud 847 (7/10) symbol name unit page pmcm port cm mode register port 127 pmcs port cs mode register port 129 pmct port ct mode register port 131 pmdh port dh mode register port 133 pmdl port dl mode register port 136 pmdlh port dl mode register h port 136 pmdll port dl mode register l port 136 prcmd command register cpu 77 prm00 prescaler mode register 00 tm0 321 prm01 prescaler mode register 01 tm0 321 prm02 prescaler mode register 02 tm0 321 prm03 prescaler mode register 03 tm0 321 prm04 prescaler mode register 04 tm0 321 prm05 prescaler mode register 05 tm0 321 prscm interval timer brg compare register cg 430 prsm interval timer brg mode register cg 429 psc power save control register standby 727 psmr power save mode register standby 728 psw program status word cpu 48 pu0 pull-up resistor option register 0 port 92 pu1 pull-up resistor option register 1 port 94 pu3 pull-up resistor option register 3 port 100 pu4 pull-up resistor option register 4 port 103 pu5 pull-up resistor option register 5 port 107 pu6 pull-up resistor option register 6 port 112 pu6h pull-up resistor option register 6h port 112 pu6l pull-up resistor option register 6l port 112 pu8 pull-up resistor option register 8 port 116 pu9 pull-up resistor option register 9 port 124 pu9h pull-up resistor option register 9h port 124 pu9l pull-up resistor option register 9l port 124 pucd pull-up resistor option register cd port 126 pucm pull-up resistor option register cm port 128 pucs pull-up resistor option register cs port 130 puct pull-up resistor option register ct port 132 pudh pull-up resistor option register dh port 134 pudl pull-up resistor option register dl port 137 pudll pull-up resistor option register dll port 137 pudlh pull-up resistor option register dlh port 137 r0 to r31 general-purpose registers cpu 44 rtbh0 real-time output buffer register h0 rtp 449 rtbh1 real-time output buffer register h1 rtp 449 rtbl0 real-time output buffer register l0 rtp 449 rtbl1 real-time output buffer register l1 rtp 449 appendix b register index preliminary user?s manual u17702ej1v0ud 848 (8/10) symbol name unit page rtpc0 real-time output port control register 0 rtp 451 rtpc1 real-time output port control register 1 rtp 451 rtpm0 real-time output port mode register 0 rtp 450 rtpm1 real-time output port mode register 1 rtp 450 rxb0 receive buffer register 0 uart 499 rxb1 receive buffer register 1 uart 499 rxb2 receive buffer register 2 uart 499 selcnt1 selector operation control register 1 tm0 322 sio00 serial i/o shift register 0 csi0 533 sio00l serial i/o shift register 0l csi0 533 sio01 serial i/o shift register 1 csi0 533 sio01l serial i/o shift register 1l csi0 533 sio02 serial i/o shift register 2 csi0 533 sio02l serial i/o shift register 2l csi0 533 sioa0 serial i/o shift register a0 csia 552 sioa1 serial i/o shift register a1 csia 552 sirb0 clocked serial interface re ceive buffer register 0 csi0 529 sirb0l clocked serial interface re ceive buffer register 0l csi0 529 sirb1 clocked serial interface re ceive buffer register 1 csi0 529 sirb1l clocked serial interface re ceive buffer register 1l csi0 529 sirb2 clocked serial interface re ceive buffer register 2 csi0 529 sirb2l clocked serial interface re ceive buffer register 2l csi0 529 sirbe0 clocked serial interface read- only receive buffer register 0 csi0 530 sirbe0l clocked serial interface read- only receive buffer register 0l csi0 530 sirbe1 clocked serial interface read- only receive buffer register 1 csi0 530 sirbe1l clocked serial interface read- only receive buffer register 1l csi0 530 sirbe2 clocked serial interface read- only receive buffer register 2 csi0 530 sirbe2l clocked serial interface read- only receive buffer register 2l csi0 530 sotb0 clocked serial interface tr ansmit buffer register 0 csi0 531 sotb0l clocked serial interface tr ansmit buffer register 0l csi0 531 sotb1 clocked serial interface tr ansmit buffer register 1 csi0 531 sotb1l clocked serial interface tr ansmit buffer register 1l csi0 531 sotb2 clocked serial interface tr ansmit buffer register 2 csi0 531 sotb2l clocked serial interface tr ansmit buffer register 2l csi0 531 sotbf0 clocked serial interface init ial transmit buffer register 0 csi0 532 sotbf0l clocked serial interface init ial transmit buffer register 0l csi0 532 sotbf1 clocked serial interface init ial transmit buffer register 1 csi0 532 sotbf1l clocked serial interface init ial transmit buffer register 1l csi0 532 sotbf2 clocked serial interface init ial transmit buffer register 2 csi0 532 sotbf2l clocked serial interface init ial transmit buffer register 2l csi0 532 sreic0 interrupt control register intc 697 sreic1 interrupt control register intc 697 sreic2 interrupt control register intc 697 sric0 interrupt control register intc 697 appendix b register index preliminary user?s manual u17702ej1v0ud 849 (9/10) symbol name unit page sric1 interrupt control register intc 697 sric2 interrupt control register intc 697 stic0 interrupt control register intc 697 stic1 interrupt control register intc 697 stic2 interrupt control register intc 697 sva0 slave address register 0 i 2 c 600 sva1 slave address register 1 i 2 c 600 sys system status register cpu 77 tcl50 timer clock selection register 50 tm5 388 tcl51 timer clock selection register 51 tm5 388 tm00 16-bit timer counter 00 tm0 312 tm01 16-bit timer counter 01 tm0 312 tm02 16-bit timer counter 02 tm0 312 tm03 16-bit timer counter 03 tm0 312 tm04 16-bit timer counter 04 tm0 312 tm05 16-bit timer counter 05 tm0 312 tm0ic00 interrupt control register intc 697 tm0ic01 interrupt control register intc 697 tm0ic10 interrupt control register intc 697 tm0ic11 interrupt control register intc 697 tm0ic20 interrupt control register intc 697 tm0ic21 interrupt control register intc 697 tm0ic30 interrupt control register intc 697 tm0ic31 interrupt control register intc 697 tm0ic40 interrupt control register intc 697 tm0ic41 interrupt control register intc 697 tm0ic50 interrupt control register intc 697 tm0ic51 interrupt control register intc 697 tm5 16-bit timer counter 5 tm5 386 tm50 8-bit timer counter 50 tm5 386 tm51 8-bit timer counter 51 tm5 386 tm5ic0 interrupt control register intc 697 tm5ic1 interrupt control register intc 697 tmc00 16-bit timer mode control register 00 tm0 316 tmc01 16-bit timer mode control register 01 tm0 316 tmc02 16-bit timer mode control register 02 tm0 316 tmc03 16-bit timer mode control register 03 tm0 316 tmc04 16-bit timer mode control register 04 tm0 316 tmc05 16-bit timer mode control register 05 tm0 316 tmc50 8-bit timer mode control register 50 tm5 389 tmc51 8-bit timer mode control register 51 tm5 389 tmcyc0 8-bit timer h carrier control register 0 tmh 410 tmcyc1 8-bit timer h carrier control register 1 tmh 410 tmhic0 interrupt control register intc 697 appendix b register index preliminary user?s manual u17702ej1v0ud 850 (10/10) symbol name unit page tmhic1 interrupt control register intc 697 tmhmd0 8-bit timer h mode register 0 tmh 408 tmhmd1 8-bit timer h mode register 1 tmh 409 toc00 16-bit timer output control register 00 tm0 319 toc01 16-bit timer output control register 01 tm0 319 toc02 16-bit timer output control register 02 tm0 319 toc03 16-bit timer output control register 03 tm0 319 toc04 16-bit timer output control register 04 tm0 319 toc05 16-bit timer output control register 05 tm0 319 tp0ccic0 interrupt control register intc 697 tp0ccic1 interrupt control register intc 697 tp0ccr0 tmp0 capture/compare register 0 tmp 231 tp0ccr1 tmp0 capture/compare register 1 tmp 233 tp0cnt tmp0 counter read buffer register tmp 235 tp0ctl0 tmp0 control register 0 tmp 225 tp0ctl1 tmp0 control register 1 tmp 226 tp0ioc0 tmp0 i/o control register 0 tmp 227 tp0ioc1 tmp0 i/o control register 1 tmp 228 tp0ioc2 tmp0 i/o control register 2 tmp 229 tp0opt0 tmp0 option register 0 tmp 230 tp0ovic interrupt control register intc 697 txb0 transmit buffer register 0 uart 500 txb1 transmit buffer register 1 uart 500 txb2 transmit buffer register 2 uart 500 vswc system wait control register cpu 79 wdcs watchdog timer clock se lection register wdt 440 wdt1ic interrupt control register intc 697 wdte watchdog timer enable register wdt 446 wdtm1 watchdog timer mode register 1 wdt 441, 704 wdtm2 watchdog timer mode register 2 wdt 445 wtic interrupt control register intc 697 wtiic interrupt control register intc 697 wtm watch timer operation mode register wt 433 |
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